2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/signal.h>
12 #include <linux/module.h>
13 #include <asm/branch.h>
15 #include <asm/cpu-features.h>
17 #include <asm/fpu_emulator.h>
19 #include <asm/ptrace.h>
20 #include <asm/uaccess.h>
23 * Calculate and return exception PC in case of branch delay slot
24 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
26 int __isa_exception_epc(struct pt_regs
*regs
)
29 long epc
= regs
->cp0_epc
;
31 /* Calculate exception PC in branch delay slot. */
32 if (__get_user(inst
, (u16 __user
*) msk_isa16_mode(epc
))) {
33 /* This should never happen because delay slot was checked. */
34 force_sig(SIGSEGV
, current
);
38 if (((union mips16e_instruction
)inst
).ri
.opcode
43 } else if (mm_insn_16bit(inst
))
51 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
52 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
54 int __mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
55 unsigned long *contpc
)
57 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
65 switch (insn
.mm_i_format
.opcode
) {
67 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
69 switch (insn
.mm_i_format
.simmediate
>>
70 MM_POOL32A_MINOR_SHIFT
) {
75 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
76 regs
->regs
[insn
.mm_i_format
.rt
] =
80 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
86 switch (insn
.mm_i_format
.rt
) {
89 regs
->regs
[31] = regs
->cp0_epc
+
94 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
95 *contpc
= regs
->cp0_epc
+
97 (insn
.mm_i_format
.simmediate
<< 1);
99 *contpc
= regs
->cp0_epc
+
101 dec_insn
.next_pc_inc
;
105 regs
->regs
[31] = regs
->cp0_epc
+
107 dec_insn
.next_pc_inc
;
110 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
111 *contpc
= regs
->cp0_epc
+
113 (insn
.mm_i_format
.simmediate
<< 1);
115 *contpc
= regs
->cp0_epc
+
117 dec_insn
.next_pc_inc
;
120 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
121 *contpc
= regs
->cp0_epc
+
123 (insn
.mm_i_format
.simmediate
<< 1);
125 *contpc
= regs
->cp0_epc
+
127 dec_insn
.next_pc_inc
;
130 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
131 *contpc
= regs
->cp0_epc
+
133 (insn
.mm_i_format
.simmediate
<< 1);
135 *contpc
= regs
->cp0_epc
+
137 dec_insn
.next_pc_inc
;
147 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
149 fcr31
= current
->thread
.fpu
.fcr31
;
155 bit
= (insn
.mm_i_format
.rs
>> 2);
158 if (fcr31
& (1 << bit
))
159 *contpc
= regs
->cp0_epc
+
161 (insn
.mm_i_format
.simmediate
<< 1);
163 *contpc
= regs
->cp0_epc
+
164 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
169 switch (insn
.mm_i_format
.rt
) {
172 regs
->regs
[31] = regs
->cp0_epc
+
173 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
176 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
181 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
182 *contpc
= regs
->cp0_epc
+
184 (insn
.mm_b1_format
.simmediate
<< 1);
186 *contpc
= regs
->cp0_epc
+
187 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
190 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
191 *contpc
= regs
->cp0_epc
+
193 (insn
.mm_b1_format
.simmediate
<< 1);
195 *contpc
= regs
->cp0_epc
+
196 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
199 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
200 (insn
.mm_b0_format
.simmediate
<< 1);
203 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
204 regs
->regs
[insn
.mm_i_format
.rt
])
205 *contpc
= regs
->cp0_epc
+
207 (insn
.mm_i_format
.simmediate
<< 1);
209 *contpc
= regs
->cp0_epc
+
211 dec_insn
.next_pc_inc
;
214 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
215 regs
->regs
[insn
.mm_i_format
.rt
])
216 *contpc
= regs
->cp0_epc
+
218 (insn
.mm_i_format
.simmediate
<< 1);
220 *contpc
= regs
->cp0_epc
+
221 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
224 regs
->regs
[31] = regs
->cp0_epc
+
225 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
226 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
229 *contpc
|= (insn
.j_format
.target
<< 2);
233 regs
->regs
[31] = regs
->cp0_epc
+
234 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
237 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
240 *contpc
|= (insn
.j_format
.target
<< 1);
241 set_isa16_mode(*contpc
);
248 * Compute return address and emulate branch in microMIPS mode after an
249 * exception only. It does not handle compact branches/jumps and cannot
250 * be used in interrupt context. (Compact branches/jumps do not cause
253 int __microMIPS_compute_return_epc(struct pt_regs
*regs
)
258 unsigned long contpc
;
259 struct mm_decoded_insn mminsn
= { 0 };
261 mminsn
.micro_mips_mode
= 1;
263 /* This load never faults. */
264 pc16
= (unsigned short __user
*)msk_isa16_mode(regs
->cp0_epc
);
265 __get_user(halfword
, pc16
);
267 contpc
= regs
->cp0_epc
+ 2;
268 word
= ((unsigned int)halfword
<< 16);
271 if (!mm_insn_16bit(halfword
)) {
272 __get_user(halfword
, pc16
);
274 contpc
= regs
->cp0_epc
+ 4;
280 if (get_user(halfword
, pc16
))
282 mminsn
.next_pc_inc
= 2;
283 word
= ((unsigned int)halfword
<< 16);
285 if (!mm_insn_16bit(halfword
)) {
287 if (get_user(halfword
, pc16
))
289 mminsn
.next_pc_inc
= 4;
292 mminsn
.next_insn
= word
;
294 mm_isBranchInstr(regs
, mminsn
, &contpc
);
296 regs
->cp0_epc
= contpc
;
301 force_sig(SIGSEGV
, current
);
306 * Compute return address and emulate branch in MIPS16e mode after an
307 * exception only. It does not handle compact branches/jumps and cannot
308 * be used in interrupt context. (Compact branches/jumps do not cause
311 int __MIPS16e_compute_return_epc(struct pt_regs
*regs
)
314 union mips16e_instruction inst
;
321 /* Read the instruction. */
322 addr
= (u16 __user
*)msk_isa16_mode(epc
);
323 if (__get_user(inst
.full
, addr
)) {
324 force_sig(SIGSEGV
, current
);
328 switch (inst
.ri
.opcode
) {
329 case MIPS16e_extend_op
:
334 * JAL and JALX in MIPS16e mode
338 if (__get_user(inst2
, addr
)) {
339 force_sig(SIGSEGV
, current
);
342 fullinst
= ((unsigned)inst
.full
<< 16) | inst2
;
343 regs
->regs
[31] = epc
+ 6;
348 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
350 * ......TARGET[15:0].................TARGET[20:16]...........
351 * ......TARGET[25:21]
354 ((fullinst
& 0xffff) << 2) | ((fullinst
& 0x3e00000) >> 3) |
355 ((fullinst
& 0x1f0000) << 7);
357 set_isa16_mode(epc
); /* Set ISA mode bit. */
365 if (inst
.rr
.func
== MIPS16e_jr_func
) {
368 regs
->cp0_epc
= regs
->regs
[31];
371 regs
->regs
[reg16to32
[inst
.rr
.rx
]];
375 regs
->regs
[31] = epc
+ 2;
377 regs
->regs
[31] = epc
+ 4;
385 * All other cases have no branch delay slot and are 16-bits.
386 * Branches do not cause an exception.
394 * __compute_return_epc_for_insn - Computes the return address and do emulate
395 * branch simulation, if required.
397 * @regs: Pointer to pt_regs
398 * @insn: branch instruction to decode
399 * @returns: -EFAULT on error and forces SIGBUS, and on success
400 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
401 * evaluating the branch.
403 * MIPS R6 Compact branches and forbidden slots:
404 * Compact branches do not throw exceptions because they do
405 * not have delay slots. The forbidden slot instruction ($PC+4)
406 * is only executed if the branch was not taken. Otherwise the
407 * forbidden slot is skipped entirely. This means that the
408 * only possible reason to be here because of a MIPS R6 compact
409 * branch instruction is that the forbidden slot has thrown one.
410 * In that case the branch was not taken, so the EPC can be safely
413 int __compute_return_epc_for_insn(struct pt_regs
*regs
,
414 union mips_instruction insn
)
416 unsigned int bit
, fcr31
, dspcontrol
, reg
;
417 long epc
= regs
->cp0_epc
;
420 switch (insn
.i_format
.opcode
) {
422 * jr and jalr are in r_format format.
425 switch (insn
.r_format
.func
) {
427 regs
->regs
[insn
.r_format
.rd
] = epc
+ 8;
430 if (NO_R6EMU
&& insn
.r_format
.func
== jr_op
)
432 regs
->cp0_epc
= regs
->regs
[insn
.r_format
.rs
];
438 * This group contains:
439 * bltz_op, bgez_op, bltzl_op, bgezl_op,
440 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
443 switch (insn
.i_format
.rt
) {
448 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0) {
449 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
450 if (insn
.i_format
.rt
== bltzl_op
)
451 ret
= BRANCH_LIKELY_TAKEN
;
461 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0) {
462 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
463 if (insn
.i_format
.rt
== bgezl_op
)
464 ret
= BRANCH_LIKELY_TAKEN
;
472 if (NO_R6EMU
&& (insn
.i_format
.rs
||
473 insn
.i_format
.rt
== bltzall_op
)) {
477 regs
->regs
[31] = epc
+ 8;
479 * OK we are here either because we hit a NAL
480 * instruction or because we are emulating an
481 * old bltzal{,l} one. Lets figure out what the
484 if (!insn
.i_format
.rs
) {
486 * NAL or BLTZAL with rs == 0
487 * Doesn't matter if we are R6 or not. The
491 (insn
.i_format
.simmediate
<< 2);
494 /* Now do the real thing for non-R6 BLTZAL{,L} */
495 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0) {
496 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
497 if (insn
.i_format
.rt
== bltzall_op
)
498 ret
= BRANCH_LIKELY_TAKEN
;
506 if (NO_R6EMU
&& (insn
.i_format
.rs
||
507 insn
.i_format
.rt
== bgezall_op
)) {
511 regs
->regs
[31] = epc
+ 8;
513 * OK we are here either because we hit a BAL
514 * instruction or because we are emulating an
515 * old bgezal{,l} one. Lets figure out what the
518 if (!insn
.i_format
.rs
) {
520 * BAL or BGEZAL with rs == 0
521 * Doesn't matter if we are R6 or not. The
525 (insn
.i_format
.simmediate
<< 2);
528 /* Now do the real thing for non-R6 BGEZAL{,L} */
529 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0) {
530 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
531 if (insn
.i_format
.rt
== bgezall_op
)
532 ret
= BRANCH_LIKELY_TAKEN
;
542 dspcontrol
= rddsp(0x01);
544 if (dspcontrol
>= 32) {
545 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
554 * These are unconditional and in j_format.
557 regs
->regs
[31] = regs
->cp0_epc
+ 8;
562 epc
|= (insn
.j_format
.target
<< 2);
564 if (insn
.i_format
.opcode
== jalx_op
)
565 set_isa16_mode(regs
->cp0_epc
);
569 * These are conditional and in i_format.
575 if (regs
->regs
[insn
.i_format
.rs
] ==
576 regs
->regs
[insn
.i_format
.rt
]) {
577 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
578 if (insn
.i_format
.opcode
== beql_op
)
579 ret
= BRANCH_LIKELY_TAKEN
;
589 if (regs
->regs
[insn
.i_format
.rs
] !=
590 regs
->regs
[insn
.i_format
.rt
]) {
591 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
592 if (insn
.i_format
.opcode
== bnel_op
)
593 ret
= BRANCH_LIKELY_TAKEN
;
599 case blezl_op
: /* not really i_format */
604 * Compact branches for R6 for the
605 * blez and blezl opcodes.
606 * BLEZ | rs = 0 | rt != 0 == BLEZALC
607 * BLEZ | rs = rt != 0 == BGEZALC
608 * BLEZ | rs != 0 | rt != 0 == BGEUC
609 * BLEZL | rs = 0 | rt != 0 == BLEZC
610 * BLEZL | rs = rt != 0 == BGEZC
611 * BLEZL | rs != 0 | rt != 0 == BGEC
613 * For real BLEZ{,L}, rt is always 0.
616 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
617 if ((insn
.i_format
.opcode
== blez_op
) &&
618 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
619 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
620 regs
->regs
[31] = epc
+ 4;
624 /* rt field assumed to be zero */
625 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0) {
626 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
627 if (insn
.i_format
.opcode
== blezl_op
)
628 ret
= BRANCH_LIKELY_TAKEN
;
639 * Compact branches for R6 for the
640 * bgtz and bgtzl opcodes.
641 * BGTZ | rs = 0 | rt != 0 == BGTZALC
642 * BGTZ | rs = rt != 0 == BLTZALC
643 * BGTZ | rs != 0 | rt != 0 == BLTUC
644 * BGTZL | rs = 0 | rt != 0 == BGTZC
645 * BGTZL | rs = rt != 0 == BLTZC
646 * BGTZL | rs != 0 | rt != 0 == BLTC
648 * *ZALC varint for BGTZ &&& rt != 0
649 * For real GTZ{,L}, rt is always 0.
651 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
652 if ((insn
.i_format
.opcode
== blez_op
) &&
653 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
654 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
655 regs
->regs
[31] = epc
+ 4;
660 /* rt field assumed to be zero */
661 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0) {
662 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
663 if (insn
.i_format
.opcode
== bgtzl_op
)
664 ret
= BRANCH_LIKELY_TAKEN
;
671 * And now the FPA/cp1 branch instructions.
674 if (cpu_has_mips_r6
&&
675 ((insn
.i_format
.rs
== bc1eqz_op
) ||
676 (insn
.i_format
.rs
== bc1nez_op
))) {
677 if (!used_math()) { /* First time FPU user */
679 if (ret
&& NO_R6EMU
) {
686 lose_fpu(1); /* Save FPU state for the emulator. */
687 reg
= insn
.i_format
.rt
;
689 switch (insn
.i_format
.rs
) {
692 if (get_fpr32(¤t
->thread
.fpu
.fpr
[reg
], 0)
698 if (!(get_fpr32(¤t
->thread
.fpu
.fpr
[reg
], 0)
706 (insn
.i_format
.simmediate
<< 2);
716 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
718 fcr31
= current
->thread
.fpu
.fcr31
;
721 bit
= (insn
.i_format
.rt
>> 2);
724 switch (insn
.i_format
.rt
& 3) {
727 if (~fcr31
& (1 << bit
)) {
729 (insn
.i_format
.simmediate
<< 2);
730 if (insn
.i_format
.rt
== 2)
731 ret
= BRANCH_LIKELY_TAKEN
;
739 if (fcr31
& (1 << bit
)) {
741 (insn
.i_format
.simmediate
<< 2);
742 if (insn
.i_format
.rt
== 3)
743 ret
= BRANCH_LIKELY_TAKEN
;
751 #ifdef CONFIG_CPU_CAVIUM_OCTEON
752 case lwc2_op
: /* This is bbit0 on Octeon */
753 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
755 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
760 case ldc2_op
: /* This is bbit032 on Octeon */
761 if ((regs
->regs
[insn
.i_format
.rs
] &
762 (1ull<<(insn
.i_format
.rt
+32))) == 0)
763 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
768 case swc2_op
: /* This is bbit1 on Octeon */
769 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
770 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
775 case sdc2_op
: /* This is bbit132 on Octeon */
776 if (regs
->regs
[insn
.i_format
.rs
] &
777 (1ull<<(insn
.i_format
.rt
+32)))
778 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
789 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current
->comm
);
790 force_sig(SIGBUS
, current
);
793 pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
795 force_sig(SIGILL
, current
);
798 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn
);
800 int __compute_return_epc(struct pt_regs
*regs
)
802 unsigned int __user
*addr
;
804 union mips_instruction insn
;
811 * Read the instruction
813 addr
= (unsigned int __user
*) epc
;
814 if (__get_user(insn
.word
, addr
)) {
815 force_sig(SIGSEGV
, current
);
819 return __compute_return_epc_for_insn(regs
, insn
);
822 printk("%s: unaligned epc - sending SIGBUS.\n", current
->comm
);
823 force_sig(SIGBUS
, current
);