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Merge remote-tracking branch 'spi/topic/core' into spi-next
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-type.h>
24 #include <asm/fpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mipsmtregs.h>
27 #include <asm/msa.h>
28 #include <asm/watch.h>
29 #include <asm/elf.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/spram.h>
32 #include <asm/uaccess.h>
33
34 static int mips_fpu_disabled;
35
36 static int __init fpu_disable(char *s)
37 {
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42 }
43
44 __setup("nofpu", fpu_disable);
45
46 int mips_dsp_disabled;
47
48 static int __init dsp_disable(char *s)
49 {
50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
51 mips_dsp_disabled = 1;
52
53 return 1;
54 }
55
56 __setup("nodsp", dsp_disable);
57
58 static int mips_htw_disabled;
59
60 static int __init htw_disable(char *s)
61 {
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68 }
69
70 __setup("nohtw", htw_disable);
71
72 static inline void check_errata(void)
73 {
74 struct cpuinfo_mips *c = &current_cpu_data;
75
76 switch (current_cpu_type()) {
77 case CPU_34K:
78 /*
79 * Erratum "RPS May Cause Incorrect Instruction Execution"
80 * This code only handles VPE0, any SMP/RTOS code
81 * making use of VPE1 will be responsable for that VPE.
82 */
83 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
84 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
85 break;
86 default:
87 break;
88 }
89 }
90
91 void __init check_bugs32(void)
92 {
93 check_errata();
94 }
95
96 /*
97 * Probe whether cpu has config register by trying to play with
98 * alternate cache bit and see whether it matters.
99 * It's used by cpu_probe to distinguish between R3000A and R3081.
100 */
101 static inline int cpu_has_confreg(void)
102 {
103 #ifdef CONFIG_CPU_R3000
104 extern unsigned long r3k_cache_size(unsigned long);
105 unsigned long size1, size2;
106 unsigned long cfg = read_c0_conf();
107
108 size1 = r3k_cache_size(ST0_ISC);
109 write_c0_conf(cfg ^ R30XX_CONF_AC);
110 size2 = r3k_cache_size(ST0_ISC);
111 write_c0_conf(cfg);
112 return size1 != size2;
113 #else
114 return 0;
115 #endif
116 }
117
118 static inline void set_elf_platform(int cpu, const char *plat)
119 {
120 if (cpu == 0)
121 __elf_platform = plat;
122 }
123
124 /*
125 * Get the FPU Implementation/Revision.
126 */
127 static inline unsigned long cpu_get_fpu_id(void)
128 {
129 unsigned long tmp, fpu_id;
130
131 tmp = read_c0_status();
132 __enable_fpu(FPU_AS_IS);
133 fpu_id = read_32bit_cp1_register(CP1_REVISION);
134 write_c0_status(tmp);
135 return fpu_id;
136 }
137
138 /*
139 * Check the CPU has an FPU the official way.
140 */
141 static inline int __cpu_has_fpu(void)
142 {
143 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
144 }
145
146 static inline unsigned long cpu_get_msa_id(void)
147 {
148 unsigned long status, msa_id;
149
150 status = read_c0_status();
151 __enable_fpu(FPU_64BIT);
152 enable_msa();
153 msa_id = read_msa_ir();
154 disable_msa();
155 write_c0_status(status);
156 return msa_id;
157 }
158
159 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
160 {
161 #ifdef __NEED_VMBITS_PROBE
162 write_c0_entryhi(0x3fffffffffffe000ULL);
163 back_to_back_c0_hazard();
164 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
165 #endif
166 }
167
168 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
169 {
170 switch (isa) {
171 case MIPS_CPU_ISA_M64R2:
172 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
173 case MIPS_CPU_ISA_M64R1:
174 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
175 case MIPS_CPU_ISA_V:
176 c->isa_level |= MIPS_CPU_ISA_V;
177 case MIPS_CPU_ISA_IV:
178 c->isa_level |= MIPS_CPU_ISA_IV;
179 case MIPS_CPU_ISA_III:
180 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
181 break;
182
183 case MIPS_CPU_ISA_M32R2:
184 c->isa_level |= MIPS_CPU_ISA_M32R2;
185 case MIPS_CPU_ISA_M32R1:
186 c->isa_level |= MIPS_CPU_ISA_M32R1;
187 case MIPS_CPU_ISA_II:
188 c->isa_level |= MIPS_CPU_ISA_II;
189 break;
190 }
191 }
192
193 static char unknown_isa[] = KERN_ERR \
194 "Unsupported ISA type, c0.config0: %d.";
195
196 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
197 {
198
199 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
200
201 /*
202 * 0 = All TLBWR instructions go to FTLB
203 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
204 * FTLB and 1 goes to the VTLB.
205 * 2 = 7:1: As above with 7:1 ratio.
206 * 3 = 3:1: As above with 3:1 ratio.
207 *
208 * Use the linear midpoint as the probability threshold.
209 */
210 if (probability >= 12)
211 return 1;
212 else if (probability >= 6)
213 return 2;
214 else
215 /*
216 * So FTLB is less than 4 times bigger than VTLB.
217 * A 3:1 ratio can still be useful though.
218 */
219 return 3;
220 }
221
222 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
223 {
224 unsigned int config6;
225
226 /* It's implementation dependent how the FTLB can be enabled */
227 switch (c->cputype) {
228 case CPU_PROAPTIV:
229 case CPU_P5600:
230 /* proAptiv & related cores use Config6 to enable the FTLB */
231 config6 = read_c0_config6();
232 /* Clear the old probability value */
233 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
234 if (enable)
235 /* Enable FTLB */
236 write_c0_config6(config6 |
237 (calculate_ftlb_probability(c)
238 << MIPS_CONF6_FTLBP_SHIFT)
239 | MIPS_CONF6_FTLBEN);
240 else
241 /* Disable FTLB */
242 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
243 back_to_back_c0_hazard();
244 break;
245 }
246 }
247
248 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
249 {
250 unsigned int config0;
251 int isa;
252
253 config0 = read_c0_config();
254
255 /*
256 * Look for Standard TLB or Dual VTLB and FTLB
257 */
258 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
259 (((config0 & MIPS_CONF_MT) >> 7) == 4))
260 c->options |= MIPS_CPU_TLB;
261
262 isa = (config0 & MIPS_CONF_AT) >> 13;
263 switch (isa) {
264 case 0:
265 switch ((config0 & MIPS_CONF_AR) >> 10) {
266 case 0:
267 set_isa(c, MIPS_CPU_ISA_M32R1);
268 break;
269 case 1:
270 set_isa(c, MIPS_CPU_ISA_M32R2);
271 break;
272 default:
273 goto unknown;
274 }
275 break;
276 case 2:
277 switch ((config0 & MIPS_CONF_AR) >> 10) {
278 case 0:
279 set_isa(c, MIPS_CPU_ISA_M64R1);
280 break;
281 case 1:
282 set_isa(c, MIPS_CPU_ISA_M64R2);
283 break;
284 default:
285 goto unknown;
286 }
287 break;
288 default:
289 goto unknown;
290 }
291
292 return config0 & MIPS_CONF_M;
293
294 unknown:
295 panic(unknown_isa, config0);
296 }
297
298 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
299 {
300 unsigned int config1;
301
302 config1 = read_c0_config1();
303
304 if (config1 & MIPS_CONF1_MD)
305 c->ases |= MIPS_ASE_MDMX;
306 if (config1 & MIPS_CONF1_WR)
307 c->options |= MIPS_CPU_WATCH;
308 if (config1 & MIPS_CONF1_CA)
309 c->ases |= MIPS_ASE_MIPS16;
310 if (config1 & MIPS_CONF1_EP)
311 c->options |= MIPS_CPU_EJTAG;
312 if (config1 & MIPS_CONF1_FP) {
313 c->options |= MIPS_CPU_FPU;
314 c->options |= MIPS_CPU_32FPR;
315 }
316 if (cpu_has_tlb) {
317 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
318 c->tlbsizevtlb = c->tlbsize;
319 c->tlbsizeftlbsets = 0;
320 }
321
322 return config1 & MIPS_CONF_M;
323 }
324
325 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
326 {
327 unsigned int config2;
328
329 config2 = read_c0_config2();
330
331 if (config2 & MIPS_CONF2_SL)
332 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
333
334 return config2 & MIPS_CONF_M;
335 }
336
337 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
338 {
339 unsigned int config3;
340
341 config3 = read_c0_config3();
342
343 if (config3 & MIPS_CONF3_SM) {
344 c->ases |= MIPS_ASE_SMARTMIPS;
345 c->options |= MIPS_CPU_RIXI;
346 }
347 if (config3 & MIPS_CONF3_RXI)
348 c->options |= MIPS_CPU_RIXI;
349 if (config3 & MIPS_CONF3_DSP)
350 c->ases |= MIPS_ASE_DSP;
351 if (config3 & MIPS_CONF3_DSP2P)
352 c->ases |= MIPS_ASE_DSP2P;
353 if (config3 & MIPS_CONF3_VINT)
354 c->options |= MIPS_CPU_VINT;
355 if (config3 & MIPS_CONF3_VEIC)
356 c->options |= MIPS_CPU_VEIC;
357 if (config3 & MIPS_CONF3_MT)
358 c->ases |= MIPS_ASE_MIPSMT;
359 if (config3 & MIPS_CONF3_ULRI)
360 c->options |= MIPS_CPU_ULRI;
361 if (config3 & MIPS_CONF3_ISA)
362 c->options |= MIPS_CPU_MICROMIPS;
363 if (config3 & MIPS_CONF3_VZ)
364 c->ases |= MIPS_ASE_VZ;
365 if (config3 & MIPS_CONF3_SC)
366 c->options |= MIPS_CPU_SEGMENTS;
367 if (config3 & MIPS_CONF3_MSA)
368 c->ases |= MIPS_ASE_MSA;
369 /* Only tested on 32-bit cores */
370 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
371 c->options |= MIPS_CPU_HTW;
372
373 return config3 & MIPS_CONF_M;
374 }
375
376 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
377 {
378 unsigned int config4;
379 unsigned int newcf4;
380 unsigned int mmuextdef;
381 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
382
383 config4 = read_c0_config4();
384
385 if (cpu_has_tlb) {
386 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
387 c->options |= MIPS_CPU_TLBINV;
388 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
389 switch (mmuextdef) {
390 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
391 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
392 c->tlbsizevtlb = c->tlbsize;
393 break;
394 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
395 c->tlbsizevtlb +=
396 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
397 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
398 c->tlbsize = c->tlbsizevtlb;
399 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
400 /* fall through */
401 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
402 newcf4 = (config4 & ~ftlb_page) |
403 (page_size_ftlb(mmuextdef) <<
404 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
405 write_c0_config4(newcf4);
406 back_to_back_c0_hazard();
407 config4 = read_c0_config4();
408 if (config4 != newcf4) {
409 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
410 PAGE_SIZE, config4);
411 /* Switch FTLB off */
412 set_ftlb_enable(c, 0);
413 break;
414 }
415 c->tlbsizeftlbsets = 1 <<
416 ((config4 & MIPS_CONF4_FTLBSETS) >>
417 MIPS_CONF4_FTLBSETS_SHIFT);
418 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
419 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
420 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
421 break;
422 }
423 }
424
425 c->kscratch_mask = (config4 >> 16) & 0xff;
426
427 return config4 & MIPS_CONF_M;
428 }
429
430 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
431 {
432 unsigned int config5;
433
434 config5 = read_c0_config5();
435 config5 &= ~MIPS_CONF5_UFR;
436 write_c0_config5(config5);
437
438 if (config5 & MIPS_CONF5_EVA)
439 c->options |= MIPS_CPU_EVA;
440 if (config5 & MIPS_CONF5_MRP)
441 c->options |= MIPS_CPU_MAAR;
442
443 return config5 & MIPS_CONF_M;
444 }
445
446 static void decode_configs(struct cpuinfo_mips *c)
447 {
448 int ok;
449
450 /* MIPS32 or MIPS64 compliant CPU. */
451 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
452 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
453
454 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
455
456 /* Enable FTLB if present */
457 set_ftlb_enable(c, 1);
458
459 ok = decode_config0(c); /* Read Config registers. */
460 BUG_ON(!ok); /* Arch spec violation! */
461 if (ok)
462 ok = decode_config1(c);
463 if (ok)
464 ok = decode_config2(c);
465 if (ok)
466 ok = decode_config3(c);
467 if (ok)
468 ok = decode_config4(c);
469 if (ok)
470 ok = decode_config5(c);
471
472 mips_probe_watch_registers(c);
473
474 if (cpu_has_rixi) {
475 /* Enable the RIXI exceptions */
476 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
477 back_to_back_c0_hazard();
478 /* Verify the IEC bit is set */
479 if (read_c0_pagegrain() & PG_IEC)
480 c->options |= MIPS_CPU_RIXIEX;
481 }
482
483 #ifndef CONFIG_MIPS_CPS
484 if (cpu_has_mips_r2) {
485 c->core = get_ebase_cpunum();
486 if (cpu_has_mipsmt)
487 c->core >>= fls(core_nvpes()) - 1;
488 }
489 #endif
490 }
491
492 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
493 | MIPS_CPU_COUNTER)
494
495 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
496 {
497 switch (c->processor_id & PRID_IMP_MASK) {
498 case PRID_IMP_R2000:
499 c->cputype = CPU_R2000;
500 __cpu_name[cpu] = "R2000";
501 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
502 MIPS_CPU_NOFPUEX;
503 if (__cpu_has_fpu())
504 c->options |= MIPS_CPU_FPU;
505 c->tlbsize = 64;
506 break;
507 case PRID_IMP_R3000:
508 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
509 if (cpu_has_confreg()) {
510 c->cputype = CPU_R3081E;
511 __cpu_name[cpu] = "R3081";
512 } else {
513 c->cputype = CPU_R3000A;
514 __cpu_name[cpu] = "R3000A";
515 }
516 } else {
517 c->cputype = CPU_R3000;
518 __cpu_name[cpu] = "R3000";
519 }
520 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
521 MIPS_CPU_NOFPUEX;
522 if (__cpu_has_fpu())
523 c->options |= MIPS_CPU_FPU;
524 c->tlbsize = 64;
525 break;
526 case PRID_IMP_R4000:
527 if (read_c0_config() & CONF_SC) {
528 if ((c->processor_id & PRID_REV_MASK) >=
529 PRID_REV_R4400) {
530 c->cputype = CPU_R4400PC;
531 __cpu_name[cpu] = "R4400PC";
532 } else {
533 c->cputype = CPU_R4000PC;
534 __cpu_name[cpu] = "R4000PC";
535 }
536 } else {
537 int cca = read_c0_config() & CONF_CM_CMASK;
538 int mc;
539
540 /*
541 * SC and MC versions can't be reliably told apart,
542 * but only the latter support coherent caching
543 * modes so assume the firmware has set the KSEG0
544 * coherency attribute reasonably (if uncached, we
545 * assume SC).
546 */
547 switch (cca) {
548 case CONF_CM_CACHABLE_CE:
549 case CONF_CM_CACHABLE_COW:
550 case CONF_CM_CACHABLE_CUW:
551 mc = 1;
552 break;
553 default:
554 mc = 0;
555 break;
556 }
557 if ((c->processor_id & PRID_REV_MASK) >=
558 PRID_REV_R4400) {
559 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
560 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
561 } else {
562 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
563 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
564 }
565 }
566
567 set_isa(c, MIPS_CPU_ISA_III);
568 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
569 MIPS_CPU_WATCH | MIPS_CPU_VCE |
570 MIPS_CPU_LLSC;
571 c->tlbsize = 48;
572 break;
573 case PRID_IMP_VR41XX:
574 set_isa(c, MIPS_CPU_ISA_III);
575 c->options = R4K_OPTS;
576 c->tlbsize = 32;
577 switch (c->processor_id & 0xf0) {
578 case PRID_REV_VR4111:
579 c->cputype = CPU_VR4111;
580 __cpu_name[cpu] = "NEC VR4111";
581 break;
582 case PRID_REV_VR4121:
583 c->cputype = CPU_VR4121;
584 __cpu_name[cpu] = "NEC VR4121";
585 break;
586 case PRID_REV_VR4122:
587 if ((c->processor_id & 0xf) < 0x3) {
588 c->cputype = CPU_VR4122;
589 __cpu_name[cpu] = "NEC VR4122";
590 } else {
591 c->cputype = CPU_VR4181A;
592 __cpu_name[cpu] = "NEC VR4181A";
593 }
594 break;
595 case PRID_REV_VR4130:
596 if ((c->processor_id & 0xf) < 0x4) {
597 c->cputype = CPU_VR4131;
598 __cpu_name[cpu] = "NEC VR4131";
599 } else {
600 c->cputype = CPU_VR4133;
601 c->options |= MIPS_CPU_LLSC;
602 __cpu_name[cpu] = "NEC VR4133";
603 }
604 break;
605 default:
606 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
607 c->cputype = CPU_VR41XX;
608 __cpu_name[cpu] = "NEC Vr41xx";
609 break;
610 }
611 break;
612 case PRID_IMP_R4300:
613 c->cputype = CPU_R4300;
614 __cpu_name[cpu] = "R4300";
615 set_isa(c, MIPS_CPU_ISA_III);
616 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
617 MIPS_CPU_LLSC;
618 c->tlbsize = 32;
619 break;
620 case PRID_IMP_R4600:
621 c->cputype = CPU_R4600;
622 __cpu_name[cpu] = "R4600";
623 set_isa(c, MIPS_CPU_ISA_III);
624 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
625 MIPS_CPU_LLSC;
626 c->tlbsize = 48;
627 break;
628 #if 0
629 case PRID_IMP_R4650:
630 /*
631 * This processor doesn't have an MMU, so it's not
632 * "real easy" to run Linux on it. It is left purely
633 * for documentation. Commented out because it shares
634 * it's c0_prid id number with the TX3900.
635 */
636 c->cputype = CPU_R4650;
637 __cpu_name[cpu] = "R4650";
638 set_isa(c, MIPS_CPU_ISA_III);
639 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
640 c->tlbsize = 48;
641 break;
642 #endif
643 case PRID_IMP_TX39:
644 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
645
646 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
647 c->cputype = CPU_TX3927;
648 __cpu_name[cpu] = "TX3927";
649 c->tlbsize = 64;
650 } else {
651 switch (c->processor_id & PRID_REV_MASK) {
652 case PRID_REV_TX3912:
653 c->cputype = CPU_TX3912;
654 __cpu_name[cpu] = "TX3912";
655 c->tlbsize = 32;
656 break;
657 case PRID_REV_TX3922:
658 c->cputype = CPU_TX3922;
659 __cpu_name[cpu] = "TX3922";
660 c->tlbsize = 64;
661 break;
662 }
663 }
664 break;
665 case PRID_IMP_R4700:
666 c->cputype = CPU_R4700;
667 __cpu_name[cpu] = "R4700";
668 set_isa(c, MIPS_CPU_ISA_III);
669 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
670 MIPS_CPU_LLSC;
671 c->tlbsize = 48;
672 break;
673 case PRID_IMP_TX49:
674 c->cputype = CPU_TX49XX;
675 __cpu_name[cpu] = "R49XX";
676 set_isa(c, MIPS_CPU_ISA_III);
677 c->options = R4K_OPTS | MIPS_CPU_LLSC;
678 if (!(c->processor_id & 0x08))
679 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
680 c->tlbsize = 48;
681 break;
682 case PRID_IMP_R5000:
683 c->cputype = CPU_R5000;
684 __cpu_name[cpu] = "R5000";
685 set_isa(c, MIPS_CPU_ISA_IV);
686 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
687 MIPS_CPU_LLSC;
688 c->tlbsize = 48;
689 break;
690 case PRID_IMP_R5432:
691 c->cputype = CPU_R5432;
692 __cpu_name[cpu] = "R5432";
693 set_isa(c, MIPS_CPU_ISA_IV);
694 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
695 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
696 c->tlbsize = 48;
697 break;
698 case PRID_IMP_R5500:
699 c->cputype = CPU_R5500;
700 __cpu_name[cpu] = "R5500";
701 set_isa(c, MIPS_CPU_ISA_IV);
702 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
703 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
704 c->tlbsize = 48;
705 break;
706 case PRID_IMP_NEVADA:
707 c->cputype = CPU_NEVADA;
708 __cpu_name[cpu] = "Nevada";
709 set_isa(c, MIPS_CPU_ISA_IV);
710 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
711 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
712 c->tlbsize = 48;
713 break;
714 case PRID_IMP_R6000:
715 c->cputype = CPU_R6000;
716 __cpu_name[cpu] = "R6000";
717 set_isa(c, MIPS_CPU_ISA_II);
718 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
719 MIPS_CPU_LLSC;
720 c->tlbsize = 32;
721 break;
722 case PRID_IMP_R6000A:
723 c->cputype = CPU_R6000A;
724 __cpu_name[cpu] = "R6000A";
725 set_isa(c, MIPS_CPU_ISA_II);
726 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
727 MIPS_CPU_LLSC;
728 c->tlbsize = 32;
729 break;
730 case PRID_IMP_RM7000:
731 c->cputype = CPU_RM7000;
732 __cpu_name[cpu] = "RM7000";
733 set_isa(c, MIPS_CPU_ISA_IV);
734 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
735 MIPS_CPU_LLSC;
736 /*
737 * Undocumented RM7000: Bit 29 in the info register of
738 * the RM7000 v2.0 indicates if the TLB has 48 or 64
739 * entries.
740 *
741 * 29 1 => 64 entry JTLB
742 * 0 => 48 entry JTLB
743 */
744 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
745 break;
746 case PRID_IMP_R8000:
747 c->cputype = CPU_R8000;
748 __cpu_name[cpu] = "RM8000";
749 set_isa(c, MIPS_CPU_ISA_IV);
750 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
751 MIPS_CPU_FPU | MIPS_CPU_32FPR |
752 MIPS_CPU_LLSC;
753 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
754 break;
755 case PRID_IMP_R10000:
756 c->cputype = CPU_R10000;
757 __cpu_name[cpu] = "R10000";
758 set_isa(c, MIPS_CPU_ISA_IV);
759 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
760 MIPS_CPU_FPU | MIPS_CPU_32FPR |
761 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
762 MIPS_CPU_LLSC;
763 c->tlbsize = 64;
764 break;
765 case PRID_IMP_R12000:
766 c->cputype = CPU_R12000;
767 __cpu_name[cpu] = "R12000";
768 set_isa(c, MIPS_CPU_ISA_IV);
769 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
770 MIPS_CPU_FPU | MIPS_CPU_32FPR |
771 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
772 MIPS_CPU_LLSC;
773 c->tlbsize = 64;
774 break;
775 case PRID_IMP_R14000:
776 c->cputype = CPU_R14000;
777 __cpu_name[cpu] = "R14000";
778 set_isa(c, MIPS_CPU_ISA_IV);
779 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
780 MIPS_CPU_FPU | MIPS_CPU_32FPR |
781 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
782 MIPS_CPU_LLSC;
783 c->tlbsize = 64;
784 break;
785 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
786 switch (c->processor_id & PRID_REV_MASK) {
787 case PRID_REV_LOONGSON2E:
788 c->cputype = CPU_LOONGSON2;
789 __cpu_name[cpu] = "ICT Loongson-2";
790 set_elf_platform(cpu, "loongson2e");
791 set_isa(c, MIPS_CPU_ISA_III);
792 break;
793 case PRID_REV_LOONGSON2F:
794 c->cputype = CPU_LOONGSON2;
795 __cpu_name[cpu] = "ICT Loongson-2";
796 set_elf_platform(cpu, "loongson2f");
797 set_isa(c, MIPS_CPU_ISA_III);
798 break;
799 case PRID_REV_LOONGSON3A:
800 c->cputype = CPU_LOONGSON3;
801 __cpu_name[cpu] = "ICT Loongson-3";
802 set_elf_platform(cpu, "loongson3a");
803 set_isa(c, MIPS_CPU_ISA_M64R1);
804 break;
805 case PRID_REV_LOONGSON3B_R1:
806 case PRID_REV_LOONGSON3B_R2:
807 c->cputype = CPU_LOONGSON3;
808 __cpu_name[cpu] = "ICT Loongson-3";
809 set_elf_platform(cpu, "loongson3b");
810 set_isa(c, MIPS_CPU_ISA_M64R1);
811 break;
812 }
813
814 c->options = R4K_OPTS |
815 MIPS_CPU_FPU | MIPS_CPU_LLSC |
816 MIPS_CPU_32FPR;
817 c->tlbsize = 64;
818 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
819 break;
820 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
821 decode_configs(c);
822
823 c->cputype = CPU_LOONGSON1;
824
825 switch (c->processor_id & PRID_REV_MASK) {
826 case PRID_REV_LOONGSON1B:
827 __cpu_name[cpu] = "Loongson 1B";
828 break;
829 }
830
831 break;
832 }
833 }
834
835 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
836 {
837 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
838 switch (c->processor_id & PRID_IMP_MASK) {
839 case PRID_IMP_4KC:
840 c->cputype = CPU_4KC;
841 c->writecombine = _CACHE_UNCACHED;
842 __cpu_name[cpu] = "MIPS 4Kc";
843 break;
844 case PRID_IMP_4KEC:
845 case PRID_IMP_4KECR2:
846 c->cputype = CPU_4KEC;
847 c->writecombine = _CACHE_UNCACHED;
848 __cpu_name[cpu] = "MIPS 4KEc";
849 break;
850 case PRID_IMP_4KSC:
851 case PRID_IMP_4KSD:
852 c->cputype = CPU_4KSC;
853 c->writecombine = _CACHE_UNCACHED;
854 __cpu_name[cpu] = "MIPS 4KSc";
855 break;
856 case PRID_IMP_5KC:
857 c->cputype = CPU_5KC;
858 c->writecombine = _CACHE_UNCACHED;
859 __cpu_name[cpu] = "MIPS 5Kc";
860 break;
861 case PRID_IMP_5KE:
862 c->cputype = CPU_5KE;
863 c->writecombine = _CACHE_UNCACHED;
864 __cpu_name[cpu] = "MIPS 5KE";
865 break;
866 case PRID_IMP_20KC:
867 c->cputype = CPU_20KC;
868 c->writecombine = _CACHE_UNCACHED;
869 __cpu_name[cpu] = "MIPS 20Kc";
870 break;
871 case PRID_IMP_24K:
872 c->cputype = CPU_24K;
873 c->writecombine = _CACHE_UNCACHED;
874 __cpu_name[cpu] = "MIPS 24Kc";
875 break;
876 case PRID_IMP_24KE:
877 c->cputype = CPU_24K;
878 c->writecombine = _CACHE_UNCACHED;
879 __cpu_name[cpu] = "MIPS 24KEc";
880 break;
881 case PRID_IMP_25KF:
882 c->cputype = CPU_25KF;
883 c->writecombine = _CACHE_UNCACHED;
884 __cpu_name[cpu] = "MIPS 25Kc";
885 break;
886 case PRID_IMP_34K:
887 c->cputype = CPU_34K;
888 c->writecombine = _CACHE_UNCACHED;
889 __cpu_name[cpu] = "MIPS 34Kc";
890 break;
891 case PRID_IMP_74K:
892 c->cputype = CPU_74K;
893 c->writecombine = _CACHE_UNCACHED;
894 __cpu_name[cpu] = "MIPS 74Kc";
895 break;
896 case PRID_IMP_M14KC:
897 c->cputype = CPU_M14KC;
898 c->writecombine = _CACHE_UNCACHED;
899 __cpu_name[cpu] = "MIPS M14Kc";
900 break;
901 case PRID_IMP_M14KEC:
902 c->cputype = CPU_M14KEC;
903 c->writecombine = _CACHE_UNCACHED;
904 __cpu_name[cpu] = "MIPS M14KEc";
905 break;
906 case PRID_IMP_1004K:
907 c->cputype = CPU_1004K;
908 c->writecombine = _CACHE_UNCACHED;
909 __cpu_name[cpu] = "MIPS 1004Kc";
910 break;
911 case PRID_IMP_1074K:
912 c->cputype = CPU_1074K;
913 c->writecombine = _CACHE_UNCACHED;
914 __cpu_name[cpu] = "MIPS 1074Kc";
915 break;
916 case PRID_IMP_INTERAPTIV_UP:
917 c->cputype = CPU_INTERAPTIV;
918 __cpu_name[cpu] = "MIPS interAptiv";
919 break;
920 case PRID_IMP_INTERAPTIV_MP:
921 c->cputype = CPU_INTERAPTIV;
922 __cpu_name[cpu] = "MIPS interAptiv (multi)";
923 break;
924 case PRID_IMP_PROAPTIV_UP:
925 c->cputype = CPU_PROAPTIV;
926 __cpu_name[cpu] = "MIPS proAptiv";
927 break;
928 case PRID_IMP_PROAPTIV_MP:
929 c->cputype = CPU_PROAPTIV;
930 __cpu_name[cpu] = "MIPS proAptiv (multi)";
931 break;
932 case PRID_IMP_P5600:
933 c->cputype = CPU_P5600;
934 __cpu_name[cpu] = "MIPS P5600";
935 break;
936 case PRID_IMP_M5150:
937 c->cputype = CPU_M5150;
938 __cpu_name[cpu] = "MIPS M5150";
939 break;
940 }
941
942 decode_configs(c);
943
944 spram_config();
945 }
946
947 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
948 {
949 decode_configs(c);
950 switch (c->processor_id & PRID_IMP_MASK) {
951 case PRID_IMP_AU1_REV1:
952 case PRID_IMP_AU1_REV2:
953 c->cputype = CPU_ALCHEMY;
954 switch ((c->processor_id >> 24) & 0xff) {
955 case 0:
956 __cpu_name[cpu] = "Au1000";
957 break;
958 case 1:
959 __cpu_name[cpu] = "Au1500";
960 break;
961 case 2:
962 __cpu_name[cpu] = "Au1100";
963 break;
964 case 3:
965 __cpu_name[cpu] = "Au1550";
966 break;
967 case 4:
968 __cpu_name[cpu] = "Au1200";
969 if ((c->processor_id & PRID_REV_MASK) == 2)
970 __cpu_name[cpu] = "Au1250";
971 break;
972 case 5:
973 __cpu_name[cpu] = "Au1210";
974 break;
975 default:
976 __cpu_name[cpu] = "Au1xxx";
977 break;
978 }
979 break;
980 }
981 }
982
983 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
984 {
985 decode_configs(c);
986
987 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
988 switch (c->processor_id & PRID_IMP_MASK) {
989 case PRID_IMP_SB1:
990 c->cputype = CPU_SB1;
991 __cpu_name[cpu] = "SiByte SB1";
992 /* FPU in pass1 is known to have issues. */
993 if ((c->processor_id & PRID_REV_MASK) < 0x02)
994 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
995 break;
996 case PRID_IMP_SB1A:
997 c->cputype = CPU_SB1A;
998 __cpu_name[cpu] = "SiByte SB1A";
999 break;
1000 }
1001 }
1002
1003 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1004 {
1005 decode_configs(c);
1006 switch (c->processor_id & PRID_IMP_MASK) {
1007 case PRID_IMP_SR71000:
1008 c->cputype = CPU_SR71000;
1009 __cpu_name[cpu] = "Sandcraft SR71000";
1010 c->scache.ways = 8;
1011 c->tlbsize = 64;
1012 break;
1013 }
1014 }
1015
1016 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1017 {
1018 decode_configs(c);
1019 switch (c->processor_id & PRID_IMP_MASK) {
1020 case PRID_IMP_PR4450:
1021 c->cputype = CPU_PR4450;
1022 __cpu_name[cpu] = "Philips PR4450";
1023 set_isa(c, MIPS_CPU_ISA_M32R1);
1024 break;
1025 }
1026 }
1027
1028 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1029 {
1030 decode_configs(c);
1031 switch (c->processor_id & PRID_IMP_MASK) {
1032 case PRID_IMP_BMIPS32_REV4:
1033 case PRID_IMP_BMIPS32_REV8:
1034 c->cputype = CPU_BMIPS32;
1035 __cpu_name[cpu] = "Broadcom BMIPS32";
1036 set_elf_platform(cpu, "bmips32");
1037 break;
1038 case PRID_IMP_BMIPS3300:
1039 case PRID_IMP_BMIPS3300_ALT:
1040 case PRID_IMP_BMIPS3300_BUG:
1041 c->cputype = CPU_BMIPS3300;
1042 __cpu_name[cpu] = "Broadcom BMIPS3300";
1043 set_elf_platform(cpu, "bmips3300");
1044 break;
1045 case PRID_IMP_BMIPS43XX: {
1046 int rev = c->processor_id & PRID_REV_MASK;
1047
1048 if (rev >= PRID_REV_BMIPS4380_LO &&
1049 rev <= PRID_REV_BMIPS4380_HI) {
1050 c->cputype = CPU_BMIPS4380;
1051 __cpu_name[cpu] = "Broadcom BMIPS4380";
1052 set_elf_platform(cpu, "bmips4380");
1053 } else {
1054 c->cputype = CPU_BMIPS4350;
1055 __cpu_name[cpu] = "Broadcom BMIPS4350";
1056 set_elf_platform(cpu, "bmips4350");
1057 }
1058 break;
1059 }
1060 case PRID_IMP_BMIPS5000:
1061 c->cputype = CPU_BMIPS5000;
1062 __cpu_name[cpu] = "Broadcom BMIPS5000";
1063 set_elf_platform(cpu, "bmips5000");
1064 c->options |= MIPS_CPU_ULRI;
1065 break;
1066 }
1067 }
1068
1069 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1070 {
1071 decode_configs(c);
1072 switch (c->processor_id & PRID_IMP_MASK) {
1073 case PRID_IMP_CAVIUM_CN38XX:
1074 case PRID_IMP_CAVIUM_CN31XX:
1075 case PRID_IMP_CAVIUM_CN30XX:
1076 c->cputype = CPU_CAVIUM_OCTEON;
1077 __cpu_name[cpu] = "Cavium Octeon";
1078 goto platform;
1079 case PRID_IMP_CAVIUM_CN58XX:
1080 case PRID_IMP_CAVIUM_CN56XX:
1081 case PRID_IMP_CAVIUM_CN50XX:
1082 case PRID_IMP_CAVIUM_CN52XX:
1083 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1084 __cpu_name[cpu] = "Cavium Octeon+";
1085 platform:
1086 set_elf_platform(cpu, "octeon");
1087 break;
1088 case PRID_IMP_CAVIUM_CN61XX:
1089 case PRID_IMP_CAVIUM_CN63XX:
1090 case PRID_IMP_CAVIUM_CN66XX:
1091 case PRID_IMP_CAVIUM_CN68XX:
1092 case PRID_IMP_CAVIUM_CNF71XX:
1093 c->cputype = CPU_CAVIUM_OCTEON2;
1094 __cpu_name[cpu] = "Cavium Octeon II";
1095 set_elf_platform(cpu, "octeon2");
1096 break;
1097 case PRID_IMP_CAVIUM_CN70XX:
1098 case PRID_IMP_CAVIUM_CN78XX:
1099 c->cputype = CPU_CAVIUM_OCTEON3;
1100 __cpu_name[cpu] = "Cavium Octeon III";
1101 set_elf_platform(cpu, "octeon3");
1102 break;
1103 default:
1104 printk(KERN_INFO "Unknown Octeon chip!\n");
1105 c->cputype = CPU_UNKNOWN;
1106 break;
1107 }
1108 }
1109
1110 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1111 {
1112 decode_configs(c);
1113 /* JZRISC does not implement the CP0 counter. */
1114 c->options &= ~MIPS_CPU_COUNTER;
1115 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1116 switch (c->processor_id & PRID_IMP_MASK) {
1117 case PRID_IMP_JZRISC:
1118 c->cputype = CPU_JZRISC;
1119 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1120 __cpu_name[cpu] = "Ingenic JZRISC";
1121 break;
1122 default:
1123 panic("Unknown Ingenic Processor ID!");
1124 break;
1125 }
1126 }
1127
1128 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1129 {
1130 decode_configs(c);
1131
1132 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1133 c->cputype = CPU_ALCHEMY;
1134 __cpu_name[cpu] = "Au1300";
1135 /* following stuff is not for Alchemy */
1136 return;
1137 }
1138
1139 c->options = (MIPS_CPU_TLB |
1140 MIPS_CPU_4KEX |
1141 MIPS_CPU_COUNTER |
1142 MIPS_CPU_DIVEC |
1143 MIPS_CPU_WATCH |
1144 MIPS_CPU_EJTAG |
1145 MIPS_CPU_LLSC);
1146
1147 switch (c->processor_id & PRID_IMP_MASK) {
1148 case PRID_IMP_NETLOGIC_XLP2XX:
1149 case PRID_IMP_NETLOGIC_XLP9XX:
1150 case PRID_IMP_NETLOGIC_XLP5XX:
1151 c->cputype = CPU_XLP;
1152 __cpu_name[cpu] = "Broadcom XLPII";
1153 break;
1154
1155 case PRID_IMP_NETLOGIC_XLP8XX:
1156 case PRID_IMP_NETLOGIC_XLP3XX:
1157 c->cputype = CPU_XLP;
1158 __cpu_name[cpu] = "Netlogic XLP";
1159 break;
1160
1161 case PRID_IMP_NETLOGIC_XLR732:
1162 case PRID_IMP_NETLOGIC_XLR716:
1163 case PRID_IMP_NETLOGIC_XLR532:
1164 case PRID_IMP_NETLOGIC_XLR308:
1165 case PRID_IMP_NETLOGIC_XLR532C:
1166 case PRID_IMP_NETLOGIC_XLR516C:
1167 case PRID_IMP_NETLOGIC_XLR508C:
1168 case PRID_IMP_NETLOGIC_XLR308C:
1169 c->cputype = CPU_XLR;
1170 __cpu_name[cpu] = "Netlogic XLR";
1171 break;
1172
1173 case PRID_IMP_NETLOGIC_XLS608:
1174 case PRID_IMP_NETLOGIC_XLS408:
1175 case PRID_IMP_NETLOGIC_XLS404:
1176 case PRID_IMP_NETLOGIC_XLS208:
1177 case PRID_IMP_NETLOGIC_XLS204:
1178 case PRID_IMP_NETLOGIC_XLS108:
1179 case PRID_IMP_NETLOGIC_XLS104:
1180 case PRID_IMP_NETLOGIC_XLS616B:
1181 case PRID_IMP_NETLOGIC_XLS608B:
1182 case PRID_IMP_NETLOGIC_XLS416B:
1183 case PRID_IMP_NETLOGIC_XLS412B:
1184 case PRID_IMP_NETLOGIC_XLS408B:
1185 case PRID_IMP_NETLOGIC_XLS404B:
1186 c->cputype = CPU_XLR;
1187 __cpu_name[cpu] = "Netlogic XLS";
1188 break;
1189
1190 default:
1191 pr_info("Unknown Netlogic chip id [%02x]!\n",
1192 c->processor_id);
1193 c->cputype = CPU_XLR;
1194 break;
1195 }
1196
1197 if (c->cputype == CPU_XLP) {
1198 set_isa(c, MIPS_CPU_ISA_M64R2);
1199 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1200 /* This will be updated again after all threads are woken up */
1201 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1202 } else {
1203 set_isa(c, MIPS_CPU_ISA_M64R1);
1204 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1205 }
1206 c->kscratch_mask = 0xf;
1207 }
1208
1209 #ifdef CONFIG_64BIT
1210 /* For use by uaccess.h */
1211 u64 __ua_limit;
1212 EXPORT_SYMBOL(__ua_limit);
1213 #endif
1214
1215 const char *__cpu_name[NR_CPUS];
1216 const char *__elf_platform;
1217
1218 void cpu_probe(void)
1219 {
1220 struct cpuinfo_mips *c = &current_cpu_data;
1221 unsigned int cpu = smp_processor_id();
1222
1223 c->processor_id = PRID_IMP_UNKNOWN;
1224 c->fpu_id = FPIR_IMP_NONE;
1225 c->cputype = CPU_UNKNOWN;
1226 c->writecombine = _CACHE_UNCACHED;
1227
1228 c->processor_id = read_c0_prid();
1229 switch (c->processor_id & PRID_COMP_MASK) {
1230 case PRID_COMP_LEGACY:
1231 cpu_probe_legacy(c, cpu);
1232 break;
1233 case PRID_COMP_MIPS:
1234 cpu_probe_mips(c, cpu);
1235 break;
1236 case PRID_COMP_ALCHEMY:
1237 cpu_probe_alchemy(c, cpu);
1238 break;
1239 case PRID_COMP_SIBYTE:
1240 cpu_probe_sibyte(c, cpu);
1241 break;
1242 case PRID_COMP_BROADCOM:
1243 cpu_probe_broadcom(c, cpu);
1244 break;
1245 case PRID_COMP_SANDCRAFT:
1246 cpu_probe_sandcraft(c, cpu);
1247 break;
1248 case PRID_COMP_NXP:
1249 cpu_probe_nxp(c, cpu);
1250 break;
1251 case PRID_COMP_CAVIUM:
1252 cpu_probe_cavium(c, cpu);
1253 break;
1254 case PRID_COMP_INGENIC:
1255 cpu_probe_ingenic(c, cpu);
1256 break;
1257 case PRID_COMP_NETLOGIC:
1258 cpu_probe_netlogic(c, cpu);
1259 break;
1260 }
1261
1262 BUG_ON(!__cpu_name[cpu]);
1263 BUG_ON(c->cputype == CPU_UNKNOWN);
1264
1265 /*
1266 * Platform code can force the cpu type to optimize code
1267 * generation. In that case be sure the cpu type is correctly
1268 * manually setup otherwise it could trigger some nasty bugs.
1269 */
1270 BUG_ON(current_cpu_type() != c->cputype);
1271
1272 if (mips_fpu_disabled)
1273 c->options &= ~MIPS_CPU_FPU;
1274
1275 if (mips_dsp_disabled)
1276 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1277
1278 if (mips_htw_disabled) {
1279 c->options &= ~MIPS_CPU_HTW;
1280 write_c0_pwctl(read_c0_pwctl() &
1281 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1282 }
1283
1284 if (c->options & MIPS_CPU_FPU) {
1285 c->fpu_id = cpu_get_fpu_id();
1286
1287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1288 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1289 if (c->fpu_id & MIPS_FPIR_3D)
1290 c->ases |= MIPS_ASE_MIPS3D;
1291 }
1292 }
1293
1294 if (cpu_has_mips_r2) {
1295 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1296 /* R2 has Performance Counter Interrupt indicator */
1297 c->options |= MIPS_CPU_PCI;
1298 }
1299 else
1300 c->srsets = 1;
1301
1302 if (cpu_has_msa) {
1303 c->msa_id = cpu_get_msa_id();
1304 WARN(c->msa_id & MSA_IR_WRPF,
1305 "Vector register partitioning unimplemented!");
1306 }
1307
1308 cpu_probe_vmbits(c);
1309
1310 #ifdef CONFIG_64BIT
1311 if (cpu == 0)
1312 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1313 #endif
1314 }
1315
1316 void cpu_report(void)
1317 {
1318 struct cpuinfo_mips *c = &current_cpu_data;
1319
1320 pr_info("CPU%d revision is: %08x (%s)\n",
1321 smp_processor_id(), c->processor_id, cpu_name_string());
1322 if (c->options & MIPS_CPU_FPU)
1323 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1324 if (cpu_has_msa)
1325 pr_info("MSA revision is: %08x\n", c->msa_id);
1326 }
Linux kernel - Deliverables
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