2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003, 2004 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
32 void (*cpu_wait
)(void) = NULL
;
34 static void r3081_wait(void)
36 unsigned long cfg
= read_c0_conf();
37 write_c0_conf(cfg
| R30XX_CONF_HALT
);
40 static void r39xx_wait(void)
42 unsigned long cfg
= read_c0_conf();
43 write_c0_conf(cfg
| TX39_CONF_HALT
);
46 static void r4k_wait(void)
48 __asm__(".set\tmips3\n\t"
53 /* The Au1xxx wait is available only if using 32khz counter or
54 * external timer source, but specifically not CP0 Counter. */
57 static void au1k_wait(void)
59 /* using the wait instruction makes CP0 counter unusable */
60 __asm__(".set mips3\n\t"
61 "cache 0x14, 0(%0)\n\t"
62 "cache 0x14, 32(%0)\n\t"
74 static int __initdata nowait
= 0;
76 int __init
wait_disable(char *s
)
83 __setup("nowait", wait_disable
);
85 static inline void check_wait(void)
87 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
89 printk("Checking for 'wait' instruction... ");
91 printk (" disabled.\n");
98 cpu_wait
= r3081_wait
;
99 printk(" available.\n");
102 cpu_wait
= r39xx_wait
;
103 printk(" available.\n");
106 /* case CPU_R4300: */
126 printk(" available.\n");
133 if (allow_au1k_wait
) {
134 cpu_wait
= au1k_wait
;
135 printk(" available.\n");
137 printk(" unavailable.\n");
140 printk(" unavailable.\n");
145 void __init
check_bugs32(void)
151 * Probe whether cpu has config register by trying to play with
152 * alternate cache bit and see whether it matters.
153 * It's used by cpu_probe to distinguish between R3000A and R3081.
155 static inline int cpu_has_confreg(void)
157 #ifdef CONFIG_CPU_R3000
158 extern unsigned long r3k_cache_size(unsigned long);
159 unsigned long size1
, size2
;
160 unsigned long cfg
= read_c0_conf();
162 size1
= r3k_cache_size(ST0_ISC
);
163 write_c0_conf(cfg
^ R30XX_CONF_AC
);
164 size2
= r3k_cache_size(ST0_ISC
);
166 return size1
!= size2
;
173 * Get the FPU Implementation/Revision.
175 static inline unsigned long cpu_get_fpu_id(void)
177 unsigned long tmp
, fpu_id
;
179 tmp
= read_c0_status();
181 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
182 write_c0_status(tmp
);
187 * Check the CPU has an FPU the official way.
189 static inline int __cpu_has_fpu(void)
191 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
194 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
197 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
)
199 switch (c
->processor_id
& 0xff00) {
201 c
->cputype
= CPU_R2000
;
202 c
->isa_level
= MIPS_CPU_ISA_I
;
203 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_NOFPUEX
;
205 c
->options
|= MIPS_CPU_FPU
;
209 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
)
210 if (cpu_has_confreg())
211 c
->cputype
= CPU_R3081E
;
213 c
->cputype
= CPU_R3000A
;
215 c
->cputype
= CPU_R3000
;
216 c
->isa_level
= MIPS_CPU_ISA_I
;
217 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_NOFPUEX
;
219 c
->options
|= MIPS_CPU_FPU
;
223 if (read_c0_config() & CONF_SC
) {
224 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
225 c
->cputype
= CPU_R4400PC
;
227 c
->cputype
= CPU_R4000PC
;
229 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
230 c
->cputype
= CPU_R4400SC
;
232 c
->cputype
= CPU_R4000SC
;
235 c
->isa_level
= MIPS_CPU_ISA_III
;
236 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
237 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
241 case PRID_IMP_VR41XX
:
242 switch (c
->processor_id
& 0xf0) {
243 case PRID_REV_VR4111
:
244 c
->cputype
= CPU_VR4111
;
246 case PRID_REV_VR4121
:
247 c
->cputype
= CPU_VR4121
;
249 case PRID_REV_VR4122
:
250 if ((c
->processor_id
& 0xf) < 0x3)
251 c
->cputype
= CPU_VR4122
;
253 c
->cputype
= CPU_VR4181A
;
255 case PRID_REV_VR4130
:
256 if ((c
->processor_id
& 0xf) < 0x4)
257 c
->cputype
= CPU_VR4131
;
259 c
->cputype
= CPU_VR4133
;
262 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
263 c
->cputype
= CPU_VR41XX
;
266 c
->isa_level
= MIPS_CPU_ISA_III
;
267 c
->options
= R4K_OPTS
;
271 c
->cputype
= CPU_R4300
;
272 c
->isa_level
= MIPS_CPU_ISA_III
;
273 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
278 c
->cputype
= CPU_R4600
;
279 c
->isa_level
= MIPS_CPU_ISA_III
;
280 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
286 * This processor doesn't have an MMU, so it's not
287 * "real easy" to run Linux on it. It is left purely
288 * for documentation. Commented out because it shares
289 * it's c0_prid id number with the TX3900.
291 c
->cputype
= CPU_R4650
;
292 c
->isa_level
= MIPS_CPU_ISA_III
;
293 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
298 c
->isa_level
= MIPS_CPU_ISA_I
;
299 c
->options
= MIPS_CPU_TLB
;
301 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
302 c
->cputype
= CPU_TX3927
;
305 switch (c
->processor_id
& 0xff) {
306 case PRID_REV_TX3912
:
307 c
->cputype
= CPU_TX3912
;
310 case PRID_REV_TX3922
:
311 c
->cputype
= CPU_TX3922
;
315 c
->cputype
= CPU_UNKNOWN
;
321 c
->cputype
= CPU_R4700
;
322 c
->isa_level
= MIPS_CPU_ISA_III
;
323 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
328 c
->cputype
= CPU_TX49XX
;
329 c
->isa_level
= MIPS_CPU_ISA_III
;
330 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
331 if (!(c
->processor_id
& 0x08))
332 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
336 c
->cputype
= CPU_R5000
;
337 c
->isa_level
= MIPS_CPU_ISA_IV
;
338 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
343 c
->cputype
= CPU_R5432
;
344 c
->isa_level
= MIPS_CPU_ISA_IV
;
345 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
346 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
350 c
->cputype
= CPU_R5500
;
351 c
->isa_level
= MIPS_CPU_ISA_IV
;
352 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
353 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
356 case PRID_IMP_NEVADA
:
357 c
->cputype
= CPU_NEVADA
;
358 c
->isa_level
= MIPS_CPU_ISA_IV
;
359 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
360 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
364 c
->cputype
= CPU_R6000
;
365 c
->isa_level
= MIPS_CPU_ISA_II
;
366 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
370 case PRID_IMP_R6000A
:
371 c
->cputype
= CPU_R6000A
;
372 c
->isa_level
= MIPS_CPU_ISA_II
;
373 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
377 case PRID_IMP_RM7000
:
378 c
->cputype
= CPU_RM7000
;
379 c
->isa_level
= MIPS_CPU_ISA_IV
;
380 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
383 * Undocumented RM7000: Bit 29 in the info register of
384 * the RM7000 v2.0 indicates if the TLB has 48 or 64
387 * 29 1 => 64 entry JTLB
390 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
392 case PRID_IMP_RM9000
:
393 c
->cputype
= CPU_RM9000
;
394 c
->isa_level
= MIPS_CPU_ISA_IV
;
395 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
398 * Bit 29 in the info register of the RM9000
399 * indicates if the TLB has 48 or 64 entries.
401 * 29 1 => 64 entry JTLB
404 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
407 c
->cputype
= CPU_R8000
;
408 c
->isa_level
= MIPS_CPU_ISA_IV
;
409 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
410 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
412 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
414 case PRID_IMP_R10000
:
415 c
->cputype
= CPU_R10000
;
416 c
->isa_level
= MIPS_CPU_ISA_IV
;
417 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
418 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
419 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
423 case PRID_IMP_R12000
:
424 c
->cputype
= CPU_R12000
;
425 c
->isa_level
= MIPS_CPU_ISA_IV
;
426 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
427 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
428 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
435 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
437 unsigned int config0
;
440 config0
= read_c0_config();
442 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
443 c
->options
|= MIPS_CPU_TLB
| MIPS_CPU_4KTLB
;
444 isa
= (config0
& MIPS_CONF_AT
) >> 13;
447 c
->isa_level
= MIPS_CPU_ISA_M32
;
450 c
->isa_level
= MIPS_CPU_ISA_M64
;
453 panic("Unsupported ISA type, cp0.config0.at: %d.", isa
);
456 return config0
& MIPS_CONF_M
;
459 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
461 unsigned int config1
;
463 config1
= read_c0_config1();
465 if (config1
& MIPS_CONF1_MD
)
466 c
->ases
|= MIPS_ASE_MDMX
;
467 if (config1
& MIPS_CONF1_WR
)
468 c
->options
|= MIPS_CPU_WATCH
;
469 if (config1
& MIPS_CONF1_CA
)
470 c
->ases
|= MIPS_ASE_MIPS16
;
471 if (config1
& MIPS_CONF1_EP
)
472 c
->options
|= MIPS_CPU_EJTAG
;
473 if (config1
& MIPS_CONF1_FP
) {
474 c
->options
|= MIPS_CPU_FPU
;
475 c
->options
|= MIPS_CPU_32FPR
;
478 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
480 return config1
& MIPS_CONF_M
;
483 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
485 unsigned int config2
;
487 config2
= read_c0_config2();
489 if (config2
& MIPS_CONF2_SL
)
490 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
492 return config2
& MIPS_CONF_M
;
495 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
497 unsigned int config3
;
499 config3
= read_c0_config3();
501 if (config3
& MIPS_CONF3_SM
)
502 c
->ases
|= MIPS_ASE_SMARTMIPS
;
503 if (config3
& MIPS_CONF3_DSP
)
504 c
->ases
|= MIPS_ASE_DSP
;
505 if (config3
& MIPS_CONF3_VINT
)
506 c
->options
|= MIPS_CPU_VINT
;
507 if (config3
& MIPS_CONF3_VEIC
)
508 c
->options
|= MIPS_CPU_VEIC
;
509 if (config3
& MIPS_CONF3_MT
)
510 c
->ases
|= MIPS_ASE_MIPSMT
;
512 return config3
& MIPS_CONF_M
;
515 static inline void decode_configs(struct cpuinfo_mips
*c
)
517 /* MIPS32 or MIPS64 compliant CPU. */
518 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_COUNTER
| MIPS_CPU_DIVEC
|
519 MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
521 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
523 /* Read Config registers. */
524 if (!decode_config0(c
))
525 return; /* actually worth a panic() */
526 if (!decode_config1(c
))
528 if (!decode_config2(c
))
530 if (!decode_config3(c
))
534 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
)
537 switch (c
->processor_id
& 0xff00) {
539 c
->cputype
= CPU_4KC
;
542 c
->cputype
= CPU_4KEC
;
544 case PRID_IMP_4KECR2
:
545 c
->cputype
= CPU_4KEC
;
548 c
->cputype
= CPU_4KSC
;
551 c
->cputype
= CPU_5KC
;
554 c
->cputype
= CPU_20KC
;
558 c
->cputype
= CPU_24K
;
561 c
->cputype
= CPU_25KF
;
562 /* Probe for L2 cache */
563 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
566 c
->cputype
= CPU_34K
;
567 c
->isa_level
= MIPS_CPU_ISA_M32
;
572 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
)
575 switch (c
->processor_id
& 0xff00) {
576 case PRID_IMP_AU1_REV1
:
577 case PRID_IMP_AU1_REV2
:
578 switch ((c
->processor_id
>> 24) & 0xff) {
580 c
->cputype
= CPU_AU1000
;
583 c
->cputype
= CPU_AU1500
;
586 c
->cputype
= CPU_AU1100
;
589 c
->cputype
= CPU_AU1550
;
592 c
->cputype
= CPU_AU1200
;
595 panic("Unknown Au Core!");
602 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
)
605 switch (c
->processor_id
& 0xff00) {
607 c
->cputype
= CPU_SB1
;
608 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
609 /* FPU in pass1 is known to have issues. */
610 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
616 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
)
619 switch (c
->processor_id
& 0xff00) {
620 case PRID_IMP_SR71000
:
621 c
->cputype
= CPU_SR71000
;
628 static inline void cpu_probe_philips(struct cpuinfo_mips
*c
)
631 switch (c
->processor_id
& 0xff00) {
632 case PRID_IMP_PR4450
:
633 c
->cputype
= CPU_PR4450
;
634 c
->isa_level
= MIPS_CPU_ISA_M32
;
637 panic("Unknown Philips Core!"); /* REVISIT: die? */
643 __init
void cpu_probe(void)
645 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
647 c
->processor_id
= PRID_IMP_UNKNOWN
;
648 c
->fpu_id
= FPIR_IMP_NONE
;
649 c
->cputype
= CPU_UNKNOWN
;
651 c
->processor_id
= read_c0_prid();
652 switch (c
->processor_id
& 0xff0000) {
653 case PRID_COMP_LEGACY
:
659 case PRID_COMP_ALCHEMY
:
660 cpu_probe_alchemy(c
);
662 case PRID_COMP_SIBYTE
:
665 case PRID_COMP_SANDCRAFT
:
666 cpu_probe_sandcraft(c
);
668 case PRID_COMP_PHILIPS
:
669 cpu_probe_philips(c
);
672 c
->cputype
= CPU_UNKNOWN
;
674 if (c
->options
& MIPS_CPU_FPU
) {
675 c
->fpu_id
= cpu_get_fpu_id();
677 if (c
->isa_level
== MIPS_CPU_ISA_M32
||
678 c
->isa_level
== MIPS_CPU_ISA_M64
) {
679 if (c
->fpu_id
& MIPS_FPIR_3D
)
680 c
->ases
|= MIPS_ASE_MIPS3D
;
685 __init
void cpu_report(void)
687 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
689 printk("CPU revision is: %08x\n", c
->processor_id
);
690 if (c
->options
& MIPS_CPU_FPU
)
691 printk("FPU revision is: %08x\n", c
->fpu_id
);
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