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Merge tag 'iommu-updates-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-type.h>
24 #include <asm/fpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/watch.h>
27 #include <asm/elf.h>
28 #include <asm/spram.h>
29 #include <asm/uaccess.h>
30
31 static int mips_fpu_disabled;
32
33 static int __init fpu_disable(char *s)
34 {
35 cpu_data[0].options &= ~MIPS_CPU_FPU;
36 mips_fpu_disabled = 1;
37
38 return 1;
39 }
40
41 __setup("nofpu", fpu_disable);
42
43 int mips_dsp_disabled;
44
45 static int __init dsp_disable(char *s)
46 {
47 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
48 mips_dsp_disabled = 1;
49
50 return 1;
51 }
52
53 __setup("nodsp", dsp_disable);
54
55 static inline void check_errata(void)
56 {
57 struct cpuinfo_mips *c = &current_cpu_data;
58
59 switch (current_cpu_type()) {
60 case CPU_34K:
61 /*
62 * Erratum "RPS May Cause Incorrect Instruction Execution"
63 * This code only handles VPE0, any SMP/SMTC/RTOS code
64 * making use of VPE1 will be responsable for that VPE.
65 */
66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
68 break;
69 default:
70 break;
71 }
72 }
73
74 void __init check_bugs32(void)
75 {
76 check_errata();
77 }
78
79 /*
80 * Probe whether cpu has config register by trying to play with
81 * alternate cache bit and see whether it matters.
82 * It's used by cpu_probe to distinguish between R3000A and R3081.
83 */
84 static inline int cpu_has_confreg(void)
85 {
86 #ifdef CONFIG_CPU_R3000
87 extern unsigned long r3k_cache_size(unsigned long);
88 unsigned long size1, size2;
89 unsigned long cfg = read_c0_conf();
90
91 size1 = r3k_cache_size(ST0_ISC);
92 write_c0_conf(cfg ^ R30XX_CONF_AC);
93 size2 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg);
95 return size1 != size2;
96 #else
97 return 0;
98 #endif
99 }
100
101 static inline void set_elf_platform(int cpu, const char *plat)
102 {
103 if (cpu == 0)
104 __elf_platform = plat;
105 }
106
107 /*
108 * Get the FPU Implementation/Revision.
109 */
110 static inline unsigned long cpu_get_fpu_id(void)
111 {
112 unsigned long tmp, fpu_id;
113
114 tmp = read_c0_status();
115 __enable_fpu();
116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp);
118 return fpu_id;
119 }
120
121 /*
122 * Check the CPU has an FPU the official way.
123 */
124 static inline int __cpu_has_fpu(void)
125 {
126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
127 }
128
129 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
130 {
131 #ifdef __NEED_VMBITS_PROBE
132 write_c0_entryhi(0x3fffffffffffe000ULL);
133 back_to_back_c0_hazard();
134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
135 #endif
136 }
137
138 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
139 {
140 switch (isa) {
141 case MIPS_CPU_ISA_M64R2:
142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
143 case MIPS_CPU_ISA_M64R1:
144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
145 case MIPS_CPU_ISA_V:
146 c->isa_level |= MIPS_CPU_ISA_V;
147 case MIPS_CPU_ISA_IV:
148 c->isa_level |= MIPS_CPU_ISA_IV;
149 case MIPS_CPU_ISA_III:
150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
151 break;
152
153 case MIPS_CPU_ISA_M32R2:
154 c->isa_level |= MIPS_CPU_ISA_M32R2;
155 case MIPS_CPU_ISA_M32R1:
156 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II;
159 break;
160 }
161 }
162
163 static char unknown_isa[] = KERN_ERR \
164 "Unsupported ISA type, c0.config0: %d.";
165
166 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
167 {
168 unsigned int config0;
169 int isa;
170
171 config0 = read_c0_config();
172
173 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
174 c->options |= MIPS_CPU_TLB;
175 isa = (config0 & MIPS_CONF_AT) >> 13;
176 switch (isa) {
177 case 0:
178 switch ((config0 & MIPS_CONF_AR) >> 10) {
179 case 0:
180 set_isa(c, MIPS_CPU_ISA_M32R1);
181 break;
182 case 1:
183 set_isa(c, MIPS_CPU_ISA_M32R2);
184 break;
185 default:
186 goto unknown;
187 }
188 break;
189 case 2:
190 switch ((config0 & MIPS_CONF_AR) >> 10) {
191 case 0:
192 set_isa(c, MIPS_CPU_ISA_M64R1);
193 break;
194 case 1:
195 set_isa(c, MIPS_CPU_ISA_M64R2);
196 break;
197 default:
198 goto unknown;
199 }
200 break;
201 default:
202 goto unknown;
203 }
204
205 return config0 & MIPS_CONF_M;
206
207 unknown:
208 panic(unknown_isa, config0);
209 }
210
211 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
212 {
213 unsigned int config1;
214
215 config1 = read_c0_config1();
216
217 if (config1 & MIPS_CONF1_MD)
218 c->ases |= MIPS_ASE_MDMX;
219 if (config1 & MIPS_CONF1_WR)
220 c->options |= MIPS_CPU_WATCH;
221 if (config1 & MIPS_CONF1_CA)
222 c->ases |= MIPS_ASE_MIPS16;
223 if (config1 & MIPS_CONF1_EP)
224 c->options |= MIPS_CPU_EJTAG;
225 if (config1 & MIPS_CONF1_FP) {
226 c->options |= MIPS_CPU_FPU;
227 c->options |= MIPS_CPU_32FPR;
228 }
229 if (cpu_has_tlb)
230 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
231
232 return config1 & MIPS_CONF_M;
233 }
234
235 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
236 {
237 unsigned int config2;
238
239 config2 = read_c0_config2();
240
241 if (config2 & MIPS_CONF2_SL)
242 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
243
244 return config2 & MIPS_CONF_M;
245 }
246
247 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
248 {
249 unsigned int config3;
250
251 config3 = read_c0_config3();
252
253 if (config3 & MIPS_CONF3_SM) {
254 c->ases |= MIPS_ASE_SMARTMIPS;
255 c->options |= MIPS_CPU_RIXI;
256 }
257 if (config3 & MIPS_CONF3_RXI)
258 c->options |= MIPS_CPU_RIXI;
259 if (config3 & MIPS_CONF3_DSP)
260 c->ases |= MIPS_ASE_DSP;
261 if (config3 & MIPS_CONF3_DSP2P)
262 c->ases |= MIPS_ASE_DSP2P;
263 if (config3 & MIPS_CONF3_VINT)
264 c->options |= MIPS_CPU_VINT;
265 if (config3 & MIPS_CONF3_VEIC)
266 c->options |= MIPS_CPU_VEIC;
267 if (config3 & MIPS_CONF3_MT)
268 c->ases |= MIPS_ASE_MIPSMT;
269 if (config3 & MIPS_CONF3_ULRI)
270 c->options |= MIPS_CPU_ULRI;
271 if (config3 & MIPS_CONF3_ISA)
272 c->options |= MIPS_CPU_MICROMIPS;
273 if (config3 & MIPS_CONF3_VZ)
274 c->ases |= MIPS_ASE_VZ;
275
276 return config3 & MIPS_CONF_M;
277 }
278
279 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
280 {
281 unsigned int config4;
282
283 config4 = read_c0_config4();
284
285 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
286 && cpu_has_tlb)
287 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
288
289 c->kscratch_mask = (config4 >> 16) & 0xff;
290
291 return config4 & MIPS_CONF_M;
292 }
293
294 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
295 {
296 unsigned int config5;
297
298 config5 = read_c0_config5();
299 config5 &= ~MIPS_CONF5_UFR;
300 write_c0_config5(config5);
301
302 return config5 & MIPS_CONF_M;
303 }
304
305 static void decode_configs(struct cpuinfo_mips *c)
306 {
307 int ok;
308
309 /* MIPS32 or MIPS64 compliant CPU. */
310 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
311 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
312
313 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
314
315 ok = decode_config0(c); /* Read Config registers. */
316 BUG_ON(!ok); /* Arch spec violation! */
317 if (ok)
318 ok = decode_config1(c);
319 if (ok)
320 ok = decode_config2(c);
321 if (ok)
322 ok = decode_config3(c);
323 if (ok)
324 ok = decode_config4(c);
325 if (ok)
326 ok = decode_config5(c);
327
328 mips_probe_watch_registers(c);
329
330 if (cpu_has_mips_r2)
331 c->core = read_c0_ebase() & 0x3ff;
332 }
333
334 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
335 | MIPS_CPU_COUNTER)
336
337 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
338 {
339 switch (c->processor_id & PRID_IMP_MASK) {
340 case PRID_IMP_R2000:
341 c->cputype = CPU_R2000;
342 __cpu_name[cpu] = "R2000";
343 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
344 MIPS_CPU_NOFPUEX;
345 if (__cpu_has_fpu())
346 c->options |= MIPS_CPU_FPU;
347 c->tlbsize = 64;
348 break;
349 case PRID_IMP_R3000:
350 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
351 if (cpu_has_confreg()) {
352 c->cputype = CPU_R3081E;
353 __cpu_name[cpu] = "R3081";
354 } else {
355 c->cputype = CPU_R3000A;
356 __cpu_name[cpu] = "R3000A";
357 }
358 } else {
359 c->cputype = CPU_R3000;
360 __cpu_name[cpu] = "R3000";
361 }
362 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
363 MIPS_CPU_NOFPUEX;
364 if (__cpu_has_fpu())
365 c->options |= MIPS_CPU_FPU;
366 c->tlbsize = 64;
367 break;
368 case PRID_IMP_R4000:
369 if (read_c0_config() & CONF_SC) {
370 if ((c->processor_id & PRID_REV_MASK) >=
371 PRID_REV_R4400) {
372 c->cputype = CPU_R4400PC;
373 __cpu_name[cpu] = "R4400PC";
374 } else {
375 c->cputype = CPU_R4000PC;
376 __cpu_name[cpu] = "R4000PC";
377 }
378 } else {
379 int cca = read_c0_config() & CONF_CM_CMASK;
380 int mc;
381
382 /*
383 * SC and MC versions can't be reliably told apart,
384 * but only the latter support coherent caching
385 * modes so assume the firmware has set the KSEG0
386 * coherency attribute reasonably (if uncached, we
387 * assume SC).
388 */
389 switch (cca) {
390 case CONF_CM_CACHABLE_CE:
391 case CONF_CM_CACHABLE_COW:
392 case CONF_CM_CACHABLE_CUW:
393 mc = 1;
394 break;
395 default:
396 mc = 0;
397 break;
398 }
399 if ((c->processor_id & PRID_REV_MASK) >=
400 PRID_REV_R4400) {
401 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
402 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
403 } else {
404 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
405 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
406 }
407 }
408
409 set_isa(c, MIPS_CPU_ISA_III);
410 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
411 MIPS_CPU_WATCH | MIPS_CPU_VCE |
412 MIPS_CPU_LLSC;
413 c->tlbsize = 48;
414 break;
415 case PRID_IMP_VR41XX:
416 set_isa(c, MIPS_CPU_ISA_III);
417 c->options = R4K_OPTS;
418 c->tlbsize = 32;
419 switch (c->processor_id & 0xf0) {
420 case PRID_REV_VR4111:
421 c->cputype = CPU_VR4111;
422 __cpu_name[cpu] = "NEC VR4111";
423 break;
424 case PRID_REV_VR4121:
425 c->cputype = CPU_VR4121;
426 __cpu_name[cpu] = "NEC VR4121";
427 break;
428 case PRID_REV_VR4122:
429 if ((c->processor_id & 0xf) < 0x3) {
430 c->cputype = CPU_VR4122;
431 __cpu_name[cpu] = "NEC VR4122";
432 } else {
433 c->cputype = CPU_VR4181A;
434 __cpu_name[cpu] = "NEC VR4181A";
435 }
436 break;
437 case PRID_REV_VR4130:
438 if ((c->processor_id & 0xf) < 0x4) {
439 c->cputype = CPU_VR4131;
440 __cpu_name[cpu] = "NEC VR4131";
441 } else {
442 c->cputype = CPU_VR4133;
443 c->options |= MIPS_CPU_LLSC;
444 __cpu_name[cpu] = "NEC VR4133";
445 }
446 break;
447 default:
448 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
449 c->cputype = CPU_VR41XX;
450 __cpu_name[cpu] = "NEC Vr41xx";
451 break;
452 }
453 break;
454 case PRID_IMP_R4300:
455 c->cputype = CPU_R4300;
456 __cpu_name[cpu] = "R4300";
457 set_isa(c, MIPS_CPU_ISA_III);
458 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
459 MIPS_CPU_LLSC;
460 c->tlbsize = 32;
461 break;
462 case PRID_IMP_R4600:
463 c->cputype = CPU_R4600;
464 __cpu_name[cpu] = "R4600";
465 set_isa(c, MIPS_CPU_ISA_III);
466 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
467 MIPS_CPU_LLSC;
468 c->tlbsize = 48;
469 break;
470 #if 0
471 case PRID_IMP_R4650:
472 /*
473 * This processor doesn't have an MMU, so it's not
474 * "real easy" to run Linux on it. It is left purely
475 * for documentation. Commented out because it shares
476 * it's c0_prid id number with the TX3900.
477 */
478 c->cputype = CPU_R4650;
479 __cpu_name[cpu] = "R4650";
480 set_isa(c, MIPS_CPU_ISA_III);
481 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
482 c->tlbsize = 48;
483 break;
484 #endif
485 case PRID_IMP_TX39:
486 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
487
488 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
489 c->cputype = CPU_TX3927;
490 __cpu_name[cpu] = "TX3927";
491 c->tlbsize = 64;
492 } else {
493 switch (c->processor_id & PRID_REV_MASK) {
494 case PRID_REV_TX3912:
495 c->cputype = CPU_TX3912;
496 __cpu_name[cpu] = "TX3912";
497 c->tlbsize = 32;
498 break;
499 case PRID_REV_TX3922:
500 c->cputype = CPU_TX3922;
501 __cpu_name[cpu] = "TX3922";
502 c->tlbsize = 64;
503 break;
504 }
505 }
506 break;
507 case PRID_IMP_R4700:
508 c->cputype = CPU_R4700;
509 __cpu_name[cpu] = "R4700";
510 set_isa(c, MIPS_CPU_ISA_III);
511 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
512 MIPS_CPU_LLSC;
513 c->tlbsize = 48;
514 break;
515 case PRID_IMP_TX49:
516 c->cputype = CPU_TX49XX;
517 __cpu_name[cpu] = "R49XX";
518 set_isa(c, MIPS_CPU_ISA_III);
519 c->options = R4K_OPTS | MIPS_CPU_LLSC;
520 if (!(c->processor_id & 0x08))
521 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
522 c->tlbsize = 48;
523 break;
524 case PRID_IMP_R5000:
525 c->cputype = CPU_R5000;
526 __cpu_name[cpu] = "R5000";
527 set_isa(c, MIPS_CPU_ISA_IV);
528 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
529 MIPS_CPU_LLSC;
530 c->tlbsize = 48;
531 break;
532 case PRID_IMP_R5432:
533 c->cputype = CPU_R5432;
534 __cpu_name[cpu] = "R5432";
535 set_isa(c, MIPS_CPU_ISA_IV);
536 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
537 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
538 c->tlbsize = 48;
539 break;
540 case PRID_IMP_R5500:
541 c->cputype = CPU_R5500;
542 __cpu_name[cpu] = "R5500";
543 set_isa(c, MIPS_CPU_ISA_IV);
544 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
545 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
546 c->tlbsize = 48;
547 break;
548 case PRID_IMP_NEVADA:
549 c->cputype = CPU_NEVADA;
550 __cpu_name[cpu] = "Nevada";
551 set_isa(c, MIPS_CPU_ISA_IV);
552 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
553 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
554 c->tlbsize = 48;
555 break;
556 case PRID_IMP_R6000:
557 c->cputype = CPU_R6000;
558 __cpu_name[cpu] = "R6000";
559 set_isa(c, MIPS_CPU_ISA_II);
560 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
561 MIPS_CPU_LLSC;
562 c->tlbsize = 32;
563 break;
564 case PRID_IMP_R6000A:
565 c->cputype = CPU_R6000A;
566 __cpu_name[cpu] = "R6000A";
567 set_isa(c, MIPS_CPU_ISA_II);
568 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
569 MIPS_CPU_LLSC;
570 c->tlbsize = 32;
571 break;
572 case PRID_IMP_RM7000:
573 c->cputype = CPU_RM7000;
574 __cpu_name[cpu] = "RM7000";
575 set_isa(c, MIPS_CPU_ISA_IV);
576 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
577 MIPS_CPU_LLSC;
578 /*
579 * Undocumented RM7000: Bit 29 in the info register of
580 * the RM7000 v2.0 indicates if the TLB has 48 or 64
581 * entries.
582 *
583 * 29 1 => 64 entry JTLB
584 * 0 => 48 entry JTLB
585 */
586 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
587 break;
588 case PRID_IMP_RM9000:
589 c->cputype = CPU_RM9000;
590 __cpu_name[cpu] = "RM9000";
591 set_isa(c, MIPS_CPU_ISA_IV);
592 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
593 MIPS_CPU_LLSC;
594 /*
595 * Bit 29 in the info register of the RM9000
596 * indicates if the TLB has 48 or 64 entries.
597 *
598 * 29 1 => 64 entry JTLB
599 * 0 => 48 entry JTLB
600 */
601 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
602 break;
603 case PRID_IMP_R8000:
604 c->cputype = CPU_R8000;
605 __cpu_name[cpu] = "RM8000";
606 set_isa(c, MIPS_CPU_ISA_IV);
607 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
608 MIPS_CPU_FPU | MIPS_CPU_32FPR |
609 MIPS_CPU_LLSC;
610 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
611 break;
612 case PRID_IMP_R10000:
613 c->cputype = CPU_R10000;
614 __cpu_name[cpu] = "R10000";
615 set_isa(c, MIPS_CPU_ISA_IV);
616 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
617 MIPS_CPU_FPU | MIPS_CPU_32FPR |
618 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
619 MIPS_CPU_LLSC;
620 c->tlbsize = 64;
621 break;
622 case PRID_IMP_R12000:
623 c->cputype = CPU_R12000;
624 __cpu_name[cpu] = "R12000";
625 set_isa(c, MIPS_CPU_ISA_IV);
626 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
627 MIPS_CPU_FPU | MIPS_CPU_32FPR |
628 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
629 MIPS_CPU_LLSC;
630 c->tlbsize = 64;
631 break;
632 case PRID_IMP_R14000:
633 c->cputype = CPU_R14000;
634 __cpu_name[cpu] = "R14000";
635 set_isa(c, MIPS_CPU_ISA_IV);
636 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
637 MIPS_CPU_FPU | MIPS_CPU_32FPR |
638 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
639 MIPS_CPU_LLSC;
640 c->tlbsize = 64;
641 break;
642 case PRID_IMP_LOONGSON2:
643 c->cputype = CPU_LOONGSON2;
644 __cpu_name[cpu] = "ICT Loongson-2";
645
646 switch (c->processor_id & PRID_REV_MASK) {
647 case PRID_REV_LOONGSON2E:
648 set_elf_platform(cpu, "loongson2e");
649 break;
650 case PRID_REV_LOONGSON2F:
651 set_elf_platform(cpu, "loongson2f");
652 break;
653 }
654
655 set_isa(c, MIPS_CPU_ISA_III);
656 c->options = R4K_OPTS |
657 MIPS_CPU_FPU | MIPS_CPU_LLSC |
658 MIPS_CPU_32FPR;
659 c->tlbsize = 64;
660 break;
661 case PRID_IMP_LOONGSON1:
662 decode_configs(c);
663
664 c->cputype = CPU_LOONGSON1;
665
666 switch (c->processor_id & PRID_REV_MASK) {
667 case PRID_REV_LOONGSON1B:
668 __cpu_name[cpu] = "Loongson 1B";
669 break;
670 }
671
672 break;
673 }
674 }
675
676 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
677 {
678 decode_configs(c);
679 switch (c->processor_id & PRID_IMP_MASK) {
680 case PRID_IMP_4KC:
681 c->cputype = CPU_4KC;
682 __cpu_name[cpu] = "MIPS 4Kc";
683 break;
684 case PRID_IMP_4KEC:
685 case PRID_IMP_4KECR2:
686 c->cputype = CPU_4KEC;
687 __cpu_name[cpu] = "MIPS 4KEc";
688 break;
689 case PRID_IMP_4KSC:
690 case PRID_IMP_4KSD:
691 c->cputype = CPU_4KSC;
692 __cpu_name[cpu] = "MIPS 4KSc";
693 break;
694 case PRID_IMP_5KC:
695 c->cputype = CPU_5KC;
696 __cpu_name[cpu] = "MIPS 5Kc";
697 break;
698 case PRID_IMP_5KE:
699 c->cputype = CPU_5KE;
700 __cpu_name[cpu] = "MIPS 5KE";
701 break;
702 case PRID_IMP_20KC:
703 c->cputype = CPU_20KC;
704 __cpu_name[cpu] = "MIPS 20Kc";
705 break;
706 case PRID_IMP_24K:
707 c->cputype = CPU_24K;
708 __cpu_name[cpu] = "MIPS 24Kc";
709 break;
710 case PRID_IMP_24KE:
711 c->cputype = CPU_24K;
712 __cpu_name[cpu] = "MIPS 24KEc";
713 break;
714 case PRID_IMP_25KF:
715 c->cputype = CPU_25KF;
716 __cpu_name[cpu] = "MIPS 25Kc";
717 break;
718 case PRID_IMP_34K:
719 c->cputype = CPU_34K;
720 __cpu_name[cpu] = "MIPS 34Kc";
721 break;
722 case PRID_IMP_74K:
723 c->cputype = CPU_74K;
724 __cpu_name[cpu] = "MIPS 74Kc";
725 break;
726 case PRID_IMP_M14KC:
727 c->cputype = CPU_M14KC;
728 __cpu_name[cpu] = "MIPS M14Kc";
729 break;
730 case PRID_IMP_M14KEC:
731 c->cputype = CPU_M14KEC;
732 __cpu_name[cpu] = "MIPS M14KEc";
733 break;
734 case PRID_IMP_1004K:
735 c->cputype = CPU_1004K;
736 __cpu_name[cpu] = "MIPS 1004Kc";
737 break;
738 case PRID_IMP_1074K:
739 c->cputype = CPU_74K;
740 __cpu_name[cpu] = "MIPS 1074Kc";
741 break;
742 }
743
744 spram_config();
745 }
746
747 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
748 {
749 decode_configs(c);
750 switch (c->processor_id & PRID_IMP_MASK) {
751 case PRID_IMP_AU1_REV1:
752 case PRID_IMP_AU1_REV2:
753 c->cputype = CPU_ALCHEMY;
754 switch ((c->processor_id >> 24) & 0xff) {
755 case 0:
756 __cpu_name[cpu] = "Au1000";
757 break;
758 case 1:
759 __cpu_name[cpu] = "Au1500";
760 break;
761 case 2:
762 __cpu_name[cpu] = "Au1100";
763 break;
764 case 3:
765 __cpu_name[cpu] = "Au1550";
766 break;
767 case 4:
768 __cpu_name[cpu] = "Au1200";
769 if ((c->processor_id & PRID_REV_MASK) == 2)
770 __cpu_name[cpu] = "Au1250";
771 break;
772 case 5:
773 __cpu_name[cpu] = "Au1210";
774 break;
775 default:
776 __cpu_name[cpu] = "Au1xxx";
777 break;
778 }
779 break;
780 }
781 }
782
783 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
784 {
785 decode_configs(c);
786
787 switch (c->processor_id & PRID_IMP_MASK) {
788 case PRID_IMP_SB1:
789 c->cputype = CPU_SB1;
790 __cpu_name[cpu] = "SiByte SB1";
791 /* FPU in pass1 is known to have issues. */
792 if ((c->processor_id & PRID_REV_MASK) < 0x02)
793 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
794 break;
795 case PRID_IMP_SB1A:
796 c->cputype = CPU_SB1A;
797 __cpu_name[cpu] = "SiByte SB1A";
798 break;
799 }
800 }
801
802 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
803 {
804 decode_configs(c);
805 switch (c->processor_id & PRID_IMP_MASK) {
806 case PRID_IMP_SR71000:
807 c->cputype = CPU_SR71000;
808 __cpu_name[cpu] = "Sandcraft SR71000";
809 c->scache.ways = 8;
810 c->tlbsize = 64;
811 break;
812 }
813 }
814
815 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
816 {
817 decode_configs(c);
818 switch (c->processor_id & PRID_IMP_MASK) {
819 case PRID_IMP_PR4450:
820 c->cputype = CPU_PR4450;
821 __cpu_name[cpu] = "Philips PR4450";
822 set_isa(c, MIPS_CPU_ISA_M32R1);
823 break;
824 }
825 }
826
827 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
828 {
829 decode_configs(c);
830 switch (c->processor_id & PRID_IMP_MASK) {
831 case PRID_IMP_BMIPS32_REV4:
832 case PRID_IMP_BMIPS32_REV8:
833 c->cputype = CPU_BMIPS32;
834 __cpu_name[cpu] = "Broadcom BMIPS32";
835 set_elf_platform(cpu, "bmips32");
836 break;
837 case PRID_IMP_BMIPS3300:
838 case PRID_IMP_BMIPS3300_ALT:
839 case PRID_IMP_BMIPS3300_BUG:
840 c->cputype = CPU_BMIPS3300;
841 __cpu_name[cpu] = "Broadcom BMIPS3300";
842 set_elf_platform(cpu, "bmips3300");
843 break;
844 case PRID_IMP_BMIPS43XX: {
845 int rev = c->processor_id & PRID_REV_MASK;
846
847 if (rev >= PRID_REV_BMIPS4380_LO &&
848 rev <= PRID_REV_BMIPS4380_HI) {
849 c->cputype = CPU_BMIPS4380;
850 __cpu_name[cpu] = "Broadcom BMIPS4380";
851 set_elf_platform(cpu, "bmips4380");
852 } else {
853 c->cputype = CPU_BMIPS4350;
854 __cpu_name[cpu] = "Broadcom BMIPS4350";
855 set_elf_platform(cpu, "bmips4350");
856 }
857 break;
858 }
859 case PRID_IMP_BMIPS5000:
860 c->cputype = CPU_BMIPS5000;
861 __cpu_name[cpu] = "Broadcom BMIPS5000";
862 set_elf_platform(cpu, "bmips5000");
863 c->options |= MIPS_CPU_ULRI;
864 break;
865 }
866 }
867
868 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
869 {
870 decode_configs(c);
871 switch (c->processor_id & PRID_IMP_MASK) {
872 case PRID_IMP_CAVIUM_CN38XX:
873 case PRID_IMP_CAVIUM_CN31XX:
874 case PRID_IMP_CAVIUM_CN30XX:
875 c->cputype = CPU_CAVIUM_OCTEON;
876 __cpu_name[cpu] = "Cavium Octeon";
877 goto platform;
878 case PRID_IMP_CAVIUM_CN58XX:
879 case PRID_IMP_CAVIUM_CN56XX:
880 case PRID_IMP_CAVIUM_CN50XX:
881 case PRID_IMP_CAVIUM_CN52XX:
882 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
883 __cpu_name[cpu] = "Cavium Octeon+";
884 platform:
885 set_elf_platform(cpu, "octeon");
886 break;
887 case PRID_IMP_CAVIUM_CN61XX:
888 case PRID_IMP_CAVIUM_CN63XX:
889 case PRID_IMP_CAVIUM_CN66XX:
890 case PRID_IMP_CAVIUM_CN68XX:
891 case PRID_IMP_CAVIUM_CNF71XX:
892 c->cputype = CPU_CAVIUM_OCTEON2;
893 __cpu_name[cpu] = "Cavium Octeon II";
894 set_elf_platform(cpu, "octeon2");
895 break;
896 case PRID_IMP_CAVIUM_CN70XX:
897 case PRID_IMP_CAVIUM_CN78XX:
898 c->cputype = CPU_CAVIUM_OCTEON3;
899 __cpu_name[cpu] = "Cavium Octeon III";
900 set_elf_platform(cpu, "octeon3");
901 break;
902 default:
903 printk(KERN_INFO "Unknown Octeon chip!\n");
904 c->cputype = CPU_UNKNOWN;
905 break;
906 }
907 }
908
909 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
910 {
911 decode_configs(c);
912 /* JZRISC does not implement the CP0 counter. */
913 c->options &= ~MIPS_CPU_COUNTER;
914 switch (c->processor_id & PRID_IMP_MASK) {
915 case PRID_IMP_JZRISC:
916 c->cputype = CPU_JZRISC;
917 __cpu_name[cpu] = "Ingenic JZRISC";
918 break;
919 default:
920 panic("Unknown Ingenic Processor ID!");
921 break;
922 }
923 }
924
925 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
926 {
927 decode_configs(c);
928
929 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
930 c->cputype = CPU_ALCHEMY;
931 __cpu_name[cpu] = "Au1300";
932 /* following stuff is not for Alchemy */
933 return;
934 }
935
936 c->options = (MIPS_CPU_TLB |
937 MIPS_CPU_4KEX |
938 MIPS_CPU_COUNTER |
939 MIPS_CPU_DIVEC |
940 MIPS_CPU_WATCH |
941 MIPS_CPU_EJTAG |
942 MIPS_CPU_LLSC);
943
944 switch (c->processor_id & PRID_IMP_MASK) {
945 case PRID_IMP_NETLOGIC_XLP2XX:
946 c->cputype = CPU_XLP;
947 __cpu_name[cpu] = "Broadcom XLPII";
948 break;
949
950 case PRID_IMP_NETLOGIC_XLP8XX:
951 case PRID_IMP_NETLOGIC_XLP3XX:
952 c->cputype = CPU_XLP;
953 __cpu_name[cpu] = "Netlogic XLP";
954 break;
955
956 case PRID_IMP_NETLOGIC_XLR732:
957 case PRID_IMP_NETLOGIC_XLR716:
958 case PRID_IMP_NETLOGIC_XLR532:
959 case PRID_IMP_NETLOGIC_XLR308:
960 case PRID_IMP_NETLOGIC_XLR532C:
961 case PRID_IMP_NETLOGIC_XLR516C:
962 case PRID_IMP_NETLOGIC_XLR508C:
963 case PRID_IMP_NETLOGIC_XLR308C:
964 c->cputype = CPU_XLR;
965 __cpu_name[cpu] = "Netlogic XLR";
966 break;
967
968 case PRID_IMP_NETLOGIC_XLS608:
969 case PRID_IMP_NETLOGIC_XLS408:
970 case PRID_IMP_NETLOGIC_XLS404:
971 case PRID_IMP_NETLOGIC_XLS208:
972 case PRID_IMP_NETLOGIC_XLS204:
973 case PRID_IMP_NETLOGIC_XLS108:
974 case PRID_IMP_NETLOGIC_XLS104:
975 case PRID_IMP_NETLOGIC_XLS616B:
976 case PRID_IMP_NETLOGIC_XLS608B:
977 case PRID_IMP_NETLOGIC_XLS416B:
978 case PRID_IMP_NETLOGIC_XLS412B:
979 case PRID_IMP_NETLOGIC_XLS408B:
980 case PRID_IMP_NETLOGIC_XLS404B:
981 c->cputype = CPU_XLR;
982 __cpu_name[cpu] = "Netlogic XLS";
983 break;
984
985 default:
986 pr_info("Unknown Netlogic chip id [%02x]!\n",
987 c->processor_id);
988 c->cputype = CPU_XLR;
989 break;
990 }
991
992 if (c->cputype == CPU_XLP) {
993 set_isa(c, MIPS_CPU_ISA_M64R2);
994 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
995 /* This will be updated again after all threads are woken up */
996 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
997 } else {
998 set_isa(c, MIPS_CPU_ISA_M64R1);
999 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1000 }
1001 c->kscratch_mask = 0xf;
1002 }
1003
1004 #ifdef CONFIG_64BIT
1005 /* For use by uaccess.h */
1006 u64 __ua_limit;
1007 EXPORT_SYMBOL(__ua_limit);
1008 #endif
1009
1010 const char *__cpu_name[NR_CPUS];
1011 const char *__elf_platform;
1012
1013 void cpu_probe(void)
1014 {
1015 struct cpuinfo_mips *c = &current_cpu_data;
1016 unsigned int cpu = smp_processor_id();
1017
1018 c->processor_id = PRID_IMP_UNKNOWN;
1019 c->fpu_id = FPIR_IMP_NONE;
1020 c->cputype = CPU_UNKNOWN;
1021
1022 c->processor_id = read_c0_prid();
1023 switch (c->processor_id & PRID_COMP_MASK) {
1024 case PRID_COMP_LEGACY:
1025 cpu_probe_legacy(c, cpu);
1026 break;
1027 case PRID_COMP_MIPS:
1028 cpu_probe_mips(c, cpu);
1029 break;
1030 case PRID_COMP_ALCHEMY:
1031 cpu_probe_alchemy(c, cpu);
1032 break;
1033 case PRID_COMP_SIBYTE:
1034 cpu_probe_sibyte(c, cpu);
1035 break;
1036 case PRID_COMP_BROADCOM:
1037 cpu_probe_broadcom(c, cpu);
1038 break;
1039 case PRID_COMP_SANDCRAFT:
1040 cpu_probe_sandcraft(c, cpu);
1041 break;
1042 case PRID_COMP_NXP:
1043 cpu_probe_nxp(c, cpu);
1044 break;
1045 case PRID_COMP_CAVIUM:
1046 cpu_probe_cavium(c, cpu);
1047 break;
1048 case PRID_COMP_INGENIC:
1049 cpu_probe_ingenic(c, cpu);
1050 break;
1051 case PRID_COMP_NETLOGIC:
1052 cpu_probe_netlogic(c, cpu);
1053 break;
1054 }
1055
1056 BUG_ON(!__cpu_name[cpu]);
1057 BUG_ON(c->cputype == CPU_UNKNOWN);
1058
1059 /*
1060 * Platform code can force the cpu type to optimize code
1061 * generation. In that case be sure the cpu type is correctly
1062 * manually setup otherwise it could trigger some nasty bugs.
1063 */
1064 BUG_ON(current_cpu_type() != c->cputype);
1065
1066 if (mips_fpu_disabled)
1067 c->options &= ~MIPS_CPU_FPU;
1068
1069 if (mips_dsp_disabled)
1070 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1071
1072 if (c->options & MIPS_CPU_FPU) {
1073 c->fpu_id = cpu_get_fpu_id();
1074
1075 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1076 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1077 if (c->fpu_id & MIPS_FPIR_3D)
1078 c->ases |= MIPS_ASE_MIPS3D;
1079 }
1080 }
1081
1082 if (cpu_has_mips_r2) {
1083 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1084 /* R2 has Performance Counter Interrupt indicator */
1085 c->options |= MIPS_CPU_PCI;
1086 }
1087 else
1088 c->srsets = 1;
1089
1090 cpu_probe_vmbits(c);
1091
1092 #ifdef CONFIG_64BIT
1093 if (cpu == 0)
1094 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1095 #endif
1096 }
1097
1098 void cpu_report(void)
1099 {
1100 struct cpuinfo_mips *c = &current_cpu_data;
1101
1102 pr_info("CPU%d revision is: %08x (%s)\n",
1103 smp_processor_id(), c->processor_id, cpu_name_string());
1104 if (c->options & MIPS_CPU_FPU)
1105 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1106 }
Linux kernel - Deliverables
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