2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2014 Imagination Technologies Ltd.
7 * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
8 * Author: Markos Chandras <markos.chandras@imgtec.com>
10 * MIPS R2 user space instruction emulator for MIPS R6
13 #include <linux/bug.h>
14 #include <linux/compiler.h>
15 #include <linux/debugfs.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/ptrace.h>
20 #include <linux/seq_file.h>
23 #include <asm/branch.h>
24 #include <asm/break.h>
25 #include <asm/debug.h>
27 #include <asm/fpu_emulator.h>
29 #include <asm/mips-r2-to-r6-emul.h>
30 #include <asm/local.h>
31 #include <asm/mipsregs.h>
32 #include <asm/ptrace.h>
33 #include <asm/uaccess.h>
36 #define ADDIU "daddiu "
40 #define ADDIU "addiu "
43 #endif /* CONFIG_64BIT */
50 DEFINE_PER_CPU(struct mips_r2_emulator_stats
, mipsr2emustats
);
51 DEFINE_PER_CPU(struct mips_r2_emulator_stats
, mipsr2bdemustats
);
52 DEFINE_PER_CPU(struct mips_r2br_emulator_stats
, mipsr2bremustats
);
54 extern const unsigned int fpucondbit
[8];
56 #define MIPS_R2_EMUL_TOTAL_PASS 10
58 int mipsr2_emulation
= 0;
60 static int __init
mipsr2emu_enable(char *s
)
64 pr_info("MIPS R2-to-R6 Emulator Enabled!");
68 __setup("mipsr2emu", mipsr2emu_enable
);
71 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
72 * for performance instead of the traditional way of using a stack trampoline
73 * which is rather slow.
74 * @regs: Process register set
77 static inline int mipsr6_emul(struct pt_regs
*regs
, u32 ir
)
79 switch (MIPSInst_OPCODE(ir
)) {
82 regs
->regs
[MIPSInst_RT(ir
)] =
83 (s32
)regs
->regs
[MIPSInst_RS(ir
)] +
84 (s32
)MIPSInst_SIMM(ir
);
87 if (IS_ENABLED(CONFIG_32BIT
))
91 regs
->regs
[MIPSInst_RT(ir
)] =
92 (s64
)regs
->regs
[MIPSInst_RS(ir
)] +
93 (s64
)MIPSInst_SIMM(ir
);
99 /* FPU instructions in delay slot */
102 switch (MIPSInst_FUNC(ir
)) {
105 regs
->regs
[MIPSInst_RD(ir
)] =
106 regs
->regs
[MIPSInst_RS(ir
)] |
107 regs
->regs
[MIPSInst_RT(ir
)];
114 regs
->regs
[MIPSInst_RD(ir
)] =
115 (s32
)(((u32
)regs
->regs
[MIPSInst_RT(ir
)]) <<
123 regs
->regs
[MIPSInst_RD(ir
)] =
124 (s32
)(((u32
)regs
->regs
[MIPSInst_RT(ir
)]) >>
132 regs
->regs
[MIPSInst_RD(ir
)] =
133 (s32
)((u32
)regs
->regs
[MIPSInst_RS(ir
)] +
134 (u32
)regs
->regs
[MIPSInst_RT(ir
)]);
141 regs
->regs
[MIPSInst_RD(ir
)] =
142 (s32
)((u32
)regs
->regs
[MIPSInst_RS(ir
)] -
143 (u32
)regs
->regs
[MIPSInst_RT(ir
)]);
146 if (IS_ENABLED(CONFIG_32BIT
) || MIPSInst_RS(ir
))
150 regs
->regs
[MIPSInst_RD(ir
)] =
151 (s64
)(((u64
)regs
->regs
[MIPSInst_RT(ir
)]) <<
155 if (IS_ENABLED(CONFIG_32BIT
) || MIPSInst_RS(ir
))
159 regs
->regs
[MIPSInst_RD(ir
)] =
160 (s64
)(((u64
)regs
->regs
[MIPSInst_RT(ir
)]) >>
164 if (IS_ENABLED(CONFIG_32BIT
) || MIPSInst_FD(ir
))
168 regs
->regs
[MIPSInst_RD(ir
)] =
169 (u64
)regs
->regs
[MIPSInst_RS(ir
)] +
170 (u64
)regs
->regs
[MIPSInst_RT(ir
)];
173 if (IS_ENABLED(CONFIG_32BIT
) || MIPSInst_FD(ir
))
177 regs
->regs
[MIPSInst_RD(ir
)] =
178 (s64
)((u64
)regs
->regs
[MIPSInst_RS(ir
)] -
179 (u64
)regs
->regs
[MIPSInst_RT(ir
)]);
184 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n",
185 ir
, MIPSInst_OPCODE(ir
));
192 * movf_func - Emulate a MOVF instruction
193 * @regs: Process register set
196 * Returns 0 since it always succeeds.
198 static int movf_func(struct pt_regs
*regs
, u32 ir
)
203 csr
= current
->thread
.fpu
.fcr31
;
204 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
206 if (((csr
& cond
) == 0) && MIPSInst_RD(ir
))
207 regs
->regs
[MIPSInst_RD(ir
)] = regs
->regs
[MIPSInst_RS(ir
)];
215 * movt_func - Emulate a MOVT instruction
216 * @regs: Process register set
219 * Returns 0 since it always succeeds.
221 static int movt_func(struct pt_regs
*regs
, u32 ir
)
226 csr
= current
->thread
.fpu
.fcr31
;
227 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
229 if (((csr
& cond
) != 0) && MIPSInst_RD(ir
))
230 regs
->regs
[MIPSInst_RD(ir
)] = regs
->regs
[MIPSInst_RS(ir
)];
238 * jr_func - Emulate a JR instruction.
239 * @pt_regs: Process register set
242 * Returns SIGILL if JR was in delay slot, SIGEMT if we
243 * can't compute the EPC, SIGSEGV if we can't access the
244 * userland instruction or 0 on success.
246 static int jr_func(struct pt_regs
*regs
, u32 ir
)
249 unsigned long cepc
, epc
, nepc
;
252 if (delay_slot(regs
))
255 /* EPC after the RI/JR instruction */
256 nepc
= regs
->cp0_epc
;
257 /* Roll back to the reserved R2 JR instruction */
260 err
= __compute_return_epc(regs
);
267 cepc
= regs
->cp0_epc
;
269 /* Get DS instruction */
270 err
= __get_user(nir
, (u32 __user
*)nepc
);
274 MIPS_R2BR_STATS(jrs
);
276 /* If nir == 0(NOP), then nothing else to do */
279 * Negative err means FPU instruction in BD-slot,
280 * Zero err means 'BD-slot emulation done'
281 * For anything else we go back to trampoline emulation.
283 err
= mipsr6_emul(regs
, nir
);
285 regs
->cp0_epc
= nepc
;
286 err
= mips_dsemul(regs
, nir
, epc
, cepc
);
289 MIPS_R2_STATS(dsemul
);
297 * movz_func - Emulate a MOVZ instruction
298 * @regs: Process register set
301 * Returns 0 since it always succeeds.
303 static int movz_func(struct pt_regs
*regs
, u32 ir
)
305 if (((regs
->regs
[MIPSInst_RT(ir
)]) == 0) && MIPSInst_RD(ir
))
306 regs
->regs
[MIPSInst_RD(ir
)] = regs
->regs
[MIPSInst_RS(ir
)];
313 * movn_func - Emulate a MOVZ instruction
314 * @regs: Process register set
317 * Returns 0 since it always succeeds.
319 static int movn_func(struct pt_regs
*regs
, u32 ir
)
321 if (((regs
->regs
[MIPSInst_RT(ir
)]) != 0) && MIPSInst_RD(ir
))
322 regs
->regs
[MIPSInst_RD(ir
)] = regs
->regs
[MIPSInst_RS(ir
)];
329 * mfhi_func - Emulate a MFHI instruction
330 * @regs: Process register set
333 * Returns 0 since it always succeeds.
335 static int mfhi_func(struct pt_regs
*regs
, u32 ir
)
338 regs
->regs
[MIPSInst_RD(ir
)] = regs
->hi
;
346 * mthi_func - Emulate a MTHI instruction
347 * @regs: Process register set
350 * Returns 0 since it always succeeds.
352 static int mthi_func(struct pt_regs
*regs
, u32 ir
)
354 regs
->hi
= regs
->regs
[MIPSInst_RS(ir
)];
362 * mflo_func - Emulate a MFLO instruction
363 * @regs: Process register set
366 * Returns 0 since it always succeeds.
368 static int mflo_func(struct pt_regs
*regs
, u32 ir
)
371 regs
->regs
[MIPSInst_RD(ir
)] = regs
->lo
;
379 * mtlo_func - Emulate a MTLO instruction
380 * @regs: Process register set
383 * Returns 0 since it always succeeds.
385 static int mtlo_func(struct pt_regs
*regs
, u32 ir
)
387 regs
->lo
= regs
->regs
[MIPSInst_RS(ir
)];
395 * mult_func - Emulate a MULT instruction
396 * @regs: Process register set
399 * Returns 0 since it always succeeds.
401 static int mult_func(struct pt_regs
*regs
, u32 ir
)
406 rt
= regs
->regs
[MIPSInst_RT(ir
)];
407 rs
= regs
->regs
[MIPSInst_RS(ir
)];
408 res
= (s64
)rt
* (s64
)rs
;
422 * multu_func - Emulate a MULTU instruction
423 * @regs: Process register set
426 * Returns 0 since it always succeeds.
428 static int multu_func(struct pt_regs
*regs
, u32 ir
)
433 rt
= regs
->regs
[MIPSInst_RT(ir
)];
434 rs
= regs
->regs
[MIPSInst_RS(ir
)];
435 res
= (u64
)rt
* (u64
)rs
;
438 regs
->hi
= (s64
)(res
>> 32);
446 * div_func - Emulate a DIV instruction
447 * @regs: Process register set
450 * Returns 0 since it always succeeds.
452 static int div_func(struct pt_regs
*regs
, u32 ir
)
456 rt
= regs
->regs
[MIPSInst_RT(ir
)];
457 rs
= regs
->regs
[MIPSInst_RS(ir
)];
459 regs
->lo
= (s64
)(rs
/ rt
);
460 regs
->hi
= (s64
)(rs
% rt
);
468 * divu_func - Emulate a DIVU instruction
469 * @regs: Process register set
472 * Returns 0 since it always succeeds.
474 static int divu_func(struct pt_regs
*regs
, u32 ir
)
478 rt
= regs
->regs
[MIPSInst_RT(ir
)];
479 rs
= regs
->regs
[MIPSInst_RS(ir
)];
481 regs
->lo
= (s64
)(rs
/ rt
);
482 regs
->hi
= (s64
)(rs
% rt
);
490 * dmult_func - Emulate a DMULT instruction
491 * @regs: Process register set
494 * Returns 0 on success or SIGILL for 32-bit kernels.
496 static int dmult_func(struct pt_regs
*regs
, u32 ir
)
501 if (IS_ENABLED(CONFIG_32BIT
))
504 rt
= regs
->regs
[MIPSInst_RT(ir
)];
505 rs
= regs
->regs
[MIPSInst_RS(ir
)];
509 __asm__
__volatile__(
510 "dmuh %0, %1, %2\t\n"
522 * dmultu_func - Emulate a DMULTU instruction
523 * @regs: Process register set
526 * Returns 0 on success or SIGILL for 32-bit kernels.
528 static int dmultu_func(struct pt_regs
*regs
, u32 ir
)
533 if (IS_ENABLED(CONFIG_32BIT
))
536 rt
= regs
->regs
[MIPSInst_RT(ir
)];
537 rs
= regs
->regs
[MIPSInst_RS(ir
)];
541 __asm__
__volatile__(
542 "dmuhu %0, %1, %2\t\n"
554 * ddiv_func - Emulate a DDIV instruction
555 * @regs: Process register set
558 * Returns 0 on success or SIGILL for 32-bit kernels.
560 static int ddiv_func(struct pt_regs
*regs
, u32 ir
)
564 if (IS_ENABLED(CONFIG_32BIT
))
567 rt
= regs
->regs
[MIPSInst_RT(ir
)];
568 rs
= regs
->regs
[MIPSInst_RS(ir
)];
579 * ddivu_func - Emulate a DDIVU instruction
580 * @regs: Process register set
583 * Returns 0 on success or SIGILL for 32-bit kernels.
585 static int ddivu_func(struct pt_regs
*regs
, u32 ir
)
589 if (IS_ENABLED(CONFIG_32BIT
))
592 rt
= regs
->regs
[MIPSInst_RT(ir
)];
593 rs
= regs
->regs
[MIPSInst_RS(ir
)];
603 /* R6 removed instructions for the SPECIAL opcode */
604 static struct r2_decoder_table spec_op_table
[] = {
605 { 0xfc1ff83f, 0x00000008, jr_func
},
606 { 0xfc00ffff, 0x00000018, mult_func
},
607 { 0xfc00ffff, 0x00000019, multu_func
},
608 { 0xfc00ffff, 0x0000001c, dmult_func
},
609 { 0xfc00ffff, 0x0000001d, dmultu_func
},
610 { 0xffff07ff, 0x00000010, mfhi_func
},
611 { 0xfc1fffff, 0x00000011, mthi_func
},
612 { 0xffff07ff, 0x00000012, mflo_func
},
613 { 0xfc1fffff, 0x00000013, mtlo_func
},
614 { 0xfc0307ff, 0x00000001, movf_func
},
615 { 0xfc0307ff, 0x00010001, movt_func
},
616 { 0xfc0007ff, 0x0000000a, movz_func
},
617 { 0xfc0007ff, 0x0000000b, movn_func
},
618 { 0xfc00ffff, 0x0000001a, div_func
},
619 { 0xfc00ffff, 0x0000001b, divu_func
},
620 { 0xfc00ffff, 0x0000001e, ddiv_func
},
621 { 0xfc00ffff, 0x0000001f, ddivu_func
},
626 * madd_func - Emulate a MADD instruction
627 * @regs: Process register set
630 * Returns 0 since it always succeeds.
632 static int madd_func(struct pt_regs
*regs
, u32 ir
)
637 rt
= regs
->regs
[MIPSInst_RT(ir
)];
638 rs
= regs
->regs
[MIPSInst_RS(ir
)];
639 res
= (s64
)rt
* (s64
)rs
;
642 res
+= ((((s64
)rt
) << 32) | (u32
)rs
);
655 * maddu_func - Emulate a MADDU instruction
656 * @regs: Process register set
659 * Returns 0 since it always succeeds.
661 static int maddu_func(struct pt_regs
*regs
, u32 ir
)
666 rt
= regs
->regs
[MIPSInst_RT(ir
)];
667 rs
= regs
->regs
[MIPSInst_RS(ir
)];
668 res
= (u64
)rt
* (u64
)rs
;
671 res
+= ((((s64
)rt
) << 32) | (u32
)rs
);
684 * msub_func - Emulate a MSUB instruction
685 * @regs: Process register set
688 * Returns 0 since it always succeeds.
690 static int msub_func(struct pt_regs
*regs
, u32 ir
)
695 rt
= regs
->regs
[MIPSInst_RT(ir
)];
696 rs
= regs
->regs
[MIPSInst_RS(ir
)];
697 res
= (s64
)rt
* (s64
)rs
;
700 res
= ((((s64
)rt
) << 32) | (u32
)rs
) - res
;
713 * msubu_func - Emulate a MSUBU instruction
714 * @regs: Process register set
717 * Returns 0 since it always succeeds.
719 static int msubu_func(struct pt_regs
*regs
, u32 ir
)
724 rt
= regs
->regs
[MIPSInst_RT(ir
)];
725 rs
= regs
->regs
[MIPSInst_RS(ir
)];
726 res
= (u64
)rt
* (u64
)rs
;
729 res
= ((((s64
)rt
) << 32) | (u32
)rs
) - res
;
742 * mul_func - Emulate a MUL instruction
743 * @regs: Process register set
746 * Returns 0 since it always succeeds.
748 static int mul_func(struct pt_regs
*regs
, u32 ir
)
753 if (!MIPSInst_RD(ir
))
755 rt
= regs
->regs
[MIPSInst_RT(ir
)];
756 rs
= regs
->regs
[MIPSInst_RS(ir
)];
757 res
= (s64
)rt
* (s64
)rs
;
760 regs
->regs
[MIPSInst_RD(ir
)] = (s64
)rs
;
768 * clz_func - Emulate a CLZ instruction
769 * @regs: Process register set
772 * Returns 0 since it always succeeds.
774 static int clz_func(struct pt_regs
*regs
, u32 ir
)
779 if (!MIPSInst_RD(ir
))
782 rs
= regs
->regs
[MIPSInst_RS(ir
)];
783 __asm__
__volatile__("clz %0, %1" : "=r"(res
) : "r"(rs
));
784 regs
->regs
[MIPSInst_RD(ir
)] = res
;
792 * clo_func - Emulate a CLO instruction
793 * @regs: Process register set
796 * Returns 0 since it always succeeds.
799 static int clo_func(struct pt_regs
*regs
, u32 ir
)
804 if (!MIPSInst_RD(ir
))
807 rs
= regs
->regs
[MIPSInst_RS(ir
)];
808 __asm__
__volatile__("clo %0, %1" : "=r"(res
) : "r"(rs
));
809 regs
->regs
[MIPSInst_RD(ir
)] = res
;
817 * dclz_func - Emulate a DCLZ instruction
818 * @regs: Process register set
821 * Returns 0 since it always succeeds.
823 static int dclz_func(struct pt_regs
*regs
, u32 ir
)
828 if (IS_ENABLED(CONFIG_32BIT
))
831 if (!MIPSInst_RD(ir
))
834 rs
= regs
->regs
[MIPSInst_RS(ir
)];
835 __asm__
__volatile__("dclz %0, %1" : "=r"(res
) : "r"(rs
));
836 regs
->regs
[MIPSInst_RD(ir
)] = res
;
844 * dclo_func - Emulate a DCLO instruction
845 * @regs: Process register set
848 * Returns 0 since it always succeeds.
850 static int dclo_func(struct pt_regs
*regs
, u32 ir
)
855 if (IS_ENABLED(CONFIG_32BIT
))
858 if (!MIPSInst_RD(ir
))
861 rs
= regs
->regs
[MIPSInst_RS(ir
)];
862 __asm__
__volatile__("dclo %0, %1" : "=r"(res
) : "r"(rs
));
863 regs
->regs
[MIPSInst_RD(ir
)] = res
;
870 /* R6 removed instructions for the SPECIAL2 opcode */
871 static struct r2_decoder_table spec2_op_table
[] = {
872 { 0xfc00ffff, 0x70000000, madd_func
},
873 { 0xfc00ffff, 0x70000001, maddu_func
},
874 { 0xfc0007ff, 0x70000002, mul_func
},
875 { 0xfc00ffff, 0x70000004, msub_func
},
876 { 0xfc00ffff, 0x70000005, msubu_func
},
877 { 0xfc0007ff, 0x70000020, clz_func
},
878 { 0xfc0007ff, 0x70000021, clo_func
},
879 { 0xfc0007ff, 0x70000024, dclz_func
},
880 { 0xfc0007ff, 0x70000025, dclo_func
},
884 static inline int mipsr2_find_op_func(struct pt_regs
*regs
, u32 inst
,
885 struct r2_decoder_table
*table
)
887 struct r2_decoder_table
*p
;
890 for (p
= table
; p
->func
; p
++) {
891 if ((inst
& p
->mask
) == p
->code
) {
892 err
= (p
->func
)(regs
, inst
);
900 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
901 * @regs: Process register set
902 * @inst: Instruction to decode and emulate
903 * @fcr31: Floating Point Control and Status Register returned
905 int mipsr2_decoder(struct pt_regs
*regs
, u32 inst
, unsigned long *fcr31
)
910 unsigned long cpc
, epc
, nepc
, r31
, res
, rs
, rt
;
912 void __user
*fault_addr
= NULL
;
916 r31
= regs
->regs
[31];
918 err
= compute_return_epc(regs
);
923 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n",
926 switch (MIPSInst_OPCODE(inst
)) {
928 err
= mipsr2_find_op_func(regs
, inst
, spec_op_table
);
930 /* FPU instruction under JR */
931 regs
->cp0_cause
|= CAUSEF_BD
;
936 err
= mipsr2_find_op_func(regs
, inst
, spec2_op_table
);
939 rt
= MIPSInst_RT(inst
);
940 rs
= MIPSInst_RS(inst
);
943 if ((long)regs
->regs
[rs
] >= MIPSInst_SIMM(inst
))
944 do_trap_or_bp(regs
, 0, 0, "TGEI");
946 MIPS_R2_STATS(traps
);
950 if (regs
->regs
[rs
] >= MIPSInst_UIMM(inst
))
951 do_trap_or_bp(regs
, 0, 0, "TGEIU");
953 MIPS_R2_STATS(traps
);
957 if ((long)regs
->regs
[rs
] < MIPSInst_SIMM(inst
))
958 do_trap_or_bp(regs
, 0, 0, "TLTI");
960 MIPS_R2_STATS(traps
);
964 if (regs
->regs
[rs
] < MIPSInst_UIMM(inst
))
965 do_trap_or_bp(regs
, 0, 0, "TLTIU");
967 MIPS_R2_STATS(traps
);
971 if (regs
->regs
[rs
] == MIPSInst_SIMM(inst
))
972 do_trap_or_bp(regs
, 0, 0, "TEQI");
974 MIPS_R2_STATS(traps
);
978 if (regs
->regs
[rs
] != MIPSInst_SIMM(inst
))
979 do_trap_or_bp(regs
, 0, 0, "TNEI");
981 MIPS_R2_STATS(traps
);
988 if (delay_slot(regs
)) {
992 regs
->regs
[31] = r31
;
994 err
= __compute_return_epc(regs
);
997 if (err
!= BRANCH_LIKELY_TAKEN
)
1001 err
= __get_user(nir
, (u32 __user
*)nepc
);
1007 * This will probably be optimized away when
1008 * CONFIG_DEBUG_FS is not enabled
1012 MIPS_R2BR_STATS(bltzl
);
1015 MIPS_R2BR_STATS(bgezl
);
1018 MIPS_R2BR_STATS(bltzall
);
1021 MIPS_R2BR_STATS(bgezall
);
1025 switch (MIPSInst_OPCODE(nir
)) {
1030 regs
->cp0_cause
|= CAUSEF_BD
;
1034 err
= mipsr6_emul(regs
, nir
);
1036 err
= mips_dsemul(regs
, nir
, epc
, cpc
);
1039 MIPS_R2_STATS(dsemul
);
1045 if (delay_slot(regs
)) {
1049 regs
->regs
[31] = r31
;
1050 regs
->cp0_epc
= epc
;
1051 err
= __compute_return_epc(regs
);
1054 cpc
= regs
->cp0_epc
;
1056 err
= __get_user(nir
, (u32 __user
*)nepc
);
1062 * This will probably be optimized away when
1063 * CONFIG_DEBUG_FS is not enabled
1067 MIPS_R2BR_STATS(bltzal
);
1070 MIPS_R2BR_STATS(bgezal
);
1074 switch (MIPSInst_OPCODE(nir
)) {
1079 regs
->cp0_cause
|= CAUSEF_BD
;
1083 err
= mipsr6_emul(regs
, nir
);
1085 err
= mips_dsemul(regs
, nir
, epc
, cpc
);
1088 MIPS_R2_STATS(dsemul
);
1093 regs
->regs
[31] = r31
;
1094 regs
->cp0_epc
= epc
;
1104 if (delay_slot(regs
)) {
1108 regs
->regs
[31] = r31
;
1109 regs
->cp0_epc
= epc
;
1110 err
= __compute_return_epc(regs
);
1113 if (err
!= BRANCH_LIKELY_TAKEN
)
1115 cpc
= regs
->cp0_epc
;
1117 err
= __get_user(nir
, (u32 __user
*)nepc
);
1123 * This will probably be optimized away when
1124 * CONFIG_DEBUG_FS is not enabled
1126 switch (MIPSInst_OPCODE(inst
)) {
1128 MIPS_R2BR_STATS(beql
);
1131 MIPS_R2BR_STATS(bnel
);
1134 MIPS_R2BR_STATS(blezl
);
1137 MIPS_R2BR_STATS(bgtzl
);
1141 switch (MIPSInst_OPCODE(nir
)) {
1146 regs
->cp0_cause
|= CAUSEF_BD
;
1150 err
= mipsr6_emul(regs
, nir
);
1152 err
= mips_dsemul(regs
, nir
, epc
, cpc
);
1155 MIPS_R2_STATS(dsemul
);
1164 regs
->regs
[31] = r31
;
1165 regs
->cp0_epc
= epc
;
1166 if (!used_math()) { /* First time FPU user. */
1172 lose_fpu(1); /* Save FPU state for the emulator. */
1174 err
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 0,
1176 *fcr31
= current
->thread
.fpu
.fcr31
;
1179 * We can't allow the emulated instruction to leave any of
1180 * the cause bits set in $fcr31.
1182 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
1185 * this is a tricky issue - lose_fpu() uses LL/SC atomics
1186 * if FPU is owned and effectively cancels user level LL/SC.
1187 * So, it could be logical to don't restore FPU ownership here.
1188 * But the sequence of multiple FPU instructions is much much
1189 * more often than LL-FPU-SC and I prefer loop here until
1190 * next scheduler cycle cancels FPU ownership
1192 own_fpu(1); /* Restore FPU state. */
1195 current
->thread
.cp0_baduaddr
= (unsigned long)fault_addr
;
1197 MIPS_R2_STATS(fpus
);
1202 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1203 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1204 if (!access_ok(VERIFY_READ
, vaddr
, 4)) {
1205 current
->thread
.cp0_baduaddr
= vaddr
;
1209 __asm__
__volatile__(
1212 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1213 "1:" LB
"%1, 0(%2)\n"
1214 INS
"%0, %1, 24, 8\n"
1215 " andi %1, %2, 0x3\n"
1217 ADDIU
"%2, %2, -1\n"
1218 "2:" LB
"%1, 0(%2)\n"
1219 INS
"%0, %1, 16, 8\n"
1220 " andi %1, %2, 0x3\n"
1222 ADDIU
"%2, %2, -1\n"
1223 "3:" LB
"%1, 0(%2)\n"
1224 INS
"%0, %1, 8, 8\n"
1225 " andi %1, %2, 0x3\n"
1227 ADDIU
"%2, %2, -1\n"
1228 "4:" LB
"%1, 0(%2)\n"
1229 INS
"%0, %1, 0, 8\n"
1230 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1231 "1:" LB
"%1, 0(%2)\n"
1232 INS
"%0, %1, 24, 8\n"
1234 " andi %1, %2, 0x3\n"
1236 "2:" LB
"%1, 0(%2)\n"
1237 INS
"%0, %1, 16, 8\n"
1239 " andi %1, %2, 0x3\n"
1241 "3:" LB
"%1, 0(%2)\n"
1242 INS
"%0, %1, 8, 8\n"
1244 " andi %1, %2, 0x3\n"
1246 "4:" LB
"%1, 0(%2)\n"
1247 INS
"%0, %1, 0, 8\n"
1248 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1249 "9: sll %0, %0, 0\n"
1252 " .section .fixup,\"ax\"\n"
1256 " .section __ex_table,\"a\"\n"
1263 : "+&r"(rt
), "=&r"(rs
),
1264 "+&r"(vaddr
), "+&r"(err
)
1267 if (MIPSInst_RT(inst
) && !err
)
1268 regs
->regs
[MIPSInst_RT(inst
)] = rt
;
1270 MIPS_R2_STATS(loads
);
1275 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1276 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1277 if (!access_ok(VERIFY_READ
, vaddr
, 4)) {
1278 current
->thread
.cp0_baduaddr
= vaddr
;
1282 __asm__
__volatile__(
1285 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1286 "1:" LB
"%1, 0(%2)\n"
1287 INS
"%0, %1, 0, 8\n"
1289 " andi %1, %2, 0x3\n"
1291 "2:" LB
"%1, 0(%2)\n"
1292 INS
"%0, %1, 8, 8\n"
1294 " andi %1, %2, 0x3\n"
1296 "3:" LB
"%1, 0(%2)\n"
1297 INS
"%0, %1, 16, 8\n"
1299 " andi %1, %2, 0x3\n"
1301 "4:" LB
"%1, 0(%2)\n"
1302 INS
"%0, %1, 24, 8\n"
1304 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1305 "1:" LB
"%1, 0(%2)\n"
1306 INS
"%0, %1, 0, 8\n"
1307 " andi %1, %2, 0x3\n"
1309 ADDIU
"%2, %2, -1\n"
1310 "2:" LB
"%1, 0(%2)\n"
1311 INS
"%0, %1, 8, 8\n"
1312 " andi %1, %2, 0x3\n"
1314 ADDIU
"%2, %2, -1\n"
1315 "3:" LB
"%1, 0(%2)\n"
1316 INS
"%0, %1, 16, 8\n"
1317 " andi %1, %2, 0x3\n"
1319 ADDIU
"%2, %2, -1\n"
1320 "4:" LB
"%1, 0(%2)\n"
1321 INS
"%0, %1, 24, 8\n"
1323 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1327 " .section .fixup,\"ax\"\n"
1331 " .section __ex_table,\"a\"\n"
1338 : "+&r"(rt
), "=&r"(rs
),
1339 "+&r"(vaddr
), "+&r"(err
)
1341 if (MIPSInst_RT(inst
) && !err
)
1342 regs
->regs
[MIPSInst_RT(inst
)] = rt
;
1344 MIPS_R2_STATS(loads
);
1349 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1350 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1351 if (!access_ok(VERIFY_WRITE
, vaddr
, 4)) {
1352 current
->thread
.cp0_baduaddr
= vaddr
;
1356 __asm__
__volatile__(
1359 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1360 EXT
"%1, %0, 24, 8\n"
1361 "1:" SB
"%1, 0(%2)\n"
1362 " andi %1, %2, 0x3\n"
1364 ADDIU
"%2, %2, -1\n"
1365 EXT
"%1, %0, 16, 8\n"
1366 "2:" SB
"%1, 0(%2)\n"
1367 " andi %1, %2, 0x3\n"
1369 ADDIU
"%2, %2, -1\n"
1370 EXT
"%1, %0, 8, 8\n"
1371 "3:" SB
"%1, 0(%2)\n"
1372 " andi %1, %2, 0x3\n"
1374 ADDIU
"%2, %2, -1\n"
1375 EXT
"%1, %0, 0, 8\n"
1376 "4:" SB
"%1, 0(%2)\n"
1377 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1378 EXT
"%1, %0, 24, 8\n"
1379 "1:" SB
"%1, 0(%2)\n"
1381 " andi %1, %2, 0x3\n"
1383 EXT
"%1, %0, 16, 8\n"
1384 "2:" SB
"%1, 0(%2)\n"
1386 " andi %1, %2, 0x3\n"
1388 EXT
"%1, %0, 8, 8\n"
1389 "3:" SB
"%1, 0(%2)\n"
1391 " andi %1, %2, 0x3\n"
1393 EXT
"%1, %0, 0, 8\n"
1394 "4:" SB
"%1, 0(%2)\n"
1395 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1398 " .section .fixup,\"ax\"\n"
1402 " .section __ex_table,\"a\"\n"
1409 : "+&r"(rt
), "=&r"(rs
),
1410 "+&r"(vaddr
), "+&r"(err
)
1414 MIPS_R2_STATS(stores
);
1419 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1420 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1421 if (!access_ok(VERIFY_WRITE
, vaddr
, 4)) {
1422 current
->thread
.cp0_baduaddr
= vaddr
;
1426 __asm__
__volatile__(
1429 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1430 EXT
"%1, %0, 0, 8\n"
1431 "1:" SB
"%1, 0(%2)\n"
1433 " andi %1, %2, 0x3\n"
1435 EXT
"%1, %0, 8, 8\n"
1436 "2:" SB
"%1, 0(%2)\n"
1438 " andi %1, %2, 0x3\n"
1440 EXT
"%1, %0, 16, 8\n"
1441 "3:" SB
"%1, 0(%2)\n"
1443 " andi %1, %2, 0x3\n"
1445 EXT
"%1, %0, 24, 8\n"
1446 "4:" SB
"%1, 0(%2)\n"
1447 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1448 EXT
"%1, %0, 0, 8\n"
1449 "1:" SB
"%1, 0(%2)\n"
1450 " andi %1, %2, 0x3\n"
1452 ADDIU
"%2, %2, -1\n"
1453 EXT
"%1, %0, 8, 8\n"
1454 "2:" SB
"%1, 0(%2)\n"
1455 " andi %1, %2, 0x3\n"
1457 ADDIU
"%2, %2, -1\n"
1458 EXT
"%1, %0, 16, 8\n"
1459 "3:" SB
"%1, 0(%2)\n"
1460 " andi %1, %2, 0x3\n"
1462 ADDIU
"%2, %2, -1\n"
1463 EXT
"%1, %0, 24, 8\n"
1464 "4:" SB
"%1, 0(%2)\n"
1465 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1468 " .section .fixup,\"ax\"\n"
1472 " .section __ex_table,\"a\"\n"
1479 : "+&r"(rt
), "=&r"(rs
),
1480 "+&r"(vaddr
), "+&r"(err
)
1484 MIPS_R2_STATS(stores
);
1489 if (IS_ENABLED(CONFIG_32BIT
)) {
1494 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1495 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1496 if (!access_ok(VERIFY_READ
, vaddr
, 8)) {
1497 current
->thread
.cp0_baduaddr
= vaddr
;
1501 __asm__
__volatile__(
1504 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1506 " dinsu %0, %1, 56, 8\n"
1507 " andi %1, %2, 0x7\n"
1509 " daddiu %2, %2, -1\n"
1511 " dinsu %0, %1, 48, 8\n"
1512 " andi %1, %2, 0x7\n"
1514 " daddiu %2, %2, -1\n"
1516 " dinsu %0, %1, 40, 8\n"
1517 " andi %1, %2, 0x7\n"
1519 " daddiu %2, %2, -1\n"
1521 " dinsu %0, %1, 32, 8\n"
1522 " andi %1, %2, 0x7\n"
1524 " daddiu %2, %2, -1\n"
1526 " dins %0, %1, 24, 8\n"
1527 " andi %1, %2, 0x7\n"
1529 " daddiu %2, %2, -1\n"
1531 " dins %0, %1, 16, 8\n"
1532 " andi %1, %2, 0x7\n"
1534 " daddiu %2, %2, -1\n"
1536 " dins %0, %1, 8, 8\n"
1537 " andi %1, %2, 0x7\n"
1539 " daddiu %2, %2, -1\n"
1541 " dins %0, %1, 0, 8\n"
1542 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1544 " dinsu %0, %1, 56, 8\n"
1545 " daddiu %2, %2, 1\n"
1546 " andi %1, %2, 0x7\n"
1549 " dinsu %0, %1, 48, 8\n"
1550 " daddiu %2, %2, 1\n"
1551 " andi %1, %2, 0x7\n"
1554 " dinsu %0, %1, 40, 8\n"
1555 " daddiu %2, %2, 1\n"
1556 " andi %1, %2, 0x7\n"
1559 " dinsu %0, %1, 32, 8\n"
1560 " daddiu %2, %2, 1\n"
1561 " andi %1, %2, 0x7\n"
1564 " dins %0, %1, 24, 8\n"
1565 " daddiu %2, %2, 1\n"
1566 " andi %1, %2, 0x7\n"
1569 " dins %0, %1, 16, 8\n"
1570 " daddiu %2, %2, 1\n"
1571 " andi %1, %2, 0x7\n"
1574 " dins %0, %1, 8, 8\n"
1575 " daddiu %2, %2, 1\n"
1576 " andi %1, %2, 0x7\n"
1579 " dins %0, %1, 0, 8\n"
1580 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1583 " .section .fixup,\"ax\"\n"
1587 " .section __ex_table,\"a\"\n"
1598 : "+&r"(rt
), "=&r"(rs
),
1599 "+&r"(vaddr
), "+&r"(err
)
1601 if (MIPSInst_RT(inst
) && !err
)
1602 regs
->regs
[MIPSInst_RT(inst
)] = rt
;
1604 MIPS_R2_STATS(loads
);
1608 if (IS_ENABLED(CONFIG_32BIT
)) {
1613 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1614 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1615 if (!access_ok(VERIFY_READ
, vaddr
, 8)) {
1616 current
->thread
.cp0_baduaddr
= vaddr
;
1620 __asm__
__volatile__(
1623 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1625 " dins %0, %1, 0, 8\n"
1626 " daddiu %2, %2, 1\n"
1627 " andi %1, %2, 0x7\n"
1630 " dins %0, %1, 8, 8\n"
1631 " daddiu %2, %2, 1\n"
1632 " andi %1, %2, 0x7\n"
1635 " dins %0, %1, 16, 8\n"
1636 " daddiu %2, %2, 1\n"
1637 " andi %1, %2, 0x7\n"
1640 " dins %0, %1, 24, 8\n"
1641 " daddiu %2, %2, 1\n"
1642 " andi %1, %2, 0x7\n"
1645 " dinsu %0, %1, 32, 8\n"
1646 " daddiu %2, %2, 1\n"
1647 " andi %1, %2, 0x7\n"
1650 " dinsu %0, %1, 40, 8\n"
1651 " daddiu %2, %2, 1\n"
1652 " andi %1, %2, 0x7\n"
1655 " dinsu %0, %1, 48, 8\n"
1656 " daddiu %2, %2, 1\n"
1657 " andi %1, %2, 0x7\n"
1660 " dinsu %0, %1, 56, 8\n"
1661 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1663 " dins %0, %1, 0, 8\n"
1664 " andi %1, %2, 0x7\n"
1666 " daddiu %2, %2, -1\n"
1668 " dins %0, %1, 8, 8\n"
1669 " andi %1, %2, 0x7\n"
1671 " daddiu %2, %2, -1\n"
1673 " dins %0, %1, 16, 8\n"
1674 " andi %1, %2, 0x7\n"
1676 " daddiu %2, %2, -1\n"
1678 " dins %0, %1, 24, 8\n"
1679 " andi %1, %2, 0x7\n"
1681 " daddiu %2, %2, -1\n"
1683 " dinsu %0, %1, 32, 8\n"
1684 " andi %1, %2, 0x7\n"
1686 " daddiu %2, %2, -1\n"
1688 " dinsu %0, %1, 40, 8\n"
1689 " andi %1, %2, 0x7\n"
1691 " daddiu %2, %2, -1\n"
1693 " dinsu %0, %1, 48, 8\n"
1694 " andi %1, %2, 0x7\n"
1696 " daddiu %2, %2, -1\n"
1698 " dinsu %0, %1, 56, 8\n"
1699 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1702 " .section .fixup,\"ax\"\n"
1706 " .section __ex_table,\"a\"\n"
1717 : "+&r"(rt
), "=&r"(rs
),
1718 "+&r"(vaddr
), "+&r"(err
)
1720 if (MIPSInst_RT(inst
) && !err
)
1721 regs
->regs
[MIPSInst_RT(inst
)] = rt
;
1723 MIPS_R2_STATS(loads
);
1727 if (IS_ENABLED(CONFIG_32BIT
)) {
1732 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1733 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1734 if (!access_ok(VERIFY_WRITE
, vaddr
, 8)) {
1735 current
->thread
.cp0_baduaddr
= vaddr
;
1739 __asm__
__volatile__(
1742 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1743 " dextu %1, %0, 56, 8\n"
1745 " andi %1, %2, 0x7\n"
1747 " daddiu %2, %2, -1\n"
1748 " dextu %1, %0, 48, 8\n"
1750 " andi %1, %2, 0x7\n"
1752 " daddiu %2, %2, -1\n"
1753 " dextu %1, %0, 40, 8\n"
1755 " andi %1, %2, 0x7\n"
1757 " daddiu %2, %2, -1\n"
1758 " dextu %1, %0, 32, 8\n"
1760 " andi %1, %2, 0x7\n"
1762 " daddiu %2, %2, -1\n"
1763 " dext %1, %0, 24, 8\n"
1765 " andi %1, %2, 0x7\n"
1767 " daddiu %2, %2, -1\n"
1768 " dext %1, %0, 16, 8\n"
1770 " andi %1, %2, 0x7\n"
1772 " daddiu %2, %2, -1\n"
1773 " dext %1, %0, 8, 8\n"
1775 " andi %1, %2, 0x7\n"
1777 " daddiu %2, %2, -1\n"
1778 " dext %1, %0, 0, 8\n"
1780 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1781 " dextu %1, %0, 56, 8\n"
1783 " daddiu %2, %2, 1\n"
1784 " andi %1, %2, 0x7\n"
1786 " dextu %1, %0, 48, 8\n"
1788 " daddiu %2, %2, 1\n"
1789 " andi %1, %2, 0x7\n"
1791 " dextu %1, %0, 40, 8\n"
1793 " daddiu %2, %2, 1\n"
1794 " andi %1, %2, 0x7\n"
1796 " dextu %1, %0, 32, 8\n"
1798 " daddiu %2, %2, 1\n"
1799 " andi %1, %2, 0x7\n"
1801 " dext %1, %0, 24, 8\n"
1803 " daddiu %2, %2, 1\n"
1804 " andi %1, %2, 0x7\n"
1806 " dext %1, %0, 16, 8\n"
1808 " daddiu %2, %2, 1\n"
1809 " andi %1, %2, 0x7\n"
1811 " dext %1, %0, 8, 8\n"
1813 " daddiu %2, %2, 1\n"
1814 " andi %1, %2, 0x7\n"
1816 " dext %1, %0, 0, 8\n"
1818 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1821 " .section .fixup,\"ax\"\n"
1825 " .section __ex_table,\"a\"\n"
1836 : "+&r"(rt
), "=&r"(rs
),
1837 "+&r"(vaddr
), "+&r"(err
)
1841 MIPS_R2_STATS(stores
);
1845 if (IS_ENABLED(CONFIG_32BIT
)) {
1850 rt
= regs
->regs
[MIPSInst_RT(inst
)];
1851 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1852 if (!access_ok(VERIFY_WRITE
, vaddr
, 8)) {
1853 current
->thread
.cp0_baduaddr
= vaddr
;
1857 __asm__
__volatile__(
1860 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1861 " dext %1, %0, 0, 8\n"
1863 " daddiu %2, %2, 1\n"
1864 " andi %1, %2, 0x7\n"
1866 " dext %1, %0, 8, 8\n"
1868 " daddiu %2, %2, 1\n"
1869 " andi %1, %2, 0x7\n"
1871 " dext %1, %0, 16, 8\n"
1873 " daddiu %2, %2, 1\n"
1874 " andi %1, %2, 0x7\n"
1876 " dext %1, %0, 24, 8\n"
1878 " daddiu %2, %2, 1\n"
1879 " andi %1, %2, 0x7\n"
1881 " dextu %1, %0, 32, 8\n"
1883 " daddiu %2, %2, 1\n"
1884 " andi %1, %2, 0x7\n"
1886 " dextu %1, %0, 40, 8\n"
1888 " daddiu %2, %2, 1\n"
1889 " andi %1, %2, 0x7\n"
1891 " dextu %1, %0, 48, 8\n"
1893 " daddiu %2, %2, 1\n"
1894 " andi %1, %2, 0x7\n"
1896 " dextu %1, %0, 56, 8\n"
1898 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1899 " dext %1, %0, 0, 8\n"
1901 " andi %1, %2, 0x7\n"
1903 " daddiu %2, %2, -1\n"
1904 " dext %1, %0, 8, 8\n"
1906 " andi %1, %2, 0x7\n"
1908 " daddiu %2, %2, -1\n"
1909 " dext %1, %0, 16, 8\n"
1911 " andi %1, %2, 0x7\n"
1913 " daddiu %2, %2, -1\n"
1914 " dext %1, %0, 24, 8\n"
1916 " andi %1, %2, 0x7\n"
1918 " daddiu %2, %2, -1\n"
1919 " dextu %1, %0, 32, 8\n"
1921 " andi %1, %2, 0x7\n"
1923 " daddiu %2, %2, -1\n"
1924 " dextu %1, %0, 40, 8\n"
1926 " andi %1, %2, 0x7\n"
1928 " daddiu %2, %2, -1\n"
1929 " dextu %1, %0, 48, 8\n"
1931 " andi %1, %2, 0x7\n"
1933 " daddiu %2, %2, -1\n"
1934 " dextu %1, %0, 56, 8\n"
1936 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1939 " .section .fixup,\"ax\"\n"
1943 " .section __ex_table,\"a\"\n"
1954 : "+&r"(rt
), "=&r"(rs
),
1955 "+&r"(vaddr
), "+&r"(err
)
1959 MIPS_R2_STATS(stores
);
1963 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
1965 current
->thread
.cp0_baduaddr
= vaddr
;
1969 if (!access_ok(VERIFY_READ
, vaddr
, 4)) {
1970 current
->thread
.cp0_baduaddr
= vaddr
;
1975 if (!cpu_has_rw_llb
) {
1977 * An LL/SC block can't be safely emulated without
1978 * a Config5/LLB availability. So it's probably time to
1979 * kill our process before things get any worse. This is
1980 * because Config5/LLB allows us to use ERETNC so that
1981 * the LLAddr/LLB bit is not cleared when we return from
1982 * an exception. MIPS R2 LL/SC instructions trap with an
1983 * RI exception so once we emulate them here, we return
1984 * back to userland with ERETNC. That preserves the
1985 * LLAddr/LLB so the subsequent SC instruction will
1986 * succeed preserving the atomic semantics of the LL/SC
1987 * block. Without that, there is no safe way to emulate
1988 * an LL/SC block in MIPSR2 userland.
1990 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
1995 __asm__
__volatile__(
2000 ".section .fixup,\"ax\"\n"
2005 ".section __ex_table,\"a\"\n"
2008 : "=&r"(res
), "+&r"(err
)
2009 : "r"(vaddr
), "i"(SIGSEGV
)
2012 if (MIPSInst_RT(inst
) && !err
)
2013 regs
->regs
[MIPSInst_RT(inst
)] = res
;
2014 MIPS_R2_STATS(llsc
);
2019 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
2021 current
->thread
.cp0_baduaddr
= vaddr
;
2025 if (!access_ok(VERIFY_WRITE
, vaddr
, 4)) {
2026 current
->thread
.cp0_baduaddr
= vaddr
;
2031 if (!cpu_has_rw_llb
) {
2033 * An LL/SC block can't be safely emulated without
2034 * a Config5/LLB availability. So it's probably time to
2035 * kill our process before things get any worse. This is
2036 * because Config5/LLB allows us to use ERETNC so that
2037 * the LLAddr/LLB bit is not cleared when we return from
2038 * an exception. MIPS R2 LL/SC instructions trap with an
2039 * RI exception so once we emulate them here, we return
2040 * back to userland with ERETNC. That preserves the
2041 * LLAddr/LLB so the subsequent SC instruction will
2042 * succeed preserving the atomic semantics of the LL/SC
2043 * block. Without that, there is no safe way to emulate
2044 * an LL/SC block in MIPSR2 userland.
2046 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2051 res
= regs
->regs
[MIPSInst_RT(inst
)];
2053 __asm__
__volatile__(
2058 ".section .fixup,\"ax\"\n"
2063 ".section __ex_table,\"a\"\n"
2066 : "+&r"(res
), "+&r"(err
)
2067 : "r"(vaddr
), "i"(SIGSEGV
));
2069 if (MIPSInst_RT(inst
) && !err
)
2070 regs
->regs
[MIPSInst_RT(inst
)] = res
;
2072 MIPS_R2_STATS(llsc
);
2077 if (IS_ENABLED(CONFIG_32BIT
)) {
2082 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
2084 current
->thread
.cp0_baduaddr
= vaddr
;
2088 if (!access_ok(VERIFY_READ
, vaddr
, 8)) {
2089 current
->thread
.cp0_baduaddr
= vaddr
;
2094 if (!cpu_has_rw_llb
) {
2096 * An LL/SC block can't be safely emulated without
2097 * a Config5/LLB availability. So it's probably time to
2098 * kill our process before things get any worse. This is
2099 * because Config5/LLB allows us to use ERETNC so that
2100 * the LLAddr/LLB bit is not cleared when we return from
2101 * an exception. MIPS R2 LL/SC instructions trap with an
2102 * RI exception so once we emulate them here, we return
2103 * back to userland with ERETNC. That preserves the
2104 * LLAddr/LLB so the subsequent SC instruction will
2105 * succeed preserving the atomic semantics of the LL/SC
2106 * block. Without that, there is no safe way to emulate
2107 * an LL/SC block in MIPSR2 userland.
2109 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2114 __asm__
__volatile__(
2119 ".section .fixup,\"ax\"\n"
2124 ".section __ex_table,\"a\"\n"
2127 : "=&r"(res
), "+&r"(err
)
2128 : "r"(vaddr
), "i"(SIGSEGV
)
2130 if (MIPSInst_RT(inst
) && !err
)
2131 regs
->regs
[MIPSInst_RT(inst
)] = res
;
2133 MIPS_R2_STATS(llsc
);
2138 if (IS_ENABLED(CONFIG_32BIT
)) {
2143 vaddr
= regs
->regs
[MIPSInst_RS(inst
)] + MIPSInst_SIMM(inst
);
2145 current
->thread
.cp0_baduaddr
= vaddr
;
2149 if (!access_ok(VERIFY_WRITE
, vaddr
, 8)) {
2150 current
->thread
.cp0_baduaddr
= vaddr
;
2155 if (!cpu_has_rw_llb
) {
2157 * An LL/SC block can't be safely emulated without
2158 * a Config5/LLB availability. So it's probably time to
2159 * kill our process before things get any worse. This is
2160 * because Config5/LLB allows us to use ERETNC so that
2161 * the LLAddr/LLB bit is not cleared when we return from
2162 * an exception. MIPS R2 LL/SC instructions trap with an
2163 * RI exception so once we emulate them here, we return
2164 * back to userland with ERETNC. That preserves the
2165 * LLAddr/LLB so the subsequent SC instruction will
2166 * succeed preserving the atomic semantics of the LL/SC
2167 * block. Without that, there is no safe way to emulate
2168 * an LL/SC block in MIPSR2 userland.
2170 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2175 res
= regs
->regs
[MIPSInst_RT(inst
)];
2177 __asm__
__volatile__(
2182 ".section .fixup,\"ax\"\n"
2187 ".section __ex_table,\"a\"\n"
2190 : "+&r"(res
), "+&r"(err
)
2191 : "r"(vaddr
), "i"(SIGSEGV
));
2193 if (MIPSInst_RT(inst
) && !err
)
2194 regs
->regs
[MIPSInst_RT(inst
)] = res
;
2196 MIPS_R2_STATS(llsc
);
2207 * Let's not return to userland just yet. It's costly and
2208 * it's likely we have more R2 instructions to emulate
2210 if (!err
&& (pass
++ < MIPS_R2_EMUL_TOTAL_PASS
)) {
2211 regs
->cp0_cause
&= ~CAUSEF_BD
;
2212 err
= get_user(inst
, (u32 __user
*)regs
->cp0_epc
);
2220 if (err
&& (err
!= SIGEMT
)) {
2221 regs
->regs
[31] = r31
;
2222 regs
->cp0_epc
= epc
;
2225 /* Likely a MIPS R6 compatible instruction */
2226 if (pass
&& (err
== SIGILL
))
2232 #ifdef CONFIG_DEBUG_FS
2234 static int mipsr2_stats_show(struct seq_file
*s
, void *unused
)
2237 seq_printf(s
, "Instruction\tTotal\tBDslot\n------------------------------\n");
2238 seq_printf(s
, "movs\t\t%ld\t%ld\n",
2239 (unsigned long)__this_cpu_read(mipsr2emustats
.movs
),
2240 (unsigned long)__this_cpu_read(mipsr2bdemustats
.movs
));
2241 seq_printf(s
, "hilo\t\t%ld\t%ld\n",
2242 (unsigned long)__this_cpu_read(mipsr2emustats
.hilo
),
2243 (unsigned long)__this_cpu_read(mipsr2bdemustats
.hilo
));
2244 seq_printf(s
, "muls\t\t%ld\t%ld\n",
2245 (unsigned long)__this_cpu_read(mipsr2emustats
.muls
),
2246 (unsigned long)__this_cpu_read(mipsr2bdemustats
.muls
));
2247 seq_printf(s
, "divs\t\t%ld\t%ld\n",
2248 (unsigned long)__this_cpu_read(mipsr2emustats
.divs
),
2249 (unsigned long)__this_cpu_read(mipsr2bdemustats
.divs
));
2250 seq_printf(s
, "dsps\t\t%ld\t%ld\n",
2251 (unsigned long)__this_cpu_read(mipsr2emustats
.dsps
),
2252 (unsigned long)__this_cpu_read(mipsr2bdemustats
.dsps
));
2253 seq_printf(s
, "bops\t\t%ld\t%ld\n",
2254 (unsigned long)__this_cpu_read(mipsr2emustats
.bops
),
2255 (unsigned long)__this_cpu_read(mipsr2bdemustats
.bops
));
2256 seq_printf(s
, "traps\t\t%ld\t%ld\n",
2257 (unsigned long)__this_cpu_read(mipsr2emustats
.traps
),
2258 (unsigned long)__this_cpu_read(mipsr2bdemustats
.traps
));
2259 seq_printf(s
, "fpus\t\t%ld\t%ld\n",
2260 (unsigned long)__this_cpu_read(mipsr2emustats
.fpus
),
2261 (unsigned long)__this_cpu_read(mipsr2bdemustats
.fpus
));
2262 seq_printf(s
, "loads\t\t%ld\t%ld\n",
2263 (unsigned long)__this_cpu_read(mipsr2emustats
.loads
),
2264 (unsigned long)__this_cpu_read(mipsr2bdemustats
.loads
));
2265 seq_printf(s
, "stores\t\t%ld\t%ld\n",
2266 (unsigned long)__this_cpu_read(mipsr2emustats
.stores
),
2267 (unsigned long)__this_cpu_read(mipsr2bdemustats
.stores
));
2268 seq_printf(s
, "llsc\t\t%ld\t%ld\n",
2269 (unsigned long)__this_cpu_read(mipsr2emustats
.llsc
),
2270 (unsigned long)__this_cpu_read(mipsr2bdemustats
.llsc
));
2271 seq_printf(s
, "dsemul\t\t%ld\t%ld\n",
2272 (unsigned long)__this_cpu_read(mipsr2emustats
.dsemul
),
2273 (unsigned long)__this_cpu_read(mipsr2bdemustats
.dsemul
));
2274 seq_printf(s
, "jr\t\t%ld\n",
2275 (unsigned long)__this_cpu_read(mipsr2bremustats
.jrs
));
2276 seq_printf(s
, "bltzl\t\t%ld\n",
2277 (unsigned long)__this_cpu_read(mipsr2bremustats
.bltzl
));
2278 seq_printf(s
, "bgezl\t\t%ld\n",
2279 (unsigned long)__this_cpu_read(mipsr2bremustats
.bgezl
));
2280 seq_printf(s
, "bltzll\t\t%ld\n",
2281 (unsigned long)__this_cpu_read(mipsr2bremustats
.bltzll
));
2282 seq_printf(s
, "bgezll\t\t%ld\n",
2283 (unsigned long)__this_cpu_read(mipsr2bremustats
.bgezll
));
2284 seq_printf(s
, "bltzal\t\t%ld\n",
2285 (unsigned long)__this_cpu_read(mipsr2bremustats
.bltzal
));
2286 seq_printf(s
, "bgezal\t\t%ld\n",
2287 (unsigned long)__this_cpu_read(mipsr2bremustats
.bgezal
));
2288 seq_printf(s
, "beql\t\t%ld\n",
2289 (unsigned long)__this_cpu_read(mipsr2bremustats
.beql
));
2290 seq_printf(s
, "bnel\t\t%ld\n",
2291 (unsigned long)__this_cpu_read(mipsr2bremustats
.bnel
));
2292 seq_printf(s
, "blezl\t\t%ld\n",
2293 (unsigned long)__this_cpu_read(mipsr2bremustats
.blezl
));
2294 seq_printf(s
, "bgtzl\t\t%ld\n",
2295 (unsigned long)__this_cpu_read(mipsr2bremustats
.bgtzl
));
2300 static int mipsr2_stats_clear_show(struct seq_file
*s
, void *unused
)
2302 mipsr2_stats_show(s
, unused
);
2304 __this_cpu_write((mipsr2emustats
).movs
, 0);
2305 __this_cpu_write((mipsr2bdemustats
).movs
, 0);
2306 __this_cpu_write((mipsr2emustats
).hilo
, 0);
2307 __this_cpu_write((mipsr2bdemustats
).hilo
, 0);
2308 __this_cpu_write((mipsr2emustats
).muls
, 0);
2309 __this_cpu_write((mipsr2bdemustats
).muls
, 0);
2310 __this_cpu_write((mipsr2emustats
).divs
, 0);
2311 __this_cpu_write((mipsr2bdemustats
).divs
, 0);
2312 __this_cpu_write((mipsr2emustats
).dsps
, 0);
2313 __this_cpu_write((mipsr2bdemustats
).dsps
, 0);
2314 __this_cpu_write((mipsr2emustats
).bops
, 0);
2315 __this_cpu_write((mipsr2bdemustats
).bops
, 0);
2316 __this_cpu_write((mipsr2emustats
).traps
, 0);
2317 __this_cpu_write((mipsr2bdemustats
).traps
, 0);
2318 __this_cpu_write((mipsr2emustats
).fpus
, 0);
2319 __this_cpu_write((mipsr2bdemustats
).fpus
, 0);
2320 __this_cpu_write((mipsr2emustats
).loads
, 0);
2321 __this_cpu_write((mipsr2bdemustats
).loads
, 0);
2322 __this_cpu_write((mipsr2emustats
).stores
, 0);
2323 __this_cpu_write((mipsr2bdemustats
).stores
, 0);
2324 __this_cpu_write((mipsr2emustats
).llsc
, 0);
2325 __this_cpu_write((mipsr2bdemustats
).llsc
, 0);
2326 __this_cpu_write((mipsr2emustats
).dsemul
, 0);
2327 __this_cpu_write((mipsr2bdemustats
).dsemul
, 0);
2328 __this_cpu_write((mipsr2bremustats
).jrs
, 0);
2329 __this_cpu_write((mipsr2bremustats
).bltzl
, 0);
2330 __this_cpu_write((mipsr2bremustats
).bgezl
, 0);
2331 __this_cpu_write((mipsr2bremustats
).bltzll
, 0);
2332 __this_cpu_write((mipsr2bremustats
).bgezll
, 0);
2333 __this_cpu_write((mipsr2bremustats
).bltzal
, 0);
2334 __this_cpu_write((mipsr2bremustats
).bgezal
, 0);
2335 __this_cpu_write((mipsr2bremustats
).beql
, 0);
2336 __this_cpu_write((mipsr2bremustats
).bnel
, 0);
2337 __this_cpu_write((mipsr2bremustats
).blezl
, 0);
2338 __this_cpu_write((mipsr2bremustats
).bgtzl
, 0);
2343 static int mipsr2_stats_open(struct inode
*inode
, struct file
*file
)
2345 return single_open(file
, mipsr2_stats_show
, inode
->i_private
);
2348 static int mipsr2_stats_clear_open(struct inode
*inode
, struct file
*file
)
2350 return single_open(file
, mipsr2_stats_clear_show
, inode
->i_private
);
2353 static const struct file_operations mipsr2_emul_fops
= {
2354 .open
= mipsr2_stats_open
,
2356 .llseek
= seq_lseek
,
2357 .release
= single_release
,
2360 static const struct file_operations mipsr2_clear_fops
= {
2361 .open
= mipsr2_stats_clear_open
,
2363 .llseek
= seq_lseek
,
2364 .release
= single_release
,
2368 static int __init
mipsr2_init_debugfs(void)
2370 struct dentry
*mipsr2_emul
;
2372 if (!mips_debugfs_dir
)
2375 mipsr2_emul
= debugfs_create_file("r2_emul_stats", S_IRUGO
,
2376 mips_debugfs_dir
, NULL
,
2381 mipsr2_emul
= debugfs_create_file("r2_emul_stats_clear", S_IRUGO
,
2382 mips_debugfs_dir
, NULL
,
2383 &mipsr2_clear_fops
);
2390 device_initcall(mipsr2_init_debugfs
);
2392 #endif /* CONFIG_DEBUG_FS */