arch/mips/kernel/r4k_fpu.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
   7  *
   8  * Multi-arch abstraction and asm macros for easier reading:
   9  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  10  *
  11  * Carsten Langgaard, carstenl@mips.com
  12  * Copyright (C) 2000 MIPS Technologies, Inc.
  13  * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
  14  */
  15 #include <asm/asm.h>
  16 #include <asm/errno.h>
  17 #include <asm/fpregdef.h>
  18 #include <asm/mipsregs.h>
  19 #include <asm/asm-offsets.h>
  20 #include <asm/regdef.h>
  21
  22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
  23 #undef fp
  24
  25         .macro  EX insn, reg, src
  26         .set    push
  27         SET_HARDFLOAT
  28         .set    nomacro
  29 .ex\@:  \insn   \reg, \src
  30         .set    pop
  31         .section __ex_table,"a"
  32         PTR     .ex\@, fault
  33         .previous
  34         .endm
  35
  36         .set    noreorder
  37
  38 LEAF(_save_fp_context)
  39         .set    push
  40         SET_HARDFLOAT
  41         cfc1    t1, fcr31
  42         .set    pop
  43
  44 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
  45                 defined(CONFIG_CPU_MIPS32_R6)
  46         .set    push
  47         SET_HARDFLOAT
  48 #ifdef CONFIG_CPU_MIPS32_R2
  49         .set    mips32r2
  50         .set    fp=64
  51         mfc0    t0, CP0_STATUS
  52         sll     t0, t0, 5
  53         bgez    t0, 1f                  # skip storing odd if FR=0
  54          nop
  55 #endif
  56         /* Store the 16 odd double precision registers */
  57         EX      sdc1 $f1, SC_FPREGS+8(a0)
  58         EX      sdc1 $f3, SC_FPREGS+24(a0)
  59         EX      sdc1 $f5, SC_FPREGS+40(a0)
  60         EX      sdc1 $f7, SC_FPREGS+56(a0)
  61         EX      sdc1 $f9, SC_FPREGS+72(a0)
  62         EX      sdc1 $f11, SC_FPREGS+88(a0)
  63         EX      sdc1 $f13, SC_FPREGS+104(a0)
  64         EX      sdc1 $f15, SC_FPREGS+120(a0)
  65         EX      sdc1 $f17, SC_FPREGS+136(a0)
  66         EX      sdc1 $f19, SC_FPREGS+152(a0)
  67         EX      sdc1 $f21, SC_FPREGS+168(a0)
  68         EX      sdc1 $f23, SC_FPREGS+184(a0)
  69         EX      sdc1 $f25, SC_FPREGS+200(a0)
  70         EX      sdc1 $f27, SC_FPREGS+216(a0)
  71         EX      sdc1 $f29, SC_FPREGS+232(a0)
  72         EX      sdc1 $f31, SC_FPREGS+248(a0)
  73 1:      .set    pop
  74 #endif
  75
  76         .set push
  77         SET_HARDFLOAT
  78         /* Store the 16 even double precision registers */
  79         EX      sdc1 $f0, SC_FPREGS+0(a0)
  80         EX      sdc1 $f2, SC_FPREGS+16(a0)
  81         EX      sdc1 $f4, SC_FPREGS+32(a0)
  82         EX      sdc1 $f6, SC_FPREGS+48(a0)
  83         EX      sdc1 $f8, SC_FPREGS+64(a0)
  84         EX      sdc1 $f10, SC_FPREGS+80(a0)
  85         EX      sdc1 $f12, SC_FPREGS+96(a0)
  86         EX      sdc1 $f14, SC_FPREGS+112(a0)
  87         EX      sdc1 $f16, SC_FPREGS+128(a0)
  88         EX      sdc1 $f18, SC_FPREGS+144(a0)
  89         EX      sdc1 $f20, SC_FPREGS+160(a0)
  90         EX      sdc1 $f22, SC_FPREGS+176(a0)
  91         EX      sdc1 $f24, SC_FPREGS+192(a0)
  92         EX      sdc1 $f26, SC_FPREGS+208(a0)
  93         EX      sdc1 $f28, SC_FPREGS+224(a0)
  94         EX      sdc1 $f30, SC_FPREGS+240(a0)
  95         EX      sw t1, SC_FPC_CSR(a0)
  96         jr      ra
  97          li     v0, 0                                   # success
  98         .set pop
  99         END(_save_fp_context)
 100
 101 #ifdef CONFIG_MIPS32_COMPAT
 102         /* Save 32-bit process floating point context */
 103 LEAF(_save_fp_context32)
 104         .set push
 105         .set MIPS_ISA_ARCH_LEVEL_RAW
 106         SET_HARDFLOAT
 107         cfc1    t1, fcr31
 108
 109 #ifndef CONFIG_CPU_MIPS64_R6
 110         mfc0    t0, CP0_STATUS
 111         sll     t0, t0, 5
 112         bgez    t0, 1f                  # skip storing odd if FR=0
 113          nop
 114 #endif
 115
 116         /* Store the 16 odd double precision registers */
 117         EX      sdc1 $f1, SC32_FPREGS+8(a0)
 118         EX      sdc1 $f3, SC32_FPREGS+24(a0)
 119         EX      sdc1 $f5, SC32_FPREGS+40(a0)
 120         EX      sdc1 $f7, SC32_FPREGS+56(a0)
 121         EX      sdc1 $f9, SC32_FPREGS+72(a0)
 122         EX      sdc1 $f11, SC32_FPREGS+88(a0)
 123         EX      sdc1 $f13, SC32_FPREGS+104(a0)
 124         EX      sdc1 $f15, SC32_FPREGS+120(a0)
 125         EX      sdc1 $f17, SC32_FPREGS+136(a0)
 126         EX      sdc1 $f19, SC32_FPREGS+152(a0)
 127         EX      sdc1 $f21, SC32_FPREGS+168(a0)
 128         EX      sdc1 $f23, SC32_FPREGS+184(a0)
 129         EX      sdc1 $f25, SC32_FPREGS+200(a0)
 130         EX      sdc1 $f27, SC32_FPREGS+216(a0)
 131         EX      sdc1 $f29, SC32_FPREGS+232(a0)
 132         EX      sdc1 $f31, SC32_FPREGS+248(a0)
 133
 134         /* Store the 16 even double precision registers */
 135 1:      EX      sdc1 $f0, SC32_FPREGS+0(a0)
 136         EX      sdc1 $f2, SC32_FPREGS+16(a0)
 137         EX      sdc1 $f4, SC32_FPREGS+32(a0)
 138         EX      sdc1 $f6, SC32_FPREGS+48(a0)
 139         EX      sdc1 $f8, SC32_FPREGS+64(a0)
 140         EX      sdc1 $f10, SC32_FPREGS+80(a0)
 141         EX      sdc1 $f12, SC32_FPREGS+96(a0)
 142         EX      sdc1 $f14, SC32_FPREGS+112(a0)
 143         EX      sdc1 $f16, SC32_FPREGS+128(a0)
 144         EX      sdc1 $f18, SC32_FPREGS+144(a0)
 145         EX      sdc1 $f20, SC32_FPREGS+160(a0)
 146         EX      sdc1 $f22, SC32_FPREGS+176(a0)
 147         EX      sdc1 $f24, SC32_FPREGS+192(a0)
 148         EX      sdc1 $f26, SC32_FPREGS+208(a0)
 149         EX      sdc1 $f28, SC32_FPREGS+224(a0)
 150         EX      sdc1 $f30, SC32_FPREGS+240(a0)
 151         EX      sw t1, SC32_FPC_CSR(a0)
 152         cfc1    t0, $0                          # implementation/version
 153         EX      sw t0, SC32_FPC_EIR(a0)
 154         .set pop
 155
 156         jr      ra
 157          li     v0, 0                                   # success
 158         END(_save_fp_context32)
 159 #endif
 160
 161 /*
 162  * Restore FPU state:
 163  *  - fp gp registers
 164  *  - cp1 status/control register
 165  */
 166 LEAF(_restore_fp_context)
 167         EX      lw t1, SC_FPC_CSR(a0)
 168
 169 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)  || \
 170                 defined(CONFIG_CPU_MIPS32_R6)
 171         .set    push
 172         SET_HARDFLOAT
 173 #ifdef CONFIG_CPU_MIPS32_R2
 174         .set    mips32r2
 175         .set    fp=64
 176         mfc0    t0, CP0_STATUS
 177         sll     t0, t0, 5
 178         bgez    t0, 1f                  # skip loading odd if FR=0
 179          nop
 180 #endif
 181         EX      ldc1 $f1, SC_FPREGS+8(a0)
 182         EX      ldc1 $f3, SC_FPREGS+24(a0)
 183         EX      ldc1 $f5, SC_FPREGS+40(a0)
 184         EX      ldc1 $f7, SC_FPREGS+56(a0)
 185         EX      ldc1 $f9, SC_FPREGS+72(a0)
 186         EX      ldc1 $f11, SC_FPREGS+88(a0)
 187         EX      ldc1 $f13, SC_FPREGS+104(a0)
 188         EX      ldc1 $f15, SC_FPREGS+120(a0)
 189         EX      ldc1 $f17, SC_FPREGS+136(a0)
 190         EX      ldc1 $f19, SC_FPREGS+152(a0)
 191         EX      ldc1 $f21, SC_FPREGS+168(a0)
 192         EX      ldc1 $f23, SC_FPREGS+184(a0)
 193         EX      ldc1 $f25, SC_FPREGS+200(a0)
 194         EX      ldc1 $f27, SC_FPREGS+216(a0)
 195         EX      ldc1 $f29, SC_FPREGS+232(a0)
 196         EX      ldc1 $f31, SC_FPREGS+248(a0)
 197 1:      .set pop
 198 #endif
 199         .set push
 200         SET_HARDFLOAT
 201         EX      ldc1 $f0, SC_FPREGS+0(a0)
 202         EX      ldc1 $f2, SC_FPREGS+16(a0)
 203         EX      ldc1 $f4, SC_FPREGS+32(a0)
 204         EX      ldc1 $f6, SC_FPREGS+48(a0)
 205         EX      ldc1 $f8, SC_FPREGS+64(a0)
 206         EX      ldc1 $f10, SC_FPREGS+80(a0)
 207         EX      ldc1 $f12, SC_FPREGS+96(a0)
 208         EX      ldc1 $f14, SC_FPREGS+112(a0)
 209         EX      ldc1 $f16, SC_FPREGS+128(a0)
 210         EX      ldc1 $f18, SC_FPREGS+144(a0)
 211         EX      ldc1 $f20, SC_FPREGS+160(a0)
 212         EX      ldc1 $f22, SC_FPREGS+176(a0)
 213         EX      ldc1 $f24, SC_FPREGS+192(a0)
 214         EX      ldc1 $f26, SC_FPREGS+208(a0)
 215         EX      ldc1 $f28, SC_FPREGS+224(a0)
 216         EX      ldc1 $f30, SC_FPREGS+240(a0)
 217         ctc1    t1, fcr31
 218         .set pop
 219         jr      ra
 220          li     v0, 0                                   # success
 221         END(_restore_fp_context)
 222
 223 #ifdef CONFIG_MIPS32_COMPAT
 224 LEAF(_restore_fp_context32)
 225         /* Restore an o32 sigcontext.  */
 226         .set push
 227         SET_HARDFLOAT
 228         EX      lw t1, SC32_FPC_CSR(a0)
 229
 230 #ifndef CONFIG_CPU_MIPS64_R6
 231         mfc0    t0, CP0_STATUS
 232         sll     t0, t0, 5
 233         bgez    t0, 1f                  # skip loading odd if FR=0
 234          nop
 235 #endif
 236
 237         EX      ldc1 $f1, SC32_FPREGS+8(a0)
 238         EX      ldc1 $f3, SC32_FPREGS+24(a0)
 239         EX      ldc1 $f5, SC32_FPREGS+40(a0)
 240         EX      ldc1 $f7, SC32_FPREGS+56(a0)
 241         EX      ldc1 $f9, SC32_FPREGS+72(a0)
 242         EX      ldc1 $f11, SC32_FPREGS+88(a0)
 243         EX      ldc1 $f13, SC32_FPREGS+104(a0)
 244         EX      ldc1 $f15, SC32_FPREGS+120(a0)
 245         EX      ldc1 $f17, SC32_FPREGS+136(a0)
 246         EX      ldc1 $f19, SC32_FPREGS+152(a0)
 247         EX      ldc1 $f21, SC32_FPREGS+168(a0)
 248         EX      ldc1 $f23, SC32_FPREGS+184(a0)
 249         EX      ldc1 $f25, SC32_FPREGS+200(a0)
 250         EX      ldc1 $f27, SC32_FPREGS+216(a0)
 251         EX      ldc1 $f29, SC32_FPREGS+232(a0)
 252         EX      ldc1 $f31, SC32_FPREGS+248(a0)
 253
 254 1:      EX      ldc1 $f0, SC32_FPREGS+0(a0)
 255         EX      ldc1 $f2, SC32_FPREGS+16(a0)
 256         EX      ldc1 $f4, SC32_FPREGS+32(a0)
 257         EX      ldc1 $f6, SC32_FPREGS+48(a0)
 258         EX      ldc1 $f8, SC32_FPREGS+64(a0)
 259         EX      ldc1 $f10, SC32_FPREGS+80(a0)
 260         EX      ldc1 $f12, SC32_FPREGS+96(a0)
 261         EX      ldc1 $f14, SC32_FPREGS+112(a0)
 262         EX      ldc1 $f16, SC32_FPREGS+128(a0)
 263         EX      ldc1 $f18, SC32_FPREGS+144(a0)
 264         EX      ldc1 $f20, SC32_FPREGS+160(a0)
 265         EX      ldc1 $f22, SC32_FPREGS+176(a0)
 266         EX      ldc1 $f24, SC32_FPREGS+192(a0)
 267         EX      ldc1 $f26, SC32_FPREGS+208(a0)
 268         EX      ldc1 $f28, SC32_FPREGS+224(a0)
 269         EX      ldc1 $f30, SC32_FPREGS+240(a0)
 270         ctc1    t1, fcr31
 271         jr      ra
 272          li     v0, 0                                   # success
 273         .set pop
 274         END(_restore_fp_context32)
 275 #endif
 276
 277         .set    reorder
 278
 279         .type   fault@function
 280         .ent    fault
 281 fault:  li      v0, -EFAULT                             # failure
 282         jr      ra
 283         .end    fault