2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
8 * SMP support for BMIPS
11 #include <linux/init.h>
12 #include <linux/sched.h>
14 #include <linux/delay.h>
15 #include <linux/smp.h>
16 #include <linux/interrupt.h>
17 #include <linux/spinlock.h>
18 #include <linux/cpu.h>
19 #include <linux/cpumask.h>
20 #include <linux/reboot.h>
22 #include <linux/compiler.h>
23 #include <linux/linkage.h>
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
28 #include <asm/pgtable.h>
29 #include <asm/processor.h>
30 #include <asm/bootinfo.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <asm/mipsregs.h>
35 #include <asm/bmips.h>
36 #include <asm/traps.h>
37 #include <asm/barrier.h>
39 static int __maybe_unused max_cpus
= 1;
41 /* these may be configured by the platform code */
42 int bmips_smp_enabled
= 1;
44 cpumask_t bmips_booted_mask
;
48 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
49 unsigned long bmips_smp_boot_sp
;
50 unsigned long bmips_smp_boot_gp
;
52 static void bmips43xx_send_ipi_single(int cpu
, unsigned int action
);
53 static void bmips5000_send_ipi_single(int cpu
, unsigned int action
);
54 static irqreturn_t
bmips43xx_ipi_interrupt(int irq
, void *dev_id
);
55 static irqreturn_t
bmips5000_ipi_interrupt(int irq
, void *dev_id
);
57 /* SW interrupts 0,1 are used for interprocessor signaling */
58 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
59 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
61 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
62 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
63 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
64 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
66 static void __init
bmips_smp_setup(void)
68 int i
, cpu
= 1, boot_cpu
= 0;
71 switch (current_cpu_type()) {
74 /* arbitration priority */
75 clear_c0_brcm_cmt_ctrl(0x30);
77 /* NBK and weak order flags */
78 set_c0_brcm_config_0(0x30000);
80 /* Find out if we are running on TP0 or TP1 */
81 boot_cpu
= !!(read_c0_brcm_cmt_local() & (1 << 31));
84 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
86 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
87 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
94 change_c0_brcm_cmt_intr(0xf8018000,
95 (cpu_hw_intr
<< 27) | (0x03 << 15));
97 /* single core, 2 threads (2 pipelines) */
102 /* enable raceless SW interrupts */
103 set_c0_brcm_config(0x03 << 22);
105 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
106 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
108 /* N cores, 2 threads per core */
109 max_cpus
= (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
111 /* clear any pending SW interrupts */
112 for (i
= 0; i
< max_cpus
; i
++) {
113 write_c0_brcm_action(ACTION_CLR_IPI(i
, 0));
114 write_c0_brcm_action(ACTION_CLR_IPI(i
, 1));
122 if (!bmips_smp_enabled
)
125 /* this can be overridden by the BSP */
126 if (!board_ebase_setup
)
127 board_ebase_setup
= &bmips_ebase_setup
;
129 __cpu_number_map
[boot_cpu
] = 0;
130 __cpu_logical_map
[0] = boot_cpu
;
132 for (i
= 0; i
< max_cpus
; i
++) {
134 __cpu_number_map
[i
] = cpu
;
135 __cpu_logical_map
[cpu
] = i
;
138 set_cpu_possible(i
, 1);
139 set_cpu_present(i
, 1);
144 * IPI IRQ setup - runs on CPU0
146 static void bmips_prepare_cpus(unsigned int max_cpus
)
148 irqreturn_t (*bmips_ipi_interrupt
)(int irq
, void *dev_id
);
150 switch (current_cpu_type()) {
153 bmips_ipi_interrupt
= bmips43xx_ipi_interrupt
;
156 bmips_ipi_interrupt
= bmips5000_ipi_interrupt
;
162 if (request_irq(IPI0_IRQ
, bmips_ipi_interrupt
, IRQF_PERCPU
,
164 panic("Can't request IPI0 interrupt");
165 if (request_irq(IPI1_IRQ
, bmips_ipi_interrupt
, IRQF_PERCPU
,
167 panic("Can't request IPI1 interrupt");
171 * Tell the hardware to boot CPUx - runs on CPU0
173 static void bmips_boot_secondary(int cpu
, struct task_struct
*idle
)
175 bmips_smp_boot_sp
= __KSTK_TOS(idle
);
176 bmips_smp_boot_gp
= (unsigned long)task_thread_info(idle
);
180 * Initial boot sequence for secondary CPU:
181 * bmips_reset_nmi_vec @ a000_0000 ->
183 * plat_wired_tlb_setup (cached function call; optional) ->
184 * start_secondary (cached jump)
186 * Warm restart sequence:
187 * play_dead WAIT loop ->
188 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
189 * eret to play_dead ->
190 * bmips_secondary_reentry ->
194 pr_info("SMP: Booting CPU%d...\n", cpu
);
196 if (cpumask_test_cpu(cpu
, &bmips_booted_mask
)) {
197 switch (current_cpu_type()) {
200 bmips43xx_send_ipi_single(cpu
, 0);
203 bmips5000_send_ipi_single(cpu
, 0);
208 switch (current_cpu_type()) {
211 /* Reset slave TP1 if booting from TP0 */
212 if (cpu_logical_map(cpu
) == 1)
213 set_c0_brcm_cmt_ctrl(0x01);
217 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu
));
220 * core N thread 0 was already booted; just
223 bmips_write_zscm_reg(0x210, 0xc0000000);
225 bmips_write_zscm_reg(0x210, 0x00);
229 cpumask_set_cpu(cpu
, &bmips_booted_mask
);
234 * Early setup - runs on secondary CPU after cache probe
236 static void bmips_init_secondary(void)
238 /* move NMI vector to kseg0, in case XKS01 is enabled */
241 unsigned long old_vec
;
242 unsigned long relo_vector
;
245 switch (current_cpu_type()) {
248 cbr
= BMIPS_GET_CBR();
250 boot_cpu
= !!(read_c0_brcm_cmt_local() & (1 << 31));
251 relo_vector
= boot_cpu
? BMIPS_RELO_VECTOR_CONTROL_0
:
252 BMIPS_RELO_VECTOR_CONTROL_1
;
254 old_vec
= __raw_readl(cbr
+ relo_vector
);
255 __raw_writel(old_vec
& ~0x20000000, cbr
+ relo_vector
);
257 clear_c0_cause(smp_processor_id() ? C_SW1
: C_SW0
);
260 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
261 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
263 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
269 * Late setup - runs on secondary CPU before entering the idle loop
271 static void bmips_smp_finish(void)
273 pr_info("SMP: CPU%d is running\n", smp_processor_id());
275 /* make sure there won't be a timer interrupt for a little while */
276 write_c0_compare(read_c0_count() + mips_hpt_frequency
/ HZ
);
279 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ1
| IE_IRQ5
| ST0_IE
);
284 * BMIPS5000 raceless IPIs
286 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
287 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
288 * IPI1 is used for SMP_CALL_FUNCTION
291 static void bmips5000_send_ipi_single(int cpu
, unsigned int action
)
293 write_c0_brcm_action(ACTION_SET_IPI(cpu
, action
== SMP_CALL_FUNCTION
));
296 static irqreturn_t
bmips5000_ipi_interrupt(int irq
, void *dev_id
)
298 int action
= irq
- IPI0_IRQ
;
300 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action
));
305 smp_call_function_interrupt();
310 static void bmips5000_send_ipi_mask(const struct cpumask
*mask
,
315 for_each_cpu(i
, mask
)
316 bmips5000_send_ipi_single(i
, action
);
320 * BMIPS43xx racey IPIs
322 * We use one inbound SW IRQ for each CPU.
324 * A spinlock must be held in order to keep CPUx from accidentally clearing
325 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
326 * same spinlock is used to protect the action masks.
329 static DEFINE_SPINLOCK(ipi_lock
);
330 static DEFINE_PER_CPU(int, ipi_action_mask
);
332 static void bmips43xx_send_ipi_single(int cpu
, unsigned int action
)
336 spin_lock_irqsave(&ipi_lock
, flags
);
337 set_c0_cause(cpu
? C_SW1
: C_SW0
);
338 per_cpu(ipi_action_mask
, cpu
) |= action
;
340 spin_unlock_irqrestore(&ipi_lock
, flags
);
343 static irqreturn_t
bmips43xx_ipi_interrupt(int irq
, void *dev_id
)
346 int action
, cpu
= irq
- IPI0_IRQ
;
348 spin_lock_irqsave(&ipi_lock
, flags
);
349 action
= __get_cpu_var(ipi_action_mask
);
350 per_cpu(ipi_action_mask
, cpu
) = 0;
351 clear_c0_cause(cpu
? C_SW1
: C_SW0
);
352 spin_unlock_irqrestore(&ipi_lock
, flags
);
354 if (action
& SMP_RESCHEDULE_YOURSELF
)
356 if (action
& SMP_CALL_FUNCTION
)
357 smp_call_function_interrupt();
362 static void bmips43xx_send_ipi_mask(const struct cpumask
*mask
,
367 for_each_cpu(i
, mask
)
368 bmips43xx_send_ipi_single(i
, action
);
371 #ifdef CONFIG_HOTPLUG_CPU
373 static int bmips_cpu_disable(void)
375 unsigned int cpu
= smp_processor_id();
380 pr_info("SMP: CPU%d is offline\n", cpu
);
382 set_cpu_online(cpu
, false);
383 cpu_clear(cpu
, cpu_callin_map
);
385 local_flush_tlb_all();
386 local_flush_icache_range(0, ~0);
391 static void bmips_cpu_die(unsigned int cpu
)
395 void __ref
play_dead(void)
399 /* flush data cache */
400 _dma_cache_wback_inv(0, ~0);
403 * Wakeup is on SW0 or SW1; disable everything else
404 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
405 * IRQ handlers; this clears ST0_IE and returns immediately.
407 clear_c0_cause(CAUSEF_IV
| C_SW0
| C_SW1
);
408 change_c0_status(IE_IRQ5
| IE_IRQ1
| IE_SW0
| IE_SW1
| ST0_IE
| ST0_BEV
,
409 IE_SW0
| IE_SW1
| ST0_IE
| ST0_BEV
);
410 irq_disable_hazard();
413 * wait for SW interrupt from bmips_boot_secondary(), then jump
414 * back to start_secondary()
416 __asm__
__volatile__(
418 " j bmips_secondary_reentry\n"
422 #endif /* CONFIG_HOTPLUG_CPU */
424 struct plat_smp_ops bmips43xx_smp_ops
= {
425 .smp_setup
= bmips_smp_setup
,
426 .prepare_cpus
= bmips_prepare_cpus
,
427 .boot_secondary
= bmips_boot_secondary
,
428 .smp_finish
= bmips_smp_finish
,
429 .init_secondary
= bmips_init_secondary
,
430 .send_ipi_single
= bmips43xx_send_ipi_single
,
431 .send_ipi_mask
= bmips43xx_send_ipi_mask
,
432 #ifdef CONFIG_HOTPLUG_CPU
433 .cpu_disable
= bmips_cpu_disable
,
434 .cpu_die
= bmips_cpu_die
,
438 struct plat_smp_ops bmips5000_smp_ops
= {
439 .smp_setup
= bmips_smp_setup
,
440 .prepare_cpus
= bmips_prepare_cpus
,
441 .boot_secondary
= bmips_boot_secondary
,
442 .smp_finish
= bmips_smp_finish
,
443 .init_secondary
= bmips_init_secondary
,
444 .send_ipi_single
= bmips5000_send_ipi_single
,
445 .send_ipi_mask
= bmips5000_send_ipi_mask
,
446 #ifdef CONFIG_HOTPLUG_CPU
447 .cpu_disable
= bmips_cpu_disable
,
448 .cpu_die
= bmips_cpu_die
,
452 #endif /* CONFIG_SMP */
454 /***********************************************************************
455 * BMIPS vector relocation
456 * This is primarily used for SMP boot, but it is applicable to some
457 * UP BMIPS systems as well.
458 ***********************************************************************/
460 static void bmips_wr_vec(unsigned long dst
, char *start
, char *end
)
462 memcpy((void *)dst
, start
, end
- start
);
463 dma_cache_wback((unsigned long)start
, end
- start
);
464 local_flush_icache_range(dst
, dst
+ (end
- start
));
465 instruction_hazard();
468 static inline void bmips_nmi_handler_setup(void)
470 bmips_wr_vec(BMIPS_NMI_RESET_VEC
, &bmips_reset_nmi_vec
,
471 &bmips_reset_nmi_vec_end
);
472 bmips_wr_vec(BMIPS_WARM_RESTART_VEC
, &bmips_smp_int_vec
,
473 &bmips_smp_int_vec_end
);
476 void bmips_ebase_setup(void)
478 unsigned long new_ebase
= ebase
;
479 void __iomem __maybe_unused
*cbr
;
481 BUG_ON(ebase
!= CKSEG0
);
483 switch (current_cpu_type()) {
486 * BMIPS4350 cannot relocate the normal vectors, but it
487 * can relocate the BEV=1 vectors. So CPU1 starts up at
488 * the relocated BEV=1, IV=0 general exception vector @
491 * set_uncached_handler() is used here because:
492 * - CPU1 will run this from uncached space
493 * - None of the cacheflush functions are set up yet
495 set_uncached_handler(BMIPS_WARM_RESTART_VEC
- CKSEG0
,
496 &bmips_smp_int_vec
, 0x80);
501 * 0x8000_0000: reset/NMI (initially in kseg1)
502 * 0x8000_0400: normal vectors
504 new_ebase
= 0x80000400;
505 cbr
= BMIPS_GET_CBR();
506 __raw_writel(0x80080800, cbr
+ BMIPS_RELO_VECTOR_CONTROL_0
);
507 __raw_writel(0xa0080800, cbr
+ BMIPS_RELO_VECTOR_CONTROL_1
);
511 * 0x8000_0000: reset/NMI (initially in kseg1)
512 * 0x8000_1000: normal vectors
514 new_ebase
= 0x80001000;
515 write_c0_brcm_bootvec(0xa0088008);
516 write_c0_ebase(new_ebase
);
518 bmips_write_zscm_reg(0xa0, 0xa008a008);
524 board_nmi_handler_setup
= &bmips_nmi_handler_setup
;
528 asmlinkage
void __weak
plat_wired_tlb_setup(void)
531 * Called when starting/restarting a secondary CPU.
532 * Kernel stacks and other important data might only be accessible
533 * once the wired entries are present.