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7b78d137259fdca7a14ea2789b4e034a026a58fb
[deliverable/linux.git] / arch / mips / kernel / traps.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25
26 #include <asm/bootinfo.h>
27 #include <asm/branch.h>
28 #include <asm/break.h>
29 #include <asm/cpu.h>
30 #include <asm/dsp.h>
31 #include <asm/fpu.h>
32 #include <asm/mipsregs.h>
33 #include <asm/mipsmtregs.h>
34 #include <asm/module.h>
35 #include <asm/pgtable.h>
36 #include <asm/ptrace.h>
37 #include <asm/sections.h>
38 #include <asm/system.h>
39 #include <asm/tlbdebug.h>
40 #include <asm/traps.h>
41 #include <asm/uaccess.h>
42 #include <asm/mmu_context.h>
43 #include <asm/types.h>
44 #include <asm/stacktrace.h>
45
46 extern asmlinkage void handle_int(void);
47 extern asmlinkage void handle_tlbm(void);
48 extern asmlinkage void handle_tlbl(void);
49 extern asmlinkage void handle_tlbs(void);
50 extern asmlinkage void handle_adel(void);
51 extern asmlinkage void handle_ades(void);
52 extern asmlinkage void handle_ibe(void);
53 extern asmlinkage void handle_dbe(void);
54 extern asmlinkage void handle_sys(void);
55 extern asmlinkage void handle_bp(void);
56 extern asmlinkage void handle_ri(void);
57 extern asmlinkage void handle_ri_rdhwr_vivt(void);
58 extern asmlinkage void handle_ri_rdhwr(void);
59 extern asmlinkage void handle_cpu(void);
60 extern asmlinkage void handle_ov(void);
61 extern asmlinkage void handle_tr(void);
62 extern asmlinkage void handle_fpe(void);
63 extern asmlinkage void handle_mdmx(void);
64 extern asmlinkage void handle_watch(void);
65 extern asmlinkage void handle_mt(void);
66 extern asmlinkage void handle_dsp(void);
67 extern asmlinkage void handle_mcheck(void);
68 extern asmlinkage void handle_reserved(void);
69
70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
71 struct mips_fpu_struct *ctx, int has_fpu);
72
73 void (*board_watchpoint_handler)(struct pt_regs *regs);
74 void (*board_be_init)(void);
75 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
76 void (*board_nmi_handler_setup)(void);
77 void (*board_ejtag_handler_setup)(void);
78 void (*board_bind_eic_interrupt)(int irq, int regset);
79
80
81 static void show_raw_backtrace(unsigned long reg29)
82 {
83 unsigned long *sp = (unsigned long *)reg29;
84 unsigned long addr;
85
86 printk("Call Trace:");
87 #ifdef CONFIG_KALLSYMS
88 printk("\n");
89 #endif
90 while (!kstack_end(sp)) {
91 addr = *sp++;
92 if (__kernel_text_address(addr))
93 print_ip_sym(addr);
94 }
95 printk("\n");
96 }
97
98 #ifdef CONFIG_KALLSYMS
99 int raw_show_trace;
100 static int __init set_raw_show_trace(char *str)
101 {
102 raw_show_trace = 1;
103 return 1;
104 }
105 __setup("raw_show_trace", set_raw_show_trace);
106 #endif
107
108 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
109 {
110 unsigned long sp = regs->regs[29];
111 unsigned long ra = regs->regs[31];
112 unsigned long pc = regs->cp0_epc;
113
114 if (raw_show_trace || !__kernel_text_address(pc)) {
115 show_raw_backtrace(sp);
116 return;
117 }
118 printk("Call Trace:\n");
119 do {
120 print_ip_sym(pc);
121 pc = unwind_stack(task, &sp, pc, &ra);
122 } while (pc);
123 printk("\n");
124 }
125
126 /*
127 * This routine abuses get_user()/put_user() to reference pointers
128 * with at least a bit of error checking ...
129 */
130 static void show_stacktrace(struct task_struct *task,
131 const struct pt_regs *regs)
132 {
133 const int field = 2 * sizeof(unsigned long);
134 long stackdata;
135 int i;
136 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
137
138 printk("Stack :");
139 i = 0;
140 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
141 if (i && ((i % (64 / field)) == 0))
142 printk("\n ");
143 if (i > 39) {
144 printk(" ...");
145 break;
146 }
147
148 if (__get_user(stackdata, sp++)) {
149 printk(" (Bad stack address)");
150 break;
151 }
152
153 printk(" %0*lx", field, stackdata);
154 i++;
155 }
156 printk("\n");
157 show_backtrace(task, regs);
158 }
159
160 void show_stack(struct task_struct *task, unsigned long *sp)
161 {
162 struct pt_regs regs;
163 if (sp) {
164 regs.regs[29] = (unsigned long)sp;
165 regs.regs[31] = 0;
166 regs.cp0_epc = 0;
167 } else {
168 if (task && task != current) {
169 regs.regs[29] = task->thread.reg29;
170 regs.regs[31] = 0;
171 regs.cp0_epc = task->thread.reg31;
172 } else {
173 prepare_frametrace(&regs);
174 }
175 }
176 show_stacktrace(task, &regs);
177 }
178
179 /*
180 * The architecture-independent dump_stack generator
181 */
182 void dump_stack(void)
183 {
184 struct pt_regs regs;
185
186 prepare_frametrace(&regs);
187 show_backtrace(current, &regs);
188 }
189
190 EXPORT_SYMBOL(dump_stack);
191
192 static void show_code(unsigned int __user *pc)
193 {
194 long i;
195
196 printk("\nCode:");
197
198 for(i = -3 ; i < 6 ; i++) {
199 unsigned int insn;
200 if (__get_user(insn, pc + i)) {
201 printk(" (Bad address in epc)\n");
202 break;
203 }
204 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
205 }
206 }
207
208 static void __show_regs(const struct pt_regs *regs)
209 {
210 const int field = 2 * sizeof(unsigned long);
211 unsigned int cause = regs->cp0_cause;
212 int i;
213
214 printk("Cpu %d\n", smp_processor_id());
215
216 /*
217 * Saved main processor registers
218 */
219 for (i = 0; i < 32; ) {
220 if ((i % 4) == 0)
221 printk("$%2d :", i);
222 if (i == 0)
223 printk(" %0*lx", field, 0UL);
224 else if (i == 26 || i == 27)
225 printk(" %*s", field, "");
226 else
227 printk(" %0*lx", field, regs->regs[i]);
228
229 i++;
230 if ((i % 4) == 0)
231 printk("\n");
232 }
233
234 #ifdef CONFIG_CPU_HAS_SMARTMIPS
235 printk("Acx : %0*lx\n", field, regs->acx);
236 #endif
237 printk("Hi : %0*lx\n", field, regs->hi);
238 printk("Lo : %0*lx\n", field, regs->lo);
239
240 /*
241 * Saved cp0 registers
242 */
243 printk("epc : %0*lx ", field, regs->cp0_epc);
244 print_symbol("%s ", regs->cp0_epc);
245 printk(" %s\n", print_tainted());
246 printk("ra : %0*lx ", field, regs->regs[31]);
247 print_symbol("%s\n", regs->regs[31]);
248
249 printk("Status: %08x ", (uint32_t) regs->cp0_status);
250
251 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
252 if (regs->cp0_status & ST0_KUO)
253 printk("KUo ");
254 if (regs->cp0_status & ST0_IEO)
255 printk("IEo ");
256 if (regs->cp0_status & ST0_KUP)
257 printk("KUp ");
258 if (regs->cp0_status & ST0_IEP)
259 printk("IEp ");
260 if (regs->cp0_status & ST0_KUC)
261 printk("KUc ");
262 if (regs->cp0_status & ST0_IEC)
263 printk("IEc ");
264 } else {
265 if (regs->cp0_status & ST0_KX)
266 printk("KX ");
267 if (regs->cp0_status & ST0_SX)
268 printk("SX ");
269 if (regs->cp0_status & ST0_UX)
270 printk("UX ");
271 switch (regs->cp0_status & ST0_KSU) {
272 case KSU_USER:
273 printk("USER ");
274 break;
275 case KSU_SUPERVISOR:
276 printk("SUPERVISOR ");
277 break;
278 case KSU_KERNEL:
279 printk("KERNEL ");
280 break;
281 default:
282 printk("BAD_MODE ");
283 break;
284 }
285 if (regs->cp0_status & ST0_ERL)
286 printk("ERL ");
287 if (regs->cp0_status & ST0_EXL)
288 printk("EXL ");
289 if (regs->cp0_status & ST0_IE)
290 printk("IE ");
291 }
292 printk("\n");
293
294 printk("Cause : %08x\n", cause);
295
296 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
297 if (1 <= cause && cause <= 5)
298 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
299
300 printk("PrId : %08x (%s)\n", read_c0_prid(),
301 cpu_name_string());
302 }
303
304 /*
305 * FIXME: really the generic show_regs should take a const pointer argument.
306 */
307 void show_regs(struct pt_regs *regs)
308 {
309 __show_regs((struct pt_regs *)regs);
310 }
311
312 void show_registers(const struct pt_regs *regs)
313 {
314 __show_regs(regs);
315 print_modules();
316 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
317 current->comm, current->pid, current_thread_info(), current);
318 show_stacktrace(current, regs);
319 show_code((unsigned int __user *) regs->cp0_epc);
320 printk("\n");
321 }
322
323 static DEFINE_SPINLOCK(die_lock);
324
325 void __noreturn die(const char * str, const struct pt_regs * regs)
326 {
327 static int die_counter;
328 #ifdef CONFIG_MIPS_MT_SMTC
329 unsigned long dvpret = dvpe();
330 #endif /* CONFIG_MIPS_MT_SMTC */
331
332 console_verbose();
333 spin_lock_irq(&die_lock);
334 bust_spinlocks(1);
335 #ifdef CONFIG_MIPS_MT_SMTC
336 mips_mt_regdump(dvpret);
337 #endif /* CONFIG_MIPS_MT_SMTC */
338 printk("%s[#%d]:\n", str, ++die_counter);
339 show_registers(regs);
340 add_taint(TAINT_DIE);
341 spin_unlock_irq(&die_lock);
342
343 if (in_interrupt())
344 panic("Fatal exception in interrupt");
345
346 if (panic_on_oops) {
347 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
348 ssleep(5);
349 panic("Fatal exception");
350 }
351
352 do_exit(SIGSEGV);
353 }
354
355 extern const struct exception_table_entry __start___dbe_table[];
356 extern const struct exception_table_entry __stop___dbe_table[];
357
358 __asm__(
359 " .section __dbe_table, \"a\"\n"
360 " .previous \n");
361
362 /* Given an address, look for it in the exception tables. */
363 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
364 {
365 const struct exception_table_entry *e;
366
367 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
368 if (!e)
369 e = search_module_dbetables(addr);
370 return e;
371 }
372
373 asmlinkage void do_be(struct pt_regs *regs)
374 {
375 const int field = 2 * sizeof(unsigned long);
376 const struct exception_table_entry *fixup = NULL;
377 int data = regs->cp0_cause & 4;
378 int action = MIPS_BE_FATAL;
379
380 /* XXX For now. Fixme, this searches the wrong table ... */
381 if (data && !user_mode(regs))
382 fixup = search_dbe_tables(exception_epc(regs));
383
384 if (fixup)
385 action = MIPS_BE_FIXUP;
386
387 if (board_be_handler)
388 action = board_be_handler(regs, fixup != NULL);
389
390 switch (action) {
391 case MIPS_BE_DISCARD:
392 return;
393 case MIPS_BE_FIXUP:
394 if (fixup) {
395 regs->cp0_epc = fixup->nextinsn;
396 return;
397 }
398 break;
399 default:
400 break;
401 }
402
403 /*
404 * Assume it would be too dangerous to continue ...
405 */
406 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
407 data ? "Data" : "Instruction",
408 field, regs->cp0_epc, field, regs->regs[31]);
409 die_if_kernel("Oops", regs);
410 force_sig(SIGBUS, current);
411 }
412
413 /*
414 * ll/sc, rdhwr, sync emulation
415 */
416
417 #define OPCODE 0xfc000000
418 #define BASE 0x03e00000
419 #define RT 0x001f0000
420 #define OFFSET 0x0000ffff
421 #define LL 0xc0000000
422 #define SC 0xe0000000
423 #define SPEC0 0x00000000
424 #define SPEC3 0x7c000000
425 #define RD 0x0000f800
426 #define FUNC 0x0000003f
427 #define SYNC 0x0000000f
428 #define RDHWR 0x0000003b
429
430 /*
431 * The ll_bit is cleared by r*_switch.S
432 */
433
434 unsigned long ll_bit;
435
436 static struct task_struct *ll_task = NULL;
437
438 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
439 {
440 unsigned long value, __user *vaddr;
441 long offset;
442
443 /*
444 * analyse the ll instruction that just caused a ri exception
445 * and put the referenced address to addr.
446 */
447
448 /* sign extend offset */
449 offset = opcode & OFFSET;
450 offset <<= 16;
451 offset >>= 16;
452
453 vaddr = (unsigned long __user *)
454 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
455
456 if ((unsigned long)vaddr & 3)
457 return SIGBUS;
458 if (get_user(value, vaddr))
459 return SIGSEGV;
460
461 preempt_disable();
462
463 if (ll_task == NULL || ll_task == current) {
464 ll_bit = 1;
465 } else {
466 ll_bit = 0;
467 }
468 ll_task = current;
469
470 preempt_enable();
471
472 regs->regs[(opcode & RT) >> 16] = value;
473
474 return 0;
475 }
476
477 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
478 {
479 unsigned long __user *vaddr;
480 unsigned long reg;
481 long offset;
482
483 /*
484 * analyse the sc instruction that just caused a ri exception
485 * and put the referenced address to addr.
486 */
487
488 /* sign extend offset */
489 offset = opcode & OFFSET;
490 offset <<= 16;
491 offset >>= 16;
492
493 vaddr = (unsigned long __user *)
494 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
495 reg = (opcode & RT) >> 16;
496
497 if ((unsigned long)vaddr & 3)
498 return SIGBUS;
499
500 preempt_disable();
501
502 if (ll_bit == 0 || ll_task != current) {
503 regs->regs[reg] = 0;
504 preempt_enable();
505 return 0;
506 }
507
508 preempt_enable();
509
510 if (put_user(regs->regs[reg], vaddr))
511 return SIGSEGV;
512
513 regs->regs[reg] = 1;
514
515 return 0;
516 }
517
518 /*
519 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
520 * opcodes are supposed to result in coprocessor unusable exceptions if
521 * executed on ll/sc-less processors. That's the theory. In practice a
522 * few processors such as NEC's VR4100 throw reserved instruction exceptions
523 * instead, so we're doing the emulation thing in both exception handlers.
524 */
525 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
526 {
527 if ((opcode & OPCODE) == LL)
528 return simulate_ll(regs, opcode);
529 if ((opcode & OPCODE) == SC)
530 return simulate_sc(regs, opcode);
531
532 return -1; /* Must be something else ... */
533 }
534
535 /*
536 * Simulate trapping 'rdhwr' instructions to provide user accessible
537 * registers not implemented in hardware. The only current use of this
538 * is the thread area pointer.
539 */
540 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
541 {
542 struct thread_info *ti = task_thread_info(current);
543
544 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
545 int rd = (opcode & RD) >> 11;
546 int rt = (opcode & RT) >> 16;
547 switch (rd) {
548 case 29:
549 regs->regs[rt] = ti->tp_value;
550 return 0;
551 default:
552 return -1;
553 }
554 }
555
556 /* Not ours. */
557 return -1;
558 }
559
560 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
561 {
562 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
563 return 0;
564
565 return -1; /* Must be something else ... */
566 }
567
568 asmlinkage void do_ov(struct pt_regs *regs)
569 {
570 siginfo_t info;
571
572 die_if_kernel("Integer overflow", regs);
573
574 info.si_code = FPE_INTOVF;
575 info.si_signo = SIGFPE;
576 info.si_errno = 0;
577 info.si_addr = (void __user *) regs->cp0_epc;
578 force_sig_info(SIGFPE, &info, current);
579 }
580
581 /*
582 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
583 */
584 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
585 {
586 siginfo_t info;
587
588 die_if_kernel("FP exception in kernel code", regs);
589
590 if (fcr31 & FPU_CSR_UNI_X) {
591 int sig;
592
593 /*
594 * Unimplemented operation exception. If we've got the full
595 * software emulator on-board, let's use it...
596 *
597 * Force FPU to dump state into task/thread context. We're
598 * moving a lot of data here for what is probably a single
599 * instruction, but the alternative is to pre-decode the FP
600 * register operands before invoking the emulator, which seems
601 * a bit extreme for what should be an infrequent event.
602 */
603 /* Ensure 'resume' not overwrite saved fp context again. */
604 lose_fpu(1);
605
606 /* Run the emulator */
607 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
608
609 /*
610 * We can't allow the emulated instruction to leave any of
611 * the cause bit set in $fcr31.
612 */
613 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
614
615 /* Restore the hardware register state */
616 own_fpu(1); /* Using the FPU again. */
617
618 /* If something went wrong, signal */
619 if (sig)
620 force_sig(sig, current);
621
622 return;
623 } else if (fcr31 & FPU_CSR_INV_X)
624 info.si_code = FPE_FLTINV;
625 else if (fcr31 & FPU_CSR_DIV_X)
626 info.si_code = FPE_FLTDIV;
627 else if (fcr31 & FPU_CSR_OVF_X)
628 info.si_code = FPE_FLTOVF;
629 else if (fcr31 & FPU_CSR_UDF_X)
630 info.si_code = FPE_FLTUND;
631 else if (fcr31 & FPU_CSR_INE_X)
632 info.si_code = FPE_FLTRES;
633 else
634 info.si_code = __SI_FAULT;
635 info.si_signo = SIGFPE;
636 info.si_errno = 0;
637 info.si_addr = (void __user *) regs->cp0_epc;
638 force_sig_info(SIGFPE, &info, current);
639 }
640
641 asmlinkage void do_bp(struct pt_regs *regs)
642 {
643 unsigned int opcode, bcode;
644 siginfo_t info;
645
646 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
647 goto out_sigsegv;
648
649 /*
650 * There is the ancient bug in the MIPS assemblers that the break
651 * code starts left to bit 16 instead to bit 6 in the opcode.
652 * Gas is bug-compatible, but not always, grrr...
653 * We handle both cases with a simple heuristics. --macro
654 */
655 bcode = ((opcode >> 6) & ((1 << 20) - 1));
656 if (bcode < (1 << 10))
657 bcode <<= 10;
658
659 /*
660 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
661 * insns, even for break codes that indicate arithmetic failures.
662 * Weird ...)
663 * But should we continue the brokenness??? --macro
664 */
665 switch (bcode) {
666 case BRK_OVERFLOW << 10:
667 case BRK_DIVZERO << 10:
668 die_if_kernel("Break instruction in kernel code", regs);
669 if (bcode == (BRK_DIVZERO << 10))
670 info.si_code = FPE_INTDIV;
671 else
672 info.si_code = FPE_INTOVF;
673 info.si_signo = SIGFPE;
674 info.si_errno = 0;
675 info.si_addr = (void __user *) regs->cp0_epc;
676 force_sig_info(SIGFPE, &info, current);
677 break;
678 case BRK_BUG:
679 die("Kernel bug detected", regs);
680 break;
681 default:
682 die_if_kernel("Break instruction in kernel code", regs);
683 force_sig(SIGTRAP, current);
684 }
685 return;
686
687 out_sigsegv:
688 force_sig(SIGSEGV, current);
689 }
690
691 asmlinkage void do_tr(struct pt_regs *regs)
692 {
693 unsigned int opcode, tcode = 0;
694 siginfo_t info;
695
696 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
697 goto out_sigsegv;
698
699 /* Immediate versions don't provide a code. */
700 if (!(opcode & OPCODE))
701 tcode = ((opcode >> 6) & ((1 << 10) - 1));
702
703 /*
704 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
705 * insns, even for trap codes that indicate arithmetic failures.
706 * Weird ...)
707 * But should we continue the brokenness??? --macro
708 */
709 switch (tcode) {
710 case BRK_OVERFLOW:
711 case BRK_DIVZERO:
712 die_if_kernel("Trap instruction in kernel code", regs);
713 if (tcode == BRK_DIVZERO)
714 info.si_code = FPE_INTDIV;
715 else
716 info.si_code = FPE_INTOVF;
717 info.si_signo = SIGFPE;
718 info.si_errno = 0;
719 info.si_addr = (void __user *) regs->cp0_epc;
720 force_sig_info(SIGFPE, &info, current);
721 break;
722 case BRK_BUG:
723 die("Kernel bug detected", regs);
724 break;
725 default:
726 die_if_kernel("Trap instruction in kernel code", regs);
727 force_sig(SIGTRAP, current);
728 }
729 return;
730
731 out_sigsegv:
732 force_sig(SIGSEGV, current);
733 }
734
735 asmlinkage void do_ri(struct pt_regs *regs)
736 {
737 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
738 unsigned long old_epc = regs->cp0_epc;
739 unsigned int opcode = 0;
740 int status = -1;
741
742 die_if_kernel("Reserved instruction in kernel code", regs);
743
744 if (unlikely(compute_return_epc(regs) < 0))
745 return;
746
747 if (unlikely(get_user(opcode, epc) < 0))
748 status = SIGSEGV;
749
750 if (!cpu_has_llsc && status < 0)
751 status = simulate_llsc(regs, opcode);
752
753 if (status < 0)
754 status = simulate_rdhwr(regs, opcode);
755
756 if (status < 0)
757 status = simulate_sync(regs, opcode);
758
759 if (status < 0)
760 status = SIGILL;
761
762 if (unlikely(status > 0)) {
763 regs->cp0_epc = old_epc; /* Undo skip-over. */
764 force_sig(status, current);
765 }
766 }
767
768 /*
769 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
770 * emulated more than some threshold number of instructions, force migration to
771 * a "CPU" that has FP support.
772 */
773 static void mt_ase_fp_affinity(void)
774 {
775 #ifdef CONFIG_MIPS_MT_FPAFF
776 if (mt_fpemul_threshold > 0 &&
777 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
778 /*
779 * If there's no FPU present, or if the application has already
780 * restricted the allowed set to exclude any CPUs with FPUs,
781 * we'll skip the procedure.
782 */
783 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
784 cpumask_t tmask;
785
786 cpus_and(tmask, current->thread.user_cpus_allowed,
787 mt_fpu_cpumask);
788 set_cpus_allowed(current, tmask);
789 set_thread_flag(TIF_FPUBOUND);
790 }
791 }
792 #endif /* CONFIG_MIPS_MT_FPAFF */
793 }
794
795 asmlinkage void do_cpu(struct pt_regs *regs)
796 {
797 unsigned int __user *epc;
798 unsigned long old_epc;
799 unsigned int opcode;
800 unsigned int cpid;
801 int status;
802
803 die_if_kernel("do_cpu invoked from kernel context!", regs);
804
805 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
806
807 switch (cpid) {
808 case 0:
809 epc = (unsigned int __user *)exception_epc(regs);
810 old_epc = regs->cp0_epc;
811 opcode = 0;
812 status = -1;
813
814 if (unlikely(compute_return_epc(regs) < 0))
815 return;
816
817 if (unlikely(get_user(opcode, epc) < 0))
818 status = SIGSEGV;
819
820 if (!cpu_has_llsc && status < 0)
821 status = simulate_llsc(regs, opcode);
822
823 if (status < 0)
824 status = simulate_rdhwr(regs, opcode);
825
826 if (status < 0)
827 status = SIGILL;
828
829 if (unlikely(status > 0)) {
830 regs->cp0_epc = old_epc; /* Undo skip-over. */
831 force_sig(status, current);
832 }
833
834 return;
835
836 case 1:
837 if (used_math()) /* Using the FPU again. */
838 own_fpu(1);
839 else { /* First time FPU user. */
840 init_fpu();
841 set_used_math();
842 }
843
844 if (!raw_cpu_has_fpu) {
845 int sig;
846 sig = fpu_emulator_cop1Handler(regs,
847 &current->thread.fpu, 0);
848 if (sig)
849 force_sig(sig, current);
850 else
851 mt_ase_fp_affinity();
852 }
853
854 return;
855
856 case 2:
857 case 3:
858 break;
859 }
860
861 force_sig(SIGILL, current);
862 }
863
864 asmlinkage void do_mdmx(struct pt_regs *regs)
865 {
866 force_sig(SIGILL, current);
867 }
868
869 asmlinkage void do_watch(struct pt_regs *regs)
870 {
871 if (board_watchpoint_handler) {
872 (*board_watchpoint_handler)(regs);
873 return;
874 }
875
876 /*
877 * We use the watch exception where available to detect stack
878 * overflows.
879 */
880 dump_tlb_all();
881 show_regs(regs);
882 panic("Caught WATCH exception - probably caused by stack overflow.");
883 }
884
885 asmlinkage void do_mcheck(struct pt_regs *regs)
886 {
887 const int field = 2 * sizeof(unsigned long);
888 int multi_match = regs->cp0_status & ST0_TS;
889
890 show_regs(regs);
891
892 if (multi_match) {
893 printk("Index : %0x\n", read_c0_index());
894 printk("Pagemask: %0x\n", read_c0_pagemask());
895 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
896 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
897 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
898 printk("\n");
899 dump_tlb_all();
900 }
901
902 show_code((unsigned int __user *) regs->cp0_epc);
903
904 /*
905 * Some chips may have other causes of machine check (e.g. SB1
906 * graduation timer)
907 */
908 panic("Caught Machine Check exception - %scaused by multiple "
909 "matching entries in the TLB.",
910 (multi_match) ? "" : "not ");
911 }
912
913 asmlinkage void do_mt(struct pt_regs *regs)
914 {
915 int subcode;
916
917 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
918 >> VPECONTROL_EXCPT_SHIFT;
919 switch (subcode) {
920 case 0:
921 printk(KERN_DEBUG "Thread Underflow\n");
922 break;
923 case 1:
924 printk(KERN_DEBUG "Thread Overflow\n");
925 break;
926 case 2:
927 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
928 break;
929 case 3:
930 printk(KERN_DEBUG "Gating Storage Exception\n");
931 break;
932 case 4:
933 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
934 break;
935 case 5:
936 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
937 break;
938 default:
939 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
940 subcode);
941 break;
942 }
943 die_if_kernel("MIPS MT Thread exception in kernel", regs);
944
945 force_sig(SIGILL, current);
946 }
947
948
949 asmlinkage void do_dsp(struct pt_regs *regs)
950 {
951 if (cpu_has_dsp)
952 panic("Unexpected DSP exception\n");
953
954 force_sig(SIGILL, current);
955 }
956
957 asmlinkage void do_reserved(struct pt_regs *regs)
958 {
959 /*
960 * Game over - no way to handle this if it ever occurs. Most probably
961 * caused by a new unknown cpu type or after another deadly
962 * hard/software error.
963 */
964 show_regs(regs);
965 panic("Caught reserved exception %ld - should not happen.",
966 (regs->cp0_cause & 0x7f) >> 2);
967 }
968
969 /*
970 * Some MIPS CPUs can enable/disable for cache parity detection, but do
971 * it different ways.
972 */
973 static inline void parity_protection_init(void)
974 {
975 switch (current_cpu_type()) {
976 case CPU_24K:
977 case CPU_34K:
978 case CPU_5KC:
979 write_c0_ecc(0x80000000);
980 back_to_back_c0_hazard();
981 /* Set the PE bit (bit 31) in the c0_errctl register. */
982 printk(KERN_INFO "Cache parity protection %sabled\n",
983 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
984 break;
985 case CPU_20KC:
986 case CPU_25KF:
987 /* Clear the DE bit (bit 16) in the c0_status register. */
988 printk(KERN_INFO "Enable cache parity protection for "
989 "MIPS 20KC/25KF CPUs.\n");
990 clear_c0_status(ST0_DE);
991 break;
992 default:
993 break;
994 }
995 }
996
997 asmlinkage void cache_parity_error(void)
998 {
999 const int field = 2 * sizeof(unsigned long);
1000 unsigned int reg_val;
1001
1002 /* For the moment, report the problem and hang. */
1003 printk("Cache error exception:\n");
1004 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1005 reg_val = read_c0_cacheerr();
1006 printk("c0_cacheerr == %08x\n", reg_val);
1007
1008 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1009 reg_val & (1<<30) ? "secondary" : "primary",
1010 reg_val & (1<<31) ? "data" : "insn");
1011 printk("Error bits: %s%s%s%s%s%s%s\n",
1012 reg_val & (1<<29) ? "ED " : "",
1013 reg_val & (1<<28) ? "ET " : "",
1014 reg_val & (1<<26) ? "EE " : "",
1015 reg_val & (1<<25) ? "EB " : "",
1016 reg_val & (1<<24) ? "EI " : "",
1017 reg_val & (1<<23) ? "E1 " : "",
1018 reg_val & (1<<22) ? "E0 " : "");
1019 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1020
1021 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1022 if (reg_val & (1<<22))
1023 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1024
1025 if (reg_val & (1<<23))
1026 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1027 #endif
1028
1029 panic("Can't handle the cache error!");
1030 }
1031
1032 /*
1033 * SDBBP EJTAG debug exception handler.
1034 * We skip the instruction and return to the next instruction.
1035 */
1036 void ejtag_exception_handler(struct pt_regs *regs)
1037 {
1038 const int field = 2 * sizeof(unsigned long);
1039 unsigned long depc, old_epc;
1040 unsigned int debug;
1041
1042 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1043 depc = read_c0_depc();
1044 debug = read_c0_debug();
1045 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1046 if (debug & 0x80000000) {
1047 /*
1048 * In branch delay slot.
1049 * We cheat a little bit here and use EPC to calculate the
1050 * debug return address (DEPC). EPC is restored after the
1051 * calculation.
1052 */
1053 old_epc = regs->cp0_epc;
1054 regs->cp0_epc = depc;
1055 __compute_return_epc(regs);
1056 depc = regs->cp0_epc;
1057 regs->cp0_epc = old_epc;
1058 } else
1059 depc += 4;
1060 write_c0_depc(depc);
1061
1062 #if 0
1063 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1064 write_c0_debug(debug | 0x100);
1065 #endif
1066 }
1067
1068 /*
1069 * NMI exception handler.
1070 */
1071 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1072 {
1073 bust_spinlocks(1);
1074 printk("NMI taken!!!!\n");
1075 die("NMI", regs);
1076 }
1077
1078 #define VECTORSPACING 0x100 /* for EI/VI mode */
1079
1080 unsigned long ebase;
1081 unsigned long exception_handlers[32];
1082 unsigned long vi_handlers[64];
1083
1084 /*
1085 * As a side effect of the way this is implemented we're limited
1086 * to interrupt handlers in the address range from
1087 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1088 */
1089 void *set_except_vector(int n, void *addr)
1090 {
1091 unsigned long handler = (unsigned long) addr;
1092 unsigned long old_handler = exception_handlers[n];
1093
1094 exception_handlers[n] = handler;
1095 if (n == 0 && cpu_has_divec) {
1096 *(u32 *)(ebase + 0x200) = 0x08000000 |
1097 (0x03ffffff & (handler >> 2));
1098 flush_icache_range(ebase + 0x200, ebase + 0x204);
1099 }
1100 return (void *)old_handler;
1101 }
1102
1103 #ifdef CONFIG_CPU_MIPSR2_SRS
1104 /*
1105 * MIPSR2 shadow register set allocation
1106 * FIXME: SMP...
1107 */
1108
1109 static struct shadow_registers {
1110 /*
1111 * Number of shadow register sets supported
1112 */
1113 unsigned long sr_supported;
1114 /*
1115 * Bitmap of allocated shadow registers
1116 */
1117 unsigned long sr_allocated;
1118 } shadow_registers;
1119
1120 static void mips_srs_init(void)
1121 {
1122 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1123 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1124 shadow_registers.sr_supported);
1125 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1126 }
1127
1128 int mips_srs_max(void)
1129 {
1130 return shadow_registers.sr_supported;
1131 }
1132
1133 int mips_srs_alloc(void)
1134 {
1135 struct shadow_registers *sr = &shadow_registers;
1136 int set;
1137
1138 again:
1139 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1140 if (set >= sr->sr_supported)
1141 return -1;
1142
1143 if (test_and_set_bit(set, &sr->sr_allocated))
1144 goto again;
1145
1146 return set;
1147 }
1148
1149 void mips_srs_free(int set)
1150 {
1151 struct shadow_registers *sr = &shadow_registers;
1152
1153 clear_bit(set, &sr->sr_allocated);
1154 }
1155
1156 static asmlinkage void do_default_vi(void)
1157 {
1158 show_regs(get_irq_regs());
1159 panic("Caught unexpected vectored interrupt.");
1160 }
1161
1162 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1163 {
1164 unsigned long handler;
1165 unsigned long old_handler = vi_handlers[n];
1166 u32 *w;
1167 unsigned char *b;
1168
1169 if (!cpu_has_veic && !cpu_has_vint)
1170 BUG();
1171
1172 if (addr == NULL) {
1173 handler = (unsigned long) do_default_vi;
1174 srs = 0;
1175 } else
1176 handler = (unsigned long) addr;
1177 vi_handlers[n] = (unsigned long) addr;
1178
1179 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1180
1181 if (srs >= mips_srs_max())
1182 panic("Shadow register set %d not supported", srs);
1183
1184 if (cpu_has_veic) {
1185 if (board_bind_eic_interrupt)
1186 board_bind_eic_interrupt(n, srs);
1187 } else if (cpu_has_vint) {
1188 /* SRSMap is only defined if shadow sets are implemented */
1189 if (mips_srs_max() > 1)
1190 change_c0_srsmap(0xf << n*4, srs << n*4);
1191 }
1192
1193 if (srs == 0) {
1194 /*
1195 * If no shadow set is selected then use the default handler
1196 * that does normal register saving and a standard interrupt exit
1197 */
1198
1199 extern char except_vec_vi, except_vec_vi_lui;
1200 extern char except_vec_vi_ori, except_vec_vi_end;
1201 #ifdef CONFIG_MIPS_MT_SMTC
1202 /*
1203 * We need to provide the SMTC vectored interrupt handler
1204 * not only with the address of the handler, but with the
1205 * Status.IM bit to be masked before going there.
1206 */
1207 extern char except_vec_vi_mori;
1208 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1209 #endif /* CONFIG_MIPS_MT_SMTC */
1210 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1211 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1212 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1213
1214 if (handler_len > VECTORSPACING) {
1215 /*
1216 * Sigh... panicing won't help as the console
1217 * is probably not configured :(
1218 */
1219 panic("VECTORSPACING too small");
1220 }
1221
1222 memcpy(b, &except_vec_vi, handler_len);
1223 #ifdef CONFIG_MIPS_MT_SMTC
1224 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1225
1226 w = (u32 *)(b + mori_offset);
1227 *w = (*w & 0xffff0000) | (0x100 << n);
1228 #endif /* CONFIG_MIPS_MT_SMTC */
1229 w = (u32 *)(b + lui_offset);
1230 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1231 w = (u32 *)(b + ori_offset);
1232 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1233 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1234 }
1235 else {
1236 /*
1237 * In other cases jump directly to the interrupt handler
1238 *
1239 * It is the handlers responsibility to save registers if required
1240 * (eg hi/lo) and return from the exception using "eret"
1241 */
1242 w = (u32 *)b;
1243 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1244 *w = 0;
1245 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1246 }
1247
1248 return (void *)old_handler;
1249 }
1250
1251 void *set_vi_handler(int n, vi_handler_t addr)
1252 {
1253 return set_vi_srs_handler(n, addr, 0);
1254 }
1255
1256 #else
1257
1258 static inline void mips_srs_init(void)
1259 {
1260 }
1261
1262 #endif /* CONFIG_CPU_MIPSR2_SRS */
1263
1264 /*
1265 * This is used by native signal handling
1266 */
1267 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1268 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1269
1270 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1271 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1272
1273 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1274 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1275
1276 #ifdef CONFIG_SMP
1277 static int smp_save_fp_context(struct sigcontext __user *sc)
1278 {
1279 return raw_cpu_has_fpu
1280 ? _save_fp_context(sc)
1281 : fpu_emulator_save_context(sc);
1282 }
1283
1284 static int smp_restore_fp_context(struct sigcontext __user *sc)
1285 {
1286 return raw_cpu_has_fpu
1287 ? _restore_fp_context(sc)
1288 : fpu_emulator_restore_context(sc);
1289 }
1290 #endif
1291
1292 static inline void signal_init(void)
1293 {
1294 #ifdef CONFIG_SMP
1295 /* For now just do the cpu_has_fpu check when the functions are invoked */
1296 save_fp_context = smp_save_fp_context;
1297 restore_fp_context = smp_restore_fp_context;
1298 #else
1299 if (cpu_has_fpu) {
1300 save_fp_context = _save_fp_context;
1301 restore_fp_context = _restore_fp_context;
1302 } else {
1303 save_fp_context = fpu_emulator_save_context;
1304 restore_fp_context = fpu_emulator_restore_context;
1305 }
1306 #endif
1307 }
1308
1309 #ifdef CONFIG_MIPS32_COMPAT
1310
1311 /*
1312 * This is used by 32-bit signal stuff on the 64-bit kernel
1313 */
1314 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1315 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1316
1317 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1318 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1319
1320 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1321 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1322
1323 static inline void signal32_init(void)
1324 {
1325 if (cpu_has_fpu) {
1326 save_fp_context32 = _save_fp_context32;
1327 restore_fp_context32 = _restore_fp_context32;
1328 } else {
1329 save_fp_context32 = fpu_emulator_save_context32;
1330 restore_fp_context32 = fpu_emulator_restore_context32;
1331 }
1332 }
1333 #endif
1334
1335 extern void cpu_cache_init(void);
1336 extern void tlb_init(void);
1337 extern void flush_tlb_handlers(void);
1338
1339 /*
1340 * Timer interrupt
1341 */
1342 int cp0_compare_irq;
1343
1344 /*
1345 * Performance counter IRQ or -1 if shared with timer
1346 */
1347 int cp0_perfcount_irq;
1348 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1349
1350 void __init per_cpu_trap_init(void)
1351 {
1352 unsigned int cpu = smp_processor_id();
1353 unsigned int status_set = ST0_CU0;
1354 #ifdef CONFIG_MIPS_MT_SMTC
1355 int secondaryTC = 0;
1356 int bootTC = (cpu == 0);
1357
1358 /*
1359 * Only do per_cpu_trap_init() for first TC of Each VPE.
1360 * Note that this hack assumes that the SMTC init code
1361 * assigns TCs consecutively and in ascending order.
1362 */
1363
1364 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1365 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1366 secondaryTC = 1;
1367 #endif /* CONFIG_MIPS_MT_SMTC */
1368
1369 /*
1370 * Disable coprocessors and select 32-bit or 64-bit addressing
1371 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1372 * flag that some firmware may have left set and the TS bit (for
1373 * IP27). Set XX for ISA IV code to work.
1374 */
1375 #ifdef CONFIG_64BIT
1376 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1377 #endif
1378 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1379 status_set |= ST0_XX;
1380 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1381 status_set);
1382
1383 if (cpu_has_dsp)
1384 set_c0_status(ST0_MX);
1385
1386 #ifdef CONFIG_CPU_MIPSR2
1387 if (cpu_has_mips_r2) {
1388 unsigned int enable = 0x0000000f;
1389
1390 if (cpu_has_userlocal)
1391 enable |= (1 << 29);
1392
1393 write_c0_hwrena(enable);
1394 }
1395 #endif
1396
1397 #ifdef CONFIG_MIPS_MT_SMTC
1398 if (!secondaryTC) {
1399 #endif /* CONFIG_MIPS_MT_SMTC */
1400
1401 if (cpu_has_veic || cpu_has_vint) {
1402 write_c0_ebase(ebase);
1403 /* Setting vector spacing enables EI/VI mode */
1404 change_c0_intctl(0x3e0, VECTORSPACING);
1405 }
1406 if (cpu_has_divec) {
1407 if (cpu_has_mipsmt) {
1408 unsigned int vpflags = dvpe();
1409 set_c0_cause(CAUSEF_IV);
1410 evpe(vpflags);
1411 } else
1412 set_c0_cause(CAUSEF_IV);
1413 }
1414
1415 /*
1416 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1417 *
1418 * o read IntCtl.IPTI to determine the timer interrupt
1419 * o read IntCtl.IPPCI to determine the performance counter interrupt
1420 */
1421 if (cpu_has_mips_r2) {
1422 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1423 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1424 if (cp0_perfcount_irq == cp0_compare_irq)
1425 cp0_perfcount_irq = -1;
1426 } else {
1427 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1428 cp0_perfcount_irq = -1;
1429 }
1430
1431 #ifdef CONFIG_MIPS_MT_SMTC
1432 }
1433 #endif /* CONFIG_MIPS_MT_SMTC */
1434
1435 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1436 TLBMISS_HANDLER_SETUP();
1437
1438 atomic_inc(&init_mm.mm_count);
1439 current->active_mm = &init_mm;
1440 BUG_ON(current->mm);
1441 enter_lazy_tlb(&init_mm, current);
1442
1443 #ifdef CONFIG_MIPS_MT_SMTC
1444 if (bootTC) {
1445 #endif /* CONFIG_MIPS_MT_SMTC */
1446 cpu_cache_init();
1447 tlb_init();
1448 #ifdef CONFIG_MIPS_MT_SMTC
1449 } else if (!secondaryTC) {
1450 /*
1451 * First TC in non-boot VPE must do subset of tlb_init()
1452 * for MMU countrol registers.
1453 */
1454 write_c0_pagemask(PM_DEFAULT_MASK);
1455 write_c0_wired(0);
1456 }
1457 #endif /* CONFIG_MIPS_MT_SMTC */
1458 }
1459
1460 /* Install CPU exception handler */
1461 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1462 {
1463 memcpy((void *)(ebase + offset), addr, size);
1464 flush_icache_range(ebase + offset, ebase + offset + size);
1465 }
1466
1467 static char panic_null_cerr[] __initdata =
1468 "Trying to set NULL cache error exception handler";
1469
1470 /* Install uncached CPU exception handler */
1471 void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
1472 {
1473 #ifdef CONFIG_32BIT
1474 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1475 #endif
1476 #ifdef CONFIG_64BIT
1477 unsigned long uncached_ebase = TO_UNCAC(ebase);
1478 #endif
1479
1480 if (!addr)
1481 panic(panic_null_cerr);
1482
1483 memcpy((void *)(uncached_ebase + offset), addr, size);
1484 }
1485
1486 static int __initdata rdhwr_noopt;
1487 static int __init set_rdhwr_noopt(char *str)
1488 {
1489 rdhwr_noopt = 1;
1490 return 1;
1491 }
1492
1493 __setup("rdhwr_noopt", set_rdhwr_noopt);
1494
1495 void __init trap_init(void)
1496 {
1497 extern char except_vec3_generic, except_vec3_r4000;
1498 extern char except_vec4;
1499 unsigned long i;
1500
1501 if (cpu_has_veic || cpu_has_vint)
1502 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1503 else
1504 ebase = CAC_BASE;
1505
1506 mips_srs_init();
1507
1508 per_cpu_trap_init();
1509
1510 /*
1511 * Copy the generic exception handlers to their final destination.
1512 * This will be overriden later as suitable for a particular
1513 * configuration.
1514 */
1515 set_handler(0x180, &except_vec3_generic, 0x80);
1516
1517 /*
1518 * Setup default vectors
1519 */
1520 for (i = 0; i <= 31; i++)
1521 set_except_vector(i, handle_reserved);
1522
1523 /*
1524 * Copy the EJTAG debug exception vector handler code to it's final
1525 * destination.
1526 */
1527 if (cpu_has_ejtag && board_ejtag_handler_setup)
1528 board_ejtag_handler_setup();
1529
1530 /*
1531 * Only some CPUs have the watch exceptions.
1532 */
1533 if (cpu_has_watch)
1534 set_except_vector(23, handle_watch);
1535
1536 /*
1537 * Initialise interrupt handlers
1538 */
1539 if (cpu_has_veic || cpu_has_vint) {
1540 int nvec = cpu_has_veic ? 64 : 8;
1541 for (i = 0; i < nvec; i++)
1542 set_vi_handler(i, NULL);
1543 }
1544 else if (cpu_has_divec)
1545 set_handler(0x200, &except_vec4, 0x8);
1546
1547 /*
1548 * Some CPUs can enable/disable for cache parity detection, but does
1549 * it different ways.
1550 */
1551 parity_protection_init();
1552
1553 /*
1554 * The Data Bus Errors / Instruction Bus Errors are signaled
1555 * by external hardware. Therefore these two exceptions
1556 * may have board specific handlers.
1557 */
1558 if (board_be_init)
1559 board_be_init();
1560
1561 set_except_vector(0, handle_int);
1562 set_except_vector(1, handle_tlbm);
1563 set_except_vector(2, handle_tlbl);
1564 set_except_vector(3, handle_tlbs);
1565
1566 set_except_vector(4, handle_adel);
1567 set_except_vector(5, handle_ades);
1568
1569 set_except_vector(6, handle_ibe);
1570 set_except_vector(7, handle_dbe);
1571
1572 set_except_vector(8, handle_sys);
1573 set_except_vector(9, handle_bp);
1574 set_except_vector(10, rdhwr_noopt ? handle_ri :
1575 (cpu_has_vtag_icache ?
1576 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1577 set_except_vector(11, handle_cpu);
1578 set_except_vector(12, handle_ov);
1579 set_except_vector(13, handle_tr);
1580
1581 if (current_cpu_type() == CPU_R6000 ||
1582 current_cpu_type() == CPU_R6000A) {
1583 /*
1584 * The R6000 is the only R-series CPU that features a machine
1585 * check exception (similar to the R4000 cache error) and
1586 * unaligned ldc1/sdc1 exception. The handlers have not been
1587 * written yet. Well, anyway there is no R6000 machine on the
1588 * current list of targets for Linux/MIPS.
1589 * (Duh, crap, there is someone with a triple R6k machine)
1590 */
1591 //set_except_vector(14, handle_mc);
1592 //set_except_vector(15, handle_ndc);
1593 }
1594
1595
1596 if (board_nmi_handler_setup)
1597 board_nmi_handler_setup();
1598
1599 if (cpu_has_fpu && !cpu_has_nofpuex)
1600 set_except_vector(15, handle_fpe);
1601
1602 set_except_vector(22, handle_mdmx);
1603
1604 if (cpu_has_mcheck)
1605 set_except_vector(24, handle_mcheck);
1606
1607 if (cpu_has_mipsmt)
1608 set_except_vector(25, handle_mt);
1609
1610 set_except_vector(26, handle_dsp);
1611
1612 if (cpu_has_vce)
1613 /* Special exception: R4[04]00 uses also the divec space. */
1614 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1615 else if (cpu_has_4kex)
1616 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1617 else
1618 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1619
1620 signal_init();
1621 #ifdef CONFIG_MIPS32_COMPAT
1622 signal32_init();
1623 #endif
1624
1625 flush_icache_range(ebase, ebase + 0x400);
1626 flush_tlb_handlers();
1627 }
Linux kernel - Deliverables
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