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MIPS: KVM: Print unknown load/store encodings
[deliverable/linux.git] / arch / mips / kvm / emulate.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: Instruction/Exception emulation
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/ktime.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/fs.h>
19 #include <linux/bootmem.h>
20 #include <linux/random.h>
21 #include <asm/page.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cacheops.h>
24 #include <asm/cpu-info.h>
25 #include <asm/mmu_context.h>
26 #include <asm/tlbflush.h>
27 #include <asm/inst.h>
28
29 #undef CONFIG_MIPS_MT
30 #include <asm/r4kcache.h>
31 #define CONFIG_MIPS_MT
32
33 #include "interrupt.h"
34 #include "commpage.h"
35
36 #include "trace.h"
37
38 /*
39 * Compute the return address and do emulate branch simulation, if required.
40 * This function should be called only in branch delay slot active.
41 */
42 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
43 unsigned long instpc)
44 {
45 unsigned int dspcontrol;
46 union mips_instruction insn;
47 struct kvm_vcpu_arch *arch = &vcpu->arch;
48 long epc = instpc;
49 long nextpc = KVM_INVALID_INST;
50
51 if (epc & 3)
52 goto unaligned;
53
54 /* Read the instruction */
55 insn.word = kvm_get_inst((u32 *) epc, vcpu);
56
57 if (insn.word == KVM_INVALID_INST)
58 return KVM_INVALID_INST;
59
60 switch (insn.i_format.opcode) {
61 /* jr and jalr are in r_format format. */
62 case spec_op:
63 switch (insn.r_format.func) {
64 case jalr_op:
65 arch->gprs[insn.r_format.rd] = epc + 8;
66 /* Fall through */
67 case jr_op:
68 nextpc = arch->gprs[insn.r_format.rs];
69 break;
70 }
71 break;
72
73 /*
74 * This group contains:
75 * bltz_op, bgez_op, bltzl_op, bgezl_op,
76 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
77 */
78 case bcond_op:
79 switch (insn.i_format.rt) {
80 case bltz_op:
81 case bltzl_op:
82 if ((long)arch->gprs[insn.i_format.rs] < 0)
83 epc = epc + 4 + (insn.i_format.simmediate << 2);
84 else
85 epc += 8;
86 nextpc = epc;
87 break;
88
89 case bgez_op:
90 case bgezl_op:
91 if ((long)arch->gprs[insn.i_format.rs] >= 0)
92 epc = epc + 4 + (insn.i_format.simmediate << 2);
93 else
94 epc += 8;
95 nextpc = epc;
96 break;
97
98 case bltzal_op:
99 case bltzall_op:
100 arch->gprs[31] = epc + 8;
101 if ((long)arch->gprs[insn.i_format.rs] < 0)
102 epc = epc + 4 + (insn.i_format.simmediate << 2);
103 else
104 epc += 8;
105 nextpc = epc;
106 break;
107
108 case bgezal_op:
109 case bgezall_op:
110 arch->gprs[31] = epc + 8;
111 if ((long)arch->gprs[insn.i_format.rs] >= 0)
112 epc = epc + 4 + (insn.i_format.simmediate << 2);
113 else
114 epc += 8;
115 nextpc = epc;
116 break;
117 case bposge32_op:
118 if (!cpu_has_dsp)
119 goto sigill;
120
121 dspcontrol = rddsp(0x01);
122
123 if (dspcontrol >= 32)
124 epc = epc + 4 + (insn.i_format.simmediate << 2);
125 else
126 epc += 8;
127 nextpc = epc;
128 break;
129 }
130 break;
131
132 /* These are unconditional and in j_format. */
133 case jal_op:
134 arch->gprs[31] = instpc + 8;
135 case j_op:
136 epc += 4;
137 epc >>= 28;
138 epc <<= 28;
139 epc |= (insn.j_format.target << 2);
140 nextpc = epc;
141 break;
142
143 /* These are conditional and in i_format. */
144 case beq_op:
145 case beql_op:
146 if (arch->gprs[insn.i_format.rs] ==
147 arch->gprs[insn.i_format.rt])
148 epc = epc + 4 + (insn.i_format.simmediate << 2);
149 else
150 epc += 8;
151 nextpc = epc;
152 break;
153
154 case bne_op:
155 case bnel_op:
156 if (arch->gprs[insn.i_format.rs] !=
157 arch->gprs[insn.i_format.rt])
158 epc = epc + 4 + (insn.i_format.simmediate << 2);
159 else
160 epc += 8;
161 nextpc = epc;
162 break;
163
164 case blez_op: /* not really i_format */
165 case blezl_op:
166 /* rt field assumed to be zero */
167 if ((long)arch->gprs[insn.i_format.rs] <= 0)
168 epc = epc + 4 + (insn.i_format.simmediate << 2);
169 else
170 epc += 8;
171 nextpc = epc;
172 break;
173
174 case bgtz_op:
175 case bgtzl_op:
176 /* rt field assumed to be zero */
177 if ((long)arch->gprs[insn.i_format.rs] > 0)
178 epc = epc + 4 + (insn.i_format.simmediate << 2);
179 else
180 epc += 8;
181 nextpc = epc;
182 break;
183
184 /* And now the FPA/cp1 branch instructions. */
185 case cop1_op:
186 kvm_err("%s: unsupported cop1_op\n", __func__);
187 break;
188 }
189
190 return nextpc;
191
192 unaligned:
193 kvm_err("%s: unaligned epc\n", __func__);
194 return nextpc;
195
196 sigill:
197 kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
198 return nextpc;
199 }
200
201 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause)
202 {
203 unsigned long branch_pc;
204 enum emulation_result er = EMULATE_DONE;
205
206 if (cause & CAUSEF_BD) {
207 branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
208 if (branch_pc == KVM_INVALID_INST) {
209 er = EMULATE_FAIL;
210 } else {
211 vcpu->arch.pc = branch_pc;
212 kvm_debug("BD update_pc(): New PC: %#lx\n",
213 vcpu->arch.pc);
214 }
215 } else
216 vcpu->arch.pc += 4;
217
218 kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
219
220 return er;
221 }
222
223 /**
224 * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
225 * @vcpu: Virtual CPU.
226 *
227 * Returns: 1 if the CP0_Count timer is disabled by either the guest
228 * CP0_Cause.DC bit or the count_ctl.DC bit.
229 * 0 otherwise (in which case CP0_Count timer is running).
230 */
231 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
232 {
233 struct mips_coproc *cop0 = vcpu->arch.cop0;
234
235 return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
236 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
237 }
238
239 /**
240 * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
241 *
242 * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
243 *
244 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
245 */
246 static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
247 {
248 s64 now_ns, periods;
249 u64 delta;
250
251 now_ns = ktime_to_ns(now);
252 delta = now_ns + vcpu->arch.count_dyn_bias;
253
254 if (delta >= vcpu->arch.count_period) {
255 /* If delta is out of safe range the bias needs adjusting */
256 periods = div64_s64(now_ns, vcpu->arch.count_period);
257 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
258 /* Recalculate delta with new bias */
259 delta = now_ns + vcpu->arch.count_dyn_bias;
260 }
261
262 /*
263 * We've ensured that:
264 * delta < count_period
265 *
266 * Therefore the intermediate delta*count_hz will never overflow since
267 * at the boundary condition:
268 * delta = count_period
269 * delta = NSEC_PER_SEC * 2^32 / count_hz
270 * delta * count_hz = NSEC_PER_SEC * 2^32
271 */
272 return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
273 }
274
275 /**
276 * kvm_mips_count_time() - Get effective current time.
277 * @vcpu: Virtual CPU.
278 *
279 * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
280 * except when the master disable bit is set in count_ctl, in which case it is
281 * count_resume, i.e. the time that the count was disabled.
282 *
283 * Returns: Effective monotonic ktime for CP0_Count.
284 */
285 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
286 {
287 if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
288 return vcpu->arch.count_resume;
289
290 return ktime_get();
291 }
292
293 /**
294 * kvm_mips_read_count_running() - Read the current count value as if running.
295 * @vcpu: Virtual CPU.
296 * @now: Kernel time to read CP0_Count at.
297 *
298 * Returns the current guest CP0_Count register at time @now and handles if the
299 * timer interrupt is pending and hasn't been handled yet.
300 *
301 * Returns: The current value of the guest CP0_Count register.
302 */
303 static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
304 {
305 struct mips_coproc *cop0 = vcpu->arch.cop0;
306 ktime_t expires, threshold;
307 u32 count, compare;
308 int running;
309
310 /* Calculate the biased and scaled guest CP0_Count */
311 count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
312 compare = kvm_read_c0_guest_compare(cop0);
313
314 /*
315 * Find whether CP0_Count has reached the closest timer interrupt. If
316 * not, we shouldn't inject it.
317 */
318 if ((s32)(count - compare) < 0)
319 return count;
320
321 /*
322 * The CP0_Count we're going to return has already reached the closest
323 * timer interrupt. Quickly check if it really is a new interrupt by
324 * looking at whether the interval until the hrtimer expiry time is
325 * less than 1/4 of the timer period.
326 */
327 expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
328 threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
329 if (ktime_before(expires, threshold)) {
330 /*
331 * Cancel it while we handle it so there's no chance of
332 * interference with the timeout handler.
333 */
334 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
335
336 /* Nothing should be waiting on the timeout */
337 kvm_mips_callbacks->queue_timer_int(vcpu);
338
339 /*
340 * Restart the timer if it was running based on the expiry time
341 * we read, so that we don't push it back 2 periods.
342 */
343 if (running) {
344 expires = ktime_add_ns(expires,
345 vcpu->arch.count_period);
346 hrtimer_start(&vcpu->arch.comparecount_timer, expires,
347 HRTIMER_MODE_ABS);
348 }
349 }
350
351 return count;
352 }
353
354 /**
355 * kvm_mips_read_count() - Read the current count value.
356 * @vcpu: Virtual CPU.
357 *
358 * Read the current guest CP0_Count value, taking into account whether the timer
359 * is stopped.
360 *
361 * Returns: The current guest CP0_Count value.
362 */
363 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu)
364 {
365 struct mips_coproc *cop0 = vcpu->arch.cop0;
366
367 /* If count disabled just read static copy of count */
368 if (kvm_mips_count_disabled(vcpu))
369 return kvm_read_c0_guest_count(cop0);
370
371 return kvm_mips_read_count_running(vcpu, ktime_get());
372 }
373
374 /**
375 * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
376 * @vcpu: Virtual CPU.
377 * @count: Output pointer for CP0_Count value at point of freeze.
378 *
379 * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
380 * at the point it was frozen. It is guaranteed that any pending interrupts at
381 * the point it was frozen are handled, and none after that point.
382 *
383 * This is useful where the time/CP0_Count is needed in the calculation of the
384 * new parameters.
385 *
386 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
387 *
388 * Returns: The ktime at the point of freeze.
389 */
390 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count)
391 {
392 ktime_t now;
393
394 /* stop hrtimer before finding time */
395 hrtimer_cancel(&vcpu->arch.comparecount_timer);
396 now = ktime_get();
397
398 /* find count at this point and handle pending hrtimer */
399 *count = kvm_mips_read_count_running(vcpu, now);
400
401 return now;
402 }
403
404 /**
405 * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
406 * @vcpu: Virtual CPU.
407 * @now: ktime at point of resume.
408 * @count: CP0_Count at point of resume.
409 *
410 * Resumes the timer and updates the timer expiry based on @now and @count.
411 * This can be used in conjunction with kvm_mips_freeze_timer() when timer
412 * parameters need to be changed.
413 *
414 * It is guaranteed that a timer interrupt immediately after resume will be
415 * handled, but not if CP_Compare is exactly at @count. That case is already
416 * handled by kvm_mips_freeze_timer().
417 *
418 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
419 */
420 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
421 ktime_t now, u32 count)
422 {
423 struct mips_coproc *cop0 = vcpu->arch.cop0;
424 u32 compare;
425 u64 delta;
426 ktime_t expire;
427
428 /* Calculate timeout (wrap 0 to 2^32) */
429 compare = kvm_read_c0_guest_compare(cop0);
430 delta = (u64)(u32)(compare - count - 1) + 1;
431 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
432 expire = ktime_add_ns(now, delta);
433
434 /* Update hrtimer to use new timeout */
435 hrtimer_cancel(&vcpu->arch.comparecount_timer);
436 hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
437 }
438
439 /**
440 * kvm_mips_write_count() - Modify the count and update timer.
441 * @vcpu: Virtual CPU.
442 * @count: Guest CP0_Count value to set.
443 *
444 * Sets the CP0_Count value and updates the timer accordingly.
445 */
446 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count)
447 {
448 struct mips_coproc *cop0 = vcpu->arch.cop0;
449 ktime_t now;
450
451 /* Calculate bias */
452 now = kvm_mips_count_time(vcpu);
453 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
454
455 if (kvm_mips_count_disabled(vcpu))
456 /* The timer's disabled, adjust the static count */
457 kvm_write_c0_guest_count(cop0, count);
458 else
459 /* Update timeout */
460 kvm_mips_resume_hrtimer(vcpu, now, count);
461 }
462
463 /**
464 * kvm_mips_init_count() - Initialise timer.
465 * @vcpu: Virtual CPU.
466 *
467 * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
468 * it going if it's enabled.
469 */
470 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
471 {
472 /* 100 MHz */
473 vcpu->arch.count_hz = 100*1000*1000;
474 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
475 vcpu->arch.count_hz);
476 vcpu->arch.count_dyn_bias = 0;
477
478 /* Starting at 0 */
479 kvm_mips_write_count(vcpu, 0);
480 }
481
482 /**
483 * kvm_mips_set_count_hz() - Update the frequency of the timer.
484 * @vcpu: Virtual CPU.
485 * @count_hz: Frequency of CP0_Count timer in Hz.
486 *
487 * Change the frequency of the CP0_Count timer. This is done atomically so that
488 * CP0_Count is continuous and no timer interrupt is lost.
489 *
490 * Returns: -EINVAL if @count_hz is out of range.
491 * 0 on success.
492 */
493 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
494 {
495 struct mips_coproc *cop0 = vcpu->arch.cop0;
496 int dc;
497 ktime_t now;
498 u32 count;
499
500 /* ensure the frequency is in a sensible range... */
501 if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
502 return -EINVAL;
503 /* ... and has actually changed */
504 if (vcpu->arch.count_hz == count_hz)
505 return 0;
506
507 /* Safely freeze timer so we can keep it continuous */
508 dc = kvm_mips_count_disabled(vcpu);
509 if (dc) {
510 now = kvm_mips_count_time(vcpu);
511 count = kvm_read_c0_guest_count(cop0);
512 } else {
513 now = kvm_mips_freeze_hrtimer(vcpu, &count);
514 }
515
516 /* Update the frequency */
517 vcpu->arch.count_hz = count_hz;
518 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
519 vcpu->arch.count_dyn_bias = 0;
520
521 /* Calculate adjusted bias so dynamic count is unchanged */
522 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
523
524 /* Update and resume hrtimer */
525 if (!dc)
526 kvm_mips_resume_hrtimer(vcpu, now, count);
527 return 0;
528 }
529
530 /**
531 * kvm_mips_write_compare() - Modify compare and update timer.
532 * @vcpu: Virtual CPU.
533 * @compare: New CP0_Compare value.
534 * @ack: Whether to acknowledge timer interrupt.
535 *
536 * Update CP0_Compare to a new value and update the timeout.
537 * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
538 * any pending timer interrupt is preserved.
539 */
540 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
541 {
542 struct mips_coproc *cop0 = vcpu->arch.cop0;
543 int dc;
544 u32 old_compare = kvm_read_c0_guest_compare(cop0);
545 ktime_t now;
546 u32 count;
547
548 /* if unchanged, must just be an ack */
549 if (old_compare == compare) {
550 if (!ack)
551 return;
552 kvm_mips_callbacks->dequeue_timer_int(vcpu);
553 kvm_write_c0_guest_compare(cop0, compare);
554 return;
555 }
556
557 /* freeze_hrtimer() takes care of timer interrupts <= count */
558 dc = kvm_mips_count_disabled(vcpu);
559 if (!dc)
560 now = kvm_mips_freeze_hrtimer(vcpu, &count);
561
562 if (ack)
563 kvm_mips_callbacks->dequeue_timer_int(vcpu);
564
565 kvm_write_c0_guest_compare(cop0, compare);
566
567 /* resume_hrtimer() takes care of timer interrupts > count */
568 if (!dc)
569 kvm_mips_resume_hrtimer(vcpu, now, count);
570 }
571
572 /**
573 * kvm_mips_count_disable() - Disable count.
574 * @vcpu: Virtual CPU.
575 *
576 * Disable the CP0_Count timer. A timer interrupt on or before the final stop
577 * time will be handled but not after.
578 *
579 * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
580 * count_ctl.DC has been set (count disabled).
581 *
582 * Returns: The time that the timer was stopped.
583 */
584 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
585 {
586 struct mips_coproc *cop0 = vcpu->arch.cop0;
587 u32 count;
588 ktime_t now;
589
590 /* Stop hrtimer */
591 hrtimer_cancel(&vcpu->arch.comparecount_timer);
592
593 /* Set the static count from the dynamic count, handling pending TI */
594 now = ktime_get();
595 count = kvm_mips_read_count_running(vcpu, now);
596 kvm_write_c0_guest_count(cop0, count);
597
598 return now;
599 }
600
601 /**
602 * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
603 * @vcpu: Virtual CPU.
604 *
605 * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
606 * before the final stop time will be handled if the timer isn't disabled by
607 * count_ctl.DC, but not after.
608 *
609 * Assumes CP0_Cause.DC is clear (count enabled).
610 */
611 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
612 {
613 struct mips_coproc *cop0 = vcpu->arch.cop0;
614
615 kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
616 if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
617 kvm_mips_count_disable(vcpu);
618 }
619
620 /**
621 * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
622 * @vcpu: Virtual CPU.
623 *
624 * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
625 * the start time will be handled if the timer isn't disabled by count_ctl.DC,
626 * potentially before even returning, so the caller should be careful with
627 * ordering of CP0_Cause modifications so as not to lose it.
628 *
629 * Assumes CP0_Cause.DC is set (count disabled).
630 */
631 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
632 {
633 struct mips_coproc *cop0 = vcpu->arch.cop0;
634 u32 count;
635
636 kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
637
638 /*
639 * Set the dynamic count to match the static count.
640 * This starts the hrtimer if count_ctl.DC allows it.
641 * Otherwise it conveniently updates the biases.
642 */
643 count = kvm_read_c0_guest_count(cop0);
644 kvm_mips_write_count(vcpu, count);
645 }
646
647 /**
648 * kvm_mips_set_count_ctl() - Update the count control KVM register.
649 * @vcpu: Virtual CPU.
650 * @count_ctl: Count control register new value.
651 *
652 * Set the count control KVM register. The timer is updated accordingly.
653 *
654 * Returns: -EINVAL if reserved bits are set.
655 * 0 on success.
656 */
657 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
658 {
659 struct mips_coproc *cop0 = vcpu->arch.cop0;
660 s64 changed = count_ctl ^ vcpu->arch.count_ctl;
661 s64 delta;
662 ktime_t expire, now;
663 u32 count, compare;
664
665 /* Only allow defined bits to be changed */
666 if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
667 return -EINVAL;
668
669 /* Apply new value */
670 vcpu->arch.count_ctl = count_ctl;
671
672 /* Master CP0_Count disable */
673 if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
674 /* Is CP0_Cause.DC already disabling CP0_Count? */
675 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
676 if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
677 /* Just record the current time */
678 vcpu->arch.count_resume = ktime_get();
679 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
680 /* disable timer and record current time */
681 vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
682 } else {
683 /*
684 * Calculate timeout relative to static count at resume
685 * time (wrap 0 to 2^32).
686 */
687 count = kvm_read_c0_guest_count(cop0);
688 compare = kvm_read_c0_guest_compare(cop0);
689 delta = (u64)(u32)(compare - count - 1) + 1;
690 delta = div_u64(delta * NSEC_PER_SEC,
691 vcpu->arch.count_hz);
692 expire = ktime_add_ns(vcpu->arch.count_resume, delta);
693
694 /* Handle pending interrupt */
695 now = ktime_get();
696 if (ktime_compare(now, expire) >= 0)
697 /* Nothing should be waiting on the timeout */
698 kvm_mips_callbacks->queue_timer_int(vcpu);
699
700 /* Resume hrtimer without changing bias */
701 count = kvm_mips_read_count_running(vcpu, now);
702 kvm_mips_resume_hrtimer(vcpu, now, count);
703 }
704 }
705
706 return 0;
707 }
708
709 /**
710 * kvm_mips_set_count_resume() - Update the count resume KVM register.
711 * @vcpu: Virtual CPU.
712 * @count_resume: Count resume register new value.
713 *
714 * Set the count resume KVM register.
715 *
716 * Returns: -EINVAL if out of valid range (0..now).
717 * 0 on success.
718 */
719 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
720 {
721 /*
722 * It doesn't make sense for the resume time to be in the future, as it
723 * would be possible for the next interrupt to be more than a full
724 * period in the future.
725 */
726 if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
727 return -EINVAL;
728
729 vcpu->arch.count_resume = ns_to_ktime(count_resume);
730 return 0;
731 }
732
733 /**
734 * kvm_mips_count_timeout() - Push timer forward on timeout.
735 * @vcpu: Virtual CPU.
736 *
737 * Handle an hrtimer event by push the hrtimer forward a period.
738 *
739 * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
740 */
741 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
742 {
743 /* Add the Count period to the current expiry time */
744 hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
745 vcpu->arch.count_period);
746 return HRTIMER_RESTART;
747 }
748
749 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
750 {
751 struct mips_coproc *cop0 = vcpu->arch.cop0;
752 enum emulation_result er = EMULATE_DONE;
753
754 if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
755 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
756 kvm_read_c0_guest_epc(cop0));
757 kvm_clear_c0_guest_status(cop0, ST0_EXL);
758 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
759
760 } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
761 kvm_clear_c0_guest_status(cop0, ST0_ERL);
762 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
763 } else {
764 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
765 vcpu->arch.pc);
766 er = EMULATE_FAIL;
767 }
768
769 return er;
770 }
771
772 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
773 {
774 kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
775 vcpu->arch.pending_exceptions);
776
777 ++vcpu->stat.wait_exits;
778 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT);
779 if (!vcpu->arch.pending_exceptions) {
780 vcpu->arch.wait = 1;
781 kvm_vcpu_block(vcpu);
782
783 /*
784 * We we are runnable, then definitely go off to user space to
785 * check if any I/O interrupts are pending.
786 */
787 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
788 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
789 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
790 }
791 }
792
793 return EMULATE_DONE;
794 }
795
796 /*
797 * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
798 * we can catch this, if things ever change
799 */
800 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
801 {
802 struct mips_coproc *cop0 = vcpu->arch.cop0;
803 unsigned long pc = vcpu->arch.pc;
804
805 kvm_err("[%#lx] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
806 return EMULATE_FAIL;
807 }
808
809 /* Write Guest TLB Entry @ Index */
810 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
811 {
812 struct mips_coproc *cop0 = vcpu->arch.cop0;
813 int index = kvm_read_c0_guest_index(cop0);
814 struct kvm_mips_tlb *tlb = NULL;
815 unsigned long pc = vcpu->arch.pc;
816
817 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
818 kvm_debug("%s: illegal index: %d\n", __func__, index);
819 kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
820 pc, index, kvm_read_c0_guest_entryhi(cop0),
821 kvm_read_c0_guest_entrylo0(cop0),
822 kvm_read_c0_guest_entrylo1(cop0),
823 kvm_read_c0_guest_pagemask(cop0));
824 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
825 }
826
827 tlb = &vcpu->arch.guest_tlb[index];
828 /*
829 * Probe the shadow host TLB for the entry being overwritten, if one
830 * matches, invalidate it
831 */
832 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
833
834 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
835 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
836 tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
837 tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
838
839 kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
840 pc, index, kvm_read_c0_guest_entryhi(cop0),
841 kvm_read_c0_guest_entrylo0(cop0),
842 kvm_read_c0_guest_entrylo1(cop0),
843 kvm_read_c0_guest_pagemask(cop0));
844
845 return EMULATE_DONE;
846 }
847
848 /* Write Guest TLB Entry @ Random Index */
849 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
850 {
851 struct mips_coproc *cop0 = vcpu->arch.cop0;
852 struct kvm_mips_tlb *tlb = NULL;
853 unsigned long pc = vcpu->arch.pc;
854 int index;
855
856 get_random_bytes(&index, sizeof(index));
857 index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
858
859 tlb = &vcpu->arch.guest_tlb[index];
860
861 /*
862 * Probe the shadow host TLB for the entry being overwritten, if one
863 * matches, invalidate it
864 */
865 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
866
867 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
868 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
869 tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
870 tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
871
872 kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
873 pc, index, kvm_read_c0_guest_entryhi(cop0),
874 kvm_read_c0_guest_entrylo0(cop0),
875 kvm_read_c0_guest_entrylo1(cop0));
876
877 return EMULATE_DONE;
878 }
879
880 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
881 {
882 struct mips_coproc *cop0 = vcpu->arch.cop0;
883 long entryhi = kvm_read_c0_guest_entryhi(cop0);
884 unsigned long pc = vcpu->arch.pc;
885 int index = -1;
886
887 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
888
889 kvm_write_c0_guest_index(cop0, index);
890
891 kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
892 index);
893
894 return EMULATE_DONE;
895 }
896
897 /**
898 * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
899 * @vcpu: Virtual CPU.
900 *
901 * Finds the mask of bits which are writable in the guest's Config1 CP0
902 * register, by userland (currently read-only to the guest).
903 */
904 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
905 {
906 unsigned int mask = 0;
907
908 /* Permit FPU to be present if FPU is supported */
909 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
910 mask |= MIPS_CONF1_FP;
911
912 return mask;
913 }
914
915 /**
916 * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
917 * @vcpu: Virtual CPU.
918 *
919 * Finds the mask of bits which are writable in the guest's Config3 CP0
920 * register, by userland (currently read-only to the guest).
921 */
922 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
923 {
924 /* Config4 is optional */
925 unsigned int mask = MIPS_CONF_M;
926
927 /* Permit MSA to be present if MSA is supported */
928 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
929 mask |= MIPS_CONF3_MSA;
930
931 return mask;
932 }
933
934 /**
935 * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
936 * @vcpu: Virtual CPU.
937 *
938 * Finds the mask of bits which are writable in the guest's Config4 CP0
939 * register, by userland (currently read-only to the guest).
940 */
941 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
942 {
943 /* Config5 is optional */
944 return MIPS_CONF_M;
945 }
946
947 /**
948 * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
949 * @vcpu: Virtual CPU.
950 *
951 * Finds the mask of bits which are writable in the guest's Config5 CP0
952 * register, by the guest itself.
953 */
954 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
955 {
956 unsigned int mask = 0;
957
958 /* Permit MSAEn changes if MSA supported and enabled */
959 if (kvm_mips_guest_has_msa(&vcpu->arch))
960 mask |= MIPS_CONF5_MSAEN;
961
962 /*
963 * Permit guest FPU mode changes if FPU is enabled and the relevant
964 * feature exists according to FIR register.
965 */
966 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
967 if (cpu_has_fre)
968 mask |= MIPS_CONF5_FRE;
969 /* We don't support UFR or UFE */
970 }
971
972 return mask;
973 }
974
975 enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
976 struct kvm_run *run,
977 struct kvm_vcpu *vcpu)
978 {
979 struct mips_coproc *cop0 = vcpu->arch.cop0;
980 enum emulation_result er = EMULATE_DONE;
981 u32 rt, rd, copz, sel, co_bit, op;
982 unsigned long curr_pc;
983
984 /*
985 * Update PC and hold onto current PC in case there is
986 * an error and we want to rollback the PC
987 */
988 curr_pc = vcpu->arch.pc;
989 er = update_pc(vcpu, cause);
990 if (er == EMULATE_FAIL)
991 return er;
992
993 copz = (inst >> 21) & 0x1f;
994 rt = (inst >> 16) & 0x1f;
995 rd = (inst >> 11) & 0x1f;
996 sel = inst & 0x7;
997 co_bit = (inst >> 25) & 1;
998
999 if (co_bit) {
1000 op = (inst) & 0xff;
1001
1002 switch (op) {
1003 case tlbr_op: /* Read indexed TLB entry */
1004 er = kvm_mips_emul_tlbr(vcpu);
1005 break;
1006 case tlbwi_op: /* Write indexed */
1007 er = kvm_mips_emul_tlbwi(vcpu);
1008 break;
1009 case tlbwr_op: /* Write random */
1010 er = kvm_mips_emul_tlbwr(vcpu);
1011 break;
1012 case tlbp_op: /* TLB Probe */
1013 er = kvm_mips_emul_tlbp(vcpu);
1014 break;
1015 case rfe_op:
1016 kvm_err("!!!COP0_RFE!!!\n");
1017 break;
1018 case eret_op:
1019 er = kvm_mips_emul_eret(vcpu);
1020 goto dont_update_pc;
1021 break;
1022 case wait_op:
1023 er = kvm_mips_emul_wait(vcpu);
1024 break;
1025 }
1026 } else {
1027 switch (copz) {
1028 case mfc_op:
1029 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1030 cop0->stat[rd][sel]++;
1031 #endif
1032 /* Get reg */
1033 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1034 vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
1035 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1036 vcpu->arch.gprs[rt] = 0x0;
1037 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1038 kvm_mips_trans_mfc0(inst, opc, vcpu);
1039 #endif
1040 } else {
1041 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1042
1043 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1044 kvm_mips_trans_mfc0(inst, opc, vcpu);
1045 #endif
1046 }
1047
1048 trace_kvm_hwr(vcpu, KVM_TRACE_MFC0,
1049 KVM_TRACE_COP0(rd, sel),
1050 vcpu->arch.gprs[rt]);
1051 break;
1052
1053 case dmfc_op:
1054 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1055
1056 trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0,
1057 KVM_TRACE_COP0(rd, sel),
1058 vcpu->arch.gprs[rt]);
1059 break;
1060
1061 case mtc_op:
1062 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1063 cop0->stat[rd][sel]++;
1064 #endif
1065 trace_kvm_hwr(vcpu, KVM_TRACE_MTC0,
1066 KVM_TRACE_COP0(rd, sel),
1067 vcpu->arch.gprs[rt]);
1068
1069 if ((rd == MIPS_CP0_TLB_INDEX)
1070 && (vcpu->arch.gprs[rt] >=
1071 KVM_MIPS_GUEST_TLB_SIZE)) {
1072 kvm_err("Invalid TLB Index: %ld",
1073 vcpu->arch.gprs[rt]);
1074 er = EMULATE_FAIL;
1075 break;
1076 }
1077 #define C0_EBASE_CORE_MASK 0xff
1078 if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1079 /* Preserve CORE number */
1080 kvm_change_c0_guest_ebase(cop0,
1081 ~(C0_EBASE_CORE_MASK),
1082 vcpu->arch.gprs[rt]);
1083 kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
1084 kvm_read_c0_guest_ebase(cop0));
1085 } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1086 u32 nasid =
1087 vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID;
1088 if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
1089 ((kvm_read_c0_guest_entryhi(cop0) &
1090 KVM_ENTRYHI_ASID) != nasid)) {
1091 trace_kvm_asid_change(vcpu,
1092 kvm_read_c0_guest_entryhi(cop0)
1093 & KVM_ENTRYHI_ASID,
1094 nasid);
1095
1096 /* Blow away the shadow host TLBs */
1097 kvm_mips_flush_host_tlb(1);
1098 }
1099 kvm_write_c0_guest_entryhi(cop0,
1100 vcpu->arch.gprs[rt]);
1101 }
1102 /* Are we writing to COUNT */
1103 else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1104 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1105 goto done;
1106 } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1107 /* If we are writing to COMPARE */
1108 /* Clear pending timer interrupt, if any */
1109 kvm_mips_write_compare(vcpu,
1110 vcpu->arch.gprs[rt],
1111 true);
1112 } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1113 unsigned int old_val, val, change;
1114
1115 old_val = kvm_read_c0_guest_status(cop0);
1116 val = vcpu->arch.gprs[rt];
1117 change = val ^ old_val;
1118
1119 /* Make sure that the NMI bit is never set */
1120 val &= ~ST0_NMI;
1121
1122 /*
1123 * Don't allow CU1 or FR to be set unless FPU
1124 * capability enabled and exists in guest
1125 * configuration.
1126 */
1127 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1128 val &= ~(ST0_CU1 | ST0_FR);
1129
1130 /*
1131 * Also don't allow FR to be set if host doesn't
1132 * support it.
1133 */
1134 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1135 val &= ~ST0_FR;
1136
1137
1138 /* Handle changes in FPU mode */
1139 preempt_disable();
1140
1141 /*
1142 * FPU and Vector register state is made
1143 * UNPREDICTABLE by a change of FR, so don't
1144 * even bother saving it.
1145 */
1146 if (change & ST0_FR)
1147 kvm_drop_fpu(vcpu);
1148
1149 /*
1150 * If MSA state is already live, it is undefined
1151 * how it interacts with FR=0 FPU state, and we
1152 * don't want to hit reserved instruction
1153 * exceptions trying to save the MSA state later
1154 * when CU=1 && FR=1, so play it safe and save
1155 * it first.
1156 */
1157 if (change & ST0_CU1 && !(val & ST0_FR) &&
1158 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1159 kvm_lose_fpu(vcpu);
1160
1161 /*
1162 * Propagate CU1 (FPU enable) changes
1163 * immediately if the FPU context is already
1164 * loaded. When disabling we leave the context
1165 * loaded so it can be quickly enabled again in
1166 * the near future.
1167 */
1168 if (change & ST0_CU1 &&
1169 vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1170 change_c0_status(ST0_CU1, val);
1171
1172 preempt_enable();
1173
1174 kvm_write_c0_guest_status(cop0, val);
1175
1176 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1177 /*
1178 * If FPU present, we need CU1/FR bits to take
1179 * effect fairly soon.
1180 */
1181 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1182 kvm_mips_trans_mtc0(inst, opc, vcpu);
1183 #endif
1184 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1185 unsigned int old_val, val, change, wrmask;
1186
1187 old_val = kvm_read_c0_guest_config5(cop0);
1188 val = vcpu->arch.gprs[rt];
1189
1190 /* Only a few bits are writable in Config5 */
1191 wrmask = kvm_mips_config5_wrmask(vcpu);
1192 change = (val ^ old_val) & wrmask;
1193 val = old_val ^ change;
1194
1195
1196 /* Handle changes in FPU/MSA modes */
1197 preempt_disable();
1198
1199 /*
1200 * Propagate FRE changes immediately if the FPU
1201 * context is already loaded.
1202 */
1203 if (change & MIPS_CONF5_FRE &&
1204 vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1205 change_c0_config5(MIPS_CONF5_FRE, val);
1206
1207 /*
1208 * Propagate MSAEn changes immediately if the
1209 * MSA context is already loaded. When disabling
1210 * we leave the context loaded so it can be
1211 * quickly enabled again in the near future.
1212 */
1213 if (change & MIPS_CONF5_MSAEN &&
1214 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1215 change_c0_config5(MIPS_CONF5_MSAEN,
1216 val);
1217
1218 preempt_enable();
1219
1220 kvm_write_c0_guest_config5(cop0, val);
1221 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1222 u32 old_cause, new_cause;
1223
1224 old_cause = kvm_read_c0_guest_cause(cop0);
1225 new_cause = vcpu->arch.gprs[rt];
1226 /* Update R/W bits */
1227 kvm_change_c0_guest_cause(cop0, 0x08800300,
1228 new_cause);
1229 /* DC bit enabling/disabling timer? */
1230 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1231 if (new_cause & CAUSEF_DC)
1232 kvm_mips_count_disable_cause(vcpu);
1233 else
1234 kvm_mips_count_enable_cause(vcpu);
1235 }
1236 } else {
1237 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1238 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1239 kvm_mips_trans_mtc0(inst, opc, vcpu);
1240 #endif
1241 }
1242 break;
1243
1244 case dmtc_op:
1245 kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1246 vcpu->arch.pc, rt, rd, sel);
1247 trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0,
1248 KVM_TRACE_COP0(rd, sel),
1249 vcpu->arch.gprs[rt]);
1250 er = EMULATE_FAIL;
1251 break;
1252
1253 case mfmc0_op:
1254 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1255 cop0->stat[MIPS_CP0_STATUS][0]++;
1256 #endif
1257 if (rt != 0)
1258 vcpu->arch.gprs[rt] =
1259 kvm_read_c0_guest_status(cop0);
1260 /* EI */
1261 if (inst & 0x20) {
1262 kvm_debug("[%#lx] mfmc0_op: EI\n",
1263 vcpu->arch.pc);
1264 kvm_set_c0_guest_status(cop0, ST0_IE);
1265 } else {
1266 kvm_debug("[%#lx] mfmc0_op: DI\n",
1267 vcpu->arch.pc);
1268 kvm_clear_c0_guest_status(cop0, ST0_IE);
1269 }
1270
1271 break;
1272
1273 case wrpgpr_op:
1274 {
1275 u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1276 u32 pss =
1277 (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1278 /*
1279 * We don't support any shadow register sets, so
1280 * SRSCtl[PSS] == SRSCtl[CSS] = 0
1281 */
1282 if (css || pss) {
1283 er = EMULATE_FAIL;
1284 break;
1285 }
1286 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1287 vcpu->arch.gprs[rt]);
1288 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1289 }
1290 break;
1291 default:
1292 kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1293 vcpu->arch.pc, copz);
1294 er = EMULATE_FAIL;
1295 break;
1296 }
1297 }
1298
1299 done:
1300 /* Rollback PC only if emulation was unsuccessful */
1301 if (er == EMULATE_FAIL)
1302 vcpu->arch.pc = curr_pc;
1303
1304 dont_update_pc:
1305 /*
1306 * This is for special instructions whose emulation
1307 * updates the PC, so do not overwrite the PC under
1308 * any circumstances
1309 */
1310
1311 return er;
1312 }
1313
1314 enum emulation_result kvm_mips_emulate_store(u32 inst, u32 cause,
1315 struct kvm_run *run,
1316 struct kvm_vcpu *vcpu)
1317 {
1318 enum emulation_result er = EMULATE_DO_MMIO;
1319 u32 op, base, rt;
1320 s16 offset;
1321 u32 bytes;
1322 void *data = run->mmio.data;
1323 unsigned long curr_pc;
1324
1325 /*
1326 * Update PC and hold onto current PC in case there is
1327 * an error and we want to rollback the PC
1328 */
1329 curr_pc = vcpu->arch.pc;
1330 er = update_pc(vcpu, cause);
1331 if (er == EMULATE_FAIL)
1332 return er;
1333
1334 rt = (inst >> 16) & 0x1f;
1335 base = (inst >> 21) & 0x1f;
1336 offset = (s16)inst;
1337 op = (inst >> 26) & 0x3f;
1338
1339 switch (op) {
1340 case sb_op:
1341 bytes = 1;
1342 if (bytes > sizeof(run->mmio.data)) {
1343 kvm_err("%s: bad MMIO length: %d\n", __func__,
1344 run->mmio.len);
1345 }
1346 run->mmio.phys_addr =
1347 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1348 host_cp0_badvaddr);
1349 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1350 er = EMULATE_FAIL;
1351 break;
1352 }
1353 run->mmio.len = bytes;
1354 run->mmio.is_write = 1;
1355 vcpu->mmio_needed = 1;
1356 vcpu->mmio_is_write = 1;
1357 *(u8 *) data = vcpu->arch.gprs[rt];
1358 kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1359 vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
1360 *(u8 *) data);
1361
1362 break;
1363
1364 case sw_op:
1365 bytes = 4;
1366 if (bytes > sizeof(run->mmio.data)) {
1367 kvm_err("%s: bad MMIO length: %d\n", __func__,
1368 run->mmio.len);
1369 }
1370 run->mmio.phys_addr =
1371 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1372 host_cp0_badvaddr);
1373 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1374 er = EMULATE_FAIL;
1375 break;
1376 }
1377
1378 run->mmio.len = bytes;
1379 run->mmio.is_write = 1;
1380 vcpu->mmio_needed = 1;
1381 vcpu->mmio_is_write = 1;
1382 *(u32 *) data = vcpu->arch.gprs[rt];
1383
1384 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1385 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1386 vcpu->arch.gprs[rt], *(u32 *) data);
1387 break;
1388
1389 case sh_op:
1390 bytes = 2;
1391 if (bytes > sizeof(run->mmio.data)) {
1392 kvm_err("%s: bad MMIO length: %d\n", __func__,
1393 run->mmio.len);
1394 }
1395 run->mmio.phys_addr =
1396 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1397 host_cp0_badvaddr);
1398 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1399 er = EMULATE_FAIL;
1400 break;
1401 }
1402
1403 run->mmio.len = bytes;
1404 run->mmio.is_write = 1;
1405 vcpu->mmio_needed = 1;
1406 vcpu->mmio_is_write = 1;
1407 *(u16 *) data = vcpu->arch.gprs[rt];
1408
1409 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1410 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1411 vcpu->arch.gprs[rt], *(u32 *) data);
1412 break;
1413
1414 default:
1415 kvm_err("Store not yet supported (inst=0x%08x)\n",
1416 inst);
1417 er = EMULATE_FAIL;
1418 break;
1419 }
1420
1421 /* Rollback PC if emulation was unsuccessful */
1422 if (er == EMULATE_FAIL)
1423 vcpu->arch.pc = curr_pc;
1424
1425 return er;
1426 }
1427
1428 enum emulation_result kvm_mips_emulate_load(u32 inst, u32 cause,
1429 struct kvm_run *run,
1430 struct kvm_vcpu *vcpu)
1431 {
1432 enum emulation_result er = EMULATE_DO_MMIO;
1433 u32 op, base, rt;
1434 s16 offset;
1435 u32 bytes;
1436
1437 rt = (inst >> 16) & 0x1f;
1438 base = (inst >> 21) & 0x1f;
1439 offset = (s16)inst;
1440 op = (inst >> 26) & 0x3f;
1441
1442 vcpu->arch.pending_load_cause = cause;
1443 vcpu->arch.io_gpr = rt;
1444
1445 switch (op) {
1446 case lw_op:
1447 bytes = 4;
1448 if (bytes > sizeof(run->mmio.data)) {
1449 kvm_err("%s: bad MMIO length: %d\n", __func__,
1450 run->mmio.len);
1451 er = EMULATE_FAIL;
1452 break;
1453 }
1454 run->mmio.phys_addr =
1455 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1456 host_cp0_badvaddr);
1457 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1458 er = EMULATE_FAIL;
1459 break;
1460 }
1461
1462 run->mmio.len = bytes;
1463 run->mmio.is_write = 0;
1464 vcpu->mmio_needed = 1;
1465 vcpu->mmio_is_write = 0;
1466 break;
1467
1468 case lh_op:
1469 case lhu_op:
1470 bytes = 2;
1471 if (bytes > sizeof(run->mmio.data)) {
1472 kvm_err("%s: bad MMIO length: %d\n", __func__,
1473 run->mmio.len);
1474 er = EMULATE_FAIL;
1475 break;
1476 }
1477 run->mmio.phys_addr =
1478 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1479 host_cp0_badvaddr);
1480 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1481 er = EMULATE_FAIL;
1482 break;
1483 }
1484
1485 run->mmio.len = bytes;
1486 run->mmio.is_write = 0;
1487 vcpu->mmio_needed = 1;
1488 vcpu->mmio_is_write = 0;
1489
1490 if (op == lh_op)
1491 vcpu->mmio_needed = 2;
1492 else
1493 vcpu->mmio_needed = 1;
1494
1495 break;
1496
1497 case lbu_op:
1498 case lb_op:
1499 bytes = 1;
1500 if (bytes > sizeof(run->mmio.data)) {
1501 kvm_err("%s: bad MMIO length: %d\n", __func__,
1502 run->mmio.len);
1503 er = EMULATE_FAIL;
1504 break;
1505 }
1506 run->mmio.phys_addr =
1507 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1508 host_cp0_badvaddr);
1509 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1510 er = EMULATE_FAIL;
1511 break;
1512 }
1513
1514 run->mmio.len = bytes;
1515 run->mmio.is_write = 0;
1516 vcpu->mmio_is_write = 0;
1517
1518 if (op == lb_op)
1519 vcpu->mmio_needed = 2;
1520 else
1521 vcpu->mmio_needed = 1;
1522
1523 break;
1524
1525 default:
1526 kvm_err("Load not yet supported (inst=0x%08x)\n",
1527 inst);
1528 er = EMULATE_FAIL;
1529 break;
1530 }
1531
1532 return er;
1533 }
1534
1535 enum emulation_result kvm_mips_emulate_cache(u32 inst, u32 *opc,
1536 u32 cause,
1537 struct kvm_run *run,
1538 struct kvm_vcpu *vcpu)
1539 {
1540 struct mips_coproc *cop0 = vcpu->arch.cop0;
1541 enum emulation_result er = EMULATE_DONE;
1542 u32 cache, op_inst, op, base;
1543 s16 offset;
1544 struct kvm_vcpu_arch *arch = &vcpu->arch;
1545 unsigned long va;
1546 unsigned long curr_pc;
1547
1548 /*
1549 * Update PC and hold onto current PC in case there is
1550 * an error and we want to rollback the PC
1551 */
1552 curr_pc = vcpu->arch.pc;
1553 er = update_pc(vcpu, cause);
1554 if (er == EMULATE_FAIL)
1555 return er;
1556
1557 base = (inst >> 21) & 0x1f;
1558 op_inst = (inst >> 16) & 0x1f;
1559 offset = (s16)inst;
1560 cache = op_inst & CacheOp_Cache;
1561 op = op_inst & CacheOp_Op;
1562
1563 va = arch->gprs[base] + offset;
1564
1565 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1566 cache, op, base, arch->gprs[base], offset);
1567
1568 /*
1569 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
1570 * invalidate the caches entirely by stepping through all the
1571 * ways/indexes
1572 */
1573 if (op == Index_Writeback_Inv) {
1574 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1575 vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
1576 arch->gprs[base], offset);
1577
1578 if (cache == Cache_D)
1579 r4k_blast_dcache();
1580 else if (cache == Cache_I)
1581 r4k_blast_icache();
1582 else {
1583 kvm_err("%s: unsupported CACHE INDEX operation\n",
1584 __func__);
1585 return EMULATE_FAIL;
1586 }
1587
1588 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1589 kvm_mips_trans_cache_index(inst, opc, vcpu);
1590 #endif
1591 goto done;
1592 }
1593
1594 preempt_disable();
1595 if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
1596 if (kvm_mips_host_tlb_lookup(vcpu, va) < 0)
1597 kvm_mips_handle_kseg0_tlb_fault(va, vcpu);
1598 } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
1599 KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
1600 int index;
1601
1602 /* If an entry already exists then skip */
1603 if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
1604 goto skip_fault;
1605
1606 /*
1607 * If address not in the guest TLB, then give the guest a fault,
1608 * the resulting handler will do the right thing
1609 */
1610 index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
1611 (kvm_read_c0_guest_entryhi
1612 (cop0) & KVM_ENTRYHI_ASID));
1613
1614 if (index < 0) {
1615 vcpu->arch.host_cp0_badvaddr = va;
1616 vcpu->arch.pc = curr_pc;
1617 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1618 vcpu);
1619 preempt_enable();
1620 goto dont_update_pc;
1621 } else {
1622 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
1623 /*
1624 * Check if the entry is valid, if not then setup a TLB
1625 * invalid exception to the guest
1626 */
1627 if (!TLB_IS_VALID(*tlb, va)) {
1628 vcpu->arch.host_cp0_badvaddr = va;
1629 vcpu->arch.pc = curr_pc;
1630 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1631 run, vcpu);
1632 preempt_enable();
1633 goto dont_update_pc;
1634 } else {
1635 /*
1636 * We fault an entry from the guest tlb to the
1637 * shadow host TLB
1638 */
1639 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb);
1640 }
1641 }
1642 } else {
1643 kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1644 cache, op, base, arch->gprs[base], offset);
1645 er = EMULATE_FAIL;
1646 preempt_enable();
1647 goto done;
1648
1649 }
1650
1651 skip_fault:
1652 /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
1653 if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
1654 flush_dcache_line(va);
1655
1656 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1657 /*
1658 * Replace the CACHE instruction, with a SYNCI, not the same,
1659 * but avoids a trap
1660 */
1661 kvm_mips_trans_cache_va(inst, opc, vcpu);
1662 #endif
1663 } else if (op_inst == Hit_Invalidate_I) {
1664 flush_dcache_line(va);
1665 flush_icache_line(va);
1666
1667 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1668 /* Replace the CACHE instruction, with a SYNCI */
1669 kvm_mips_trans_cache_va(inst, opc, vcpu);
1670 #endif
1671 } else {
1672 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1673 cache, op, base, arch->gprs[base], offset);
1674 er = EMULATE_FAIL;
1675 }
1676
1677 preempt_enable();
1678 done:
1679 /* Rollback PC only if emulation was unsuccessful */
1680 if (er == EMULATE_FAIL)
1681 vcpu->arch.pc = curr_pc;
1682
1683 dont_update_pc:
1684 /*
1685 * This is for exceptions whose emulation updates the PC, so do not
1686 * overwrite the PC under any circumstances
1687 */
1688
1689 return er;
1690 }
1691
1692 enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
1693 struct kvm_run *run,
1694 struct kvm_vcpu *vcpu)
1695 {
1696 enum emulation_result er = EMULATE_DONE;
1697 u32 inst;
1698
1699 /* Fetch the instruction. */
1700 if (cause & CAUSEF_BD)
1701 opc += 1;
1702
1703 inst = kvm_get_inst(opc, vcpu);
1704
1705 switch (((union mips_instruction)inst).r_format.opcode) {
1706 case cop0_op:
1707 er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
1708 break;
1709 case sb_op:
1710 case sh_op:
1711 case sw_op:
1712 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1713 break;
1714 case lb_op:
1715 case lbu_op:
1716 case lhu_op:
1717 case lh_op:
1718 case lw_op:
1719 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1720 break;
1721
1722 case cache_op:
1723 ++vcpu->stat.cache_exits;
1724 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
1725 er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
1726 break;
1727
1728 default:
1729 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
1730 inst);
1731 kvm_arch_vcpu_dump_regs(vcpu);
1732 er = EMULATE_FAIL;
1733 break;
1734 }
1735
1736 return er;
1737 }
1738
1739 enum emulation_result kvm_mips_emulate_syscall(u32 cause,
1740 u32 *opc,
1741 struct kvm_run *run,
1742 struct kvm_vcpu *vcpu)
1743 {
1744 struct mips_coproc *cop0 = vcpu->arch.cop0;
1745 struct kvm_vcpu_arch *arch = &vcpu->arch;
1746 enum emulation_result er = EMULATE_DONE;
1747
1748 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1749 /* save old pc */
1750 kvm_write_c0_guest_epc(cop0, arch->pc);
1751 kvm_set_c0_guest_status(cop0, ST0_EXL);
1752
1753 if (cause & CAUSEF_BD)
1754 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1755 else
1756 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1757
1758 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
1759
1760 kvm_change_c0_guest_cause(cop0, (0xff),
1761 (EXCCODE_SYS << CAUSEB_EXCCODE));
1762
1763 /* Set PC to the exception entry point */
1764 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1765
1766 } else {
1767 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
1768 er = EMULATE_FAIL;
1769 }
1770
1771 return er;
1772 }
1773
1774 enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
1775 u32 *opc,
1776 struct kvm_run *run,
1777 struct kvm_vcpu *vcpu)
1778 {
1779 struct mips_coproc *cop0 = vcpu->arch.cop0;
1780 struct kvm_vcpu_arch *arch = &vcpu->arch;
1781 unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
1782 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1783
1784 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1785 /* save old pc */
1786 kvm_write_c0_guest_epc(cop0, arch->pc);
1787 kvm_set_c0_guest_status(cop0, ST0_EXL);
1788
1789 if (cause & CAUSEF_BD)
1790 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1791 else
1792 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1793
1794 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
1795 arch->pc);
1796
1797 /* set pc to the exception entry point */
1798 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1799
1800 } else {
1801 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1802 arch->pc);
1803
1804 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1805 }
1806
1807 kvm_change_c0_guest_cause(cop0, (0xff),
1808 (EXCCODE_TLBL << CAUSEB_EXCCODE));
1809
1810 /* setup badvaddr, context and entryhi registers for the guest */
1811 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1812 /* XXXKYMA: is the context register used by linux??? */
1813 kvm_write_c0_guest_entryhi(cop0, entryhi);
1814 /* Blow away the shadow host TLBs */
1815 kvm_mips_flush_host_tlb(1);
1816
1817 return EMULATE_DONE;
1818 }
1819
1820 enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
1821 u32 *opc,
1822 struct kvm_run *run,
1823 struct kvm_vcpu *vcpu)
1824 {
1825 struct mips_coproc *cop0 = vcpu->arch.cop0;
1826 struct kvm_vcpu_arch *arch = &vcpu->arch;
1827 unsigned long entryhi =
1828 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1829 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1830
1831 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1832 /* save old pc */
1833 kvm_write_c0_guest_epc(cop0, arch->pc);
1834 kvm_set_c0_guest_status(cop0, ST0_EXL);
1835
1836 if (cause & CAUSEF_BD)
1837 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1838 else
1839 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1840
1841 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
1842 arch->pc);
1843
1844 /* set pc to the exception entry point */
1845 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1846
1847 } else {
1848 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1849 arch->pc);
1850 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1851 }
1852
1853 kvm_change_c0_guest_cause(cop0, (0xff),
1854 (EXCCODE_TLBL << CAUSEB_EXCCODE));
1855
1856 /* setup badvaddr, context and entryhi registers for the guest */
1857 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1858 /* XXXKYMA: is the context register used by linux??? */
1859 kvm_write_c0_guest_entryhi(cop0, entryhi);
1860 /* Blow away the shadow host TLBs */
1861 kvm_mips_flush_host_tlb(1);
1862
1863 return EMULATE_DONE;
1864 }
1865
1866 enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
1867 u32 *opc,
1868 struct kvm_run *run,
1869 struct kvm_vcpu *vcpu)
1870 {
1871 struct mips_coproc *cop0 = vcpu->arch.cop0;
1872 struct kvm_vcpu_arch *arch = &vcpu->arch;
1873 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1874 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1875
1876 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1877 /* save old pc */
1878 kvm_write_c0_guest_epc(cop0, arch->pc);
1879 kvm_set_c0_guest_status(cop0, ST0_EXL);
1880
1881 if (cause & CAUSEF_BD)
1882 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1883 else
1884 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1885
1886 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1887 arch->pc);
1888
1889 /* Set PC to the exception entry point */
1890 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1891 } else {
1892 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1893 arch->pc);
1894 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1895 }
1896
1897 kvm_change_c0_guest_cause(cop0, (0xff),
1898 (EXCCODE_TLBS << CAUSEB_EXCCODE));
1899
1900 /* setup badvaddr, context and entryhi registers for the guest */
1901 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1902 /* XXXKYMA: is the context register used by linux??? */
1903 kvm_write_c0_guest_entryhi(cop0, entryhi);
1904 /* Blow away the shadow host TLBs */
1905 kvm_mips_flush_host_tlb(1);
1906
1907 return EMULATE_DONE;
1908 }
1909
1910 enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
1911 u32 *opc,
1912 struct kvm_run *run,
1913 struct kvm_vcpu *vcpu)
1914 {
1915 struct mips_coproc *cop0 = vcpu->arch.cop0;
1916 struct kvm_vcpu_arch *arch = &vcpu->arch;
1917 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1918 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1919
1920 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1921 /* save old pc */
1922 kvm_write_c0_guest_epc(cop0, arch->pc);
1923 kvm_set_c0_guest_status(cop0, ST0_EXL);
1924
1925 if (cause & CAUSEF_BD)
1926 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1927 else
1928 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1929
1930 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1931 arch->pc);
1932
1933 /* Set PC to the exception entry point */
1934 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1935 } else {
1936 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1937 arch->pc);
1938 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1939 }
1940
1941 kvm_change_c0_guest_cause(cop0, (0xff),
1942 (EXCCODE_TLBS << CAUSEB_EXCCODE));
1943
1944 /* setup badvaddr, context and entryhi registers for the guest */
1945 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1946 /* XXXKYMA: is the context register used by linux??? */
1947 kvm_write_c0_guest_entryhi(cop0, entryhi);
1948 /* Blow away the shadow host TLBs */
1949 kvm_mips_flush_host_tlb(1);
1950
1951 return EMULATE_DONE;
1952 }
1953
1954 /* TLBMOD: store into address matching TLB with Dirty bit off */
1955 enum emulation_result kvm_mips_handle_tlbmod(u32 cause, u32 *opc,
1956 struct kvm_run *run,
1957 struct kvm_vcpu *vcpu)
1958 {
1959 enum emulation_result er = EMULATE_DONE;
1960 #ifdef DEBUG
1961 struct mips_coproc *cop0 = vcpu->arch.cop0;
1962 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1963 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1964 int index;
1965
1966 /* If address not in the guest TLB, then we are in trouble */
1967 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
1968 if (index < 0) {
1969 /* XXXKYMA Invalidate and retry */
1970 kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
1971 kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
1972 __func__, entryhi);
1973 kvm_mips_dump_guest_tlbs(vcpu);
1974 kvm_mips_dump_host_tlbs();
1975 return EMULATE_FAIL;
1976 }
1977 #endif
1978
1979 er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
1980 return er;
1981 }
1982
1983 enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
1984 u32 *opc,
1985 struct kvm_run *run,
1986 struct kvm_vcpu *vcpu)
1987 {
1988 struct mips_coproc *cop0 = vcpu->arch.cop0;
1989 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1990 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1991 struct kvm_vcpu_arch *arch = &vcpu->arch;
1992
1993 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1994 /* save old pc */
1995 kvm_write_c0_guest_epc(cop0, arch->pc);
1996 kvm_set_c0_guest_status(cop0, ST0_EXL);
1997
1998 if (cause & CAUSEF_BD)
1999 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2000 else
2001 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2002
2003 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
2004 arch->pc);
2005
2006 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2007 } else {
2008 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
2009 arch->pc);
2010 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2011 }
2012
2013 kvm_change_c0_guest_cause(cop0, (0xff),
2014 (EXCCODE_MOD << CAUSEB_EXCCODE));
2015
2016 /* setup badvaddr, context and entryhi registers for the guest */
2017 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2018 /* XXXKYMA: is the context register used by linux??? */
2019 kvm_write_c0_guest_entryhi(cop0, entryhi);
2020 /* Blow away the shadow host TLBs */
2021 kvm_mips_flush_host_tlb(1);
2022
2023 return EMULATE_DONE;
2024 }
2025
2026 enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
2027 u32 *opc,
2028 struct kvm_run *run,
2029 struct kvm_vcpu *vcpu)
2030 {
2031 struct mips_coproc *cop0 = vcpu->arch.cop0;
2032 struct kvm_vcpu_arch *arch = &vcpu->arch;
2033
2034 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2035 /* save old pc */
2036 kvm_write_c0_guest_epc(cop0, arch->pc);
2037 kvm_set_c0_guest_status(cop0, ST0_EXL);
2038
2039 if (cause & CAUSEF_BD)
2040 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2041 else
2042 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2043
2044 }
2045
2046 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2047
2048 kvm_change_c0_guest_cause(cop0, (0xff),
2049 (EXCCODE_CPU << CAUSEB_EXCCODE));
2050 kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2051
2052 return EMULATE_DONE;
2053 }
2054
2055 enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
2056 u32 *opc,
2057 struct kvm_run *run,
2058 struct kvm_vcpu *vcpu)
2059 {
2060 struct mips_coproc *cop0 = vcpu->arch.cop0;
2061 struct kvm_vcpu_arch *arch = &vcpu->arch;
2062 enum emulation_result er = EMULATE_DONE;
2063
2064 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2065 /* save old pc */
2066 kvm_write_c0_guest_epc(cop0, arch->pc);
2067 kvm_set_c0_guest_status(cop0, ST0_EXL);
2068
2069 if (cause & CAUSEF_BD)
2070 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2071 else
2072 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2073
2074 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2075
2076 kvm_change_c0_guest_cause(cop0, (0xff),
2077 (EXCCODE_RI << CAUSEB_EXCCODE));
2078
2079 /* Set PC to the exception entry point */
2080 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2081
2082 } else {
2083 kvm_err("Trying to deliver RI when EXL is already set\n");
2084 er = EMULATE_FAIL;
2085 }
2086
2087 return er;
2088 }
2089
2090 enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
2091 u32 *opc,
2092 struct kvm_run *run,
2093 struct kvm_vcpu *vcpu)
2094 {
2095 struct mips_coproc *cop0 = vcpu->arch.cop0;
2096 struct kvm_vcpu_arch *arch = &vcpu->arch;
2097 enum emulation_result er = EMULATE_DONE;
2098
2099 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2100 /* save old pc */
2101 kvm_write_c0_guest_epc(cop0, arch->pc);
2102 kvm_set_c0_guest_status(cop0, ST0_EXL);
2103
2104 if (cause & CAUSEF_BD)
2105 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2106 else
2107 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2108
2109 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2110
2111 kvm_change_c0_guest_cause(cop0, (0xff),
2112 (EXCCODE_BP << CAUSEB_EXCCODE));
2113
2114 /* Set PC to the exception entry point */
2115 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2116
2117 } else {
2118 kvm_err("Trying to deliver BP when EXL is already set\n");
2119 er = EMULATE_FAIL;
2120 }
2121
2122 return er;
2123 }
2124
2125 enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
2126 u32 *opc,
2127 struct kvm_run *run,
2128 struct kvm_vcpu *vcpu)
2129 {
2130 struct mips_coproc *cop0 = vcpu->arch.cop0;
2131 struct kvm_vcpu_arch *arch = &vcpu->arch;
2132 enum emulation_result er = EMULATE_DONE;
2133
2134 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2135 /* save old pc */
2136 kvm_write_c0_guest_epc(cop0, arch->pc);
2137 kvm_set_c0_guest_status(cop0, ST0_EXL);
2138
2139 if (cause & CAUSEF_BD)
2140 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2141 else
2142 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2143
2144 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2145
2146 kvm_change_c0_guest_cause(cop0, (0xff),
2147 (EXCCODE_TR << CAUSEB_EXCCODE));
2148
2149 /* Set PC to the exception entry point */
2150 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2151
2152 } else {
2153 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2154 er = EMULATE_FAIL;
2155 }
2156
2157 return er;
2158 }
2159
2160 enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
2161 u32 *opc,
2162 struct kvm_run *run,
2163 struct kvm_vcpu *vcpu)
2164 {
2165 struct mips_coproc *cop0 = vcpu->arch.cop0;
2166 struct kvm_vcpu_arch *arch = &vcpu->arch;
2167 enum emulation_result er = EMULATE_DONE;
2168
2169 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2170 /* save old pc */
2171 kvm_write_c0_guest_epc(cop0, arch->pc);
2172 kvm_set_c0_guest_status(cop0, ST0_EXL);
2173
2174 if (cause & CAUSEF_BD)
2175 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2176 else
2177 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2178
2179 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2180
2181 kvm_change_c0_guest_cause(cop0, (0xff),
2182 (EXCCODE_MSAFPE << CAUSEB_EXCCODE));
2183
2184 /* Set PC to the exception entry point */
2185 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2186
2187 } else {
2188 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2189 er = EMULATE_FAIL;
2190 }
2191
2192 return er;
2193 }
2194
2195 enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
2196 u32 *opc,
2197 struct kvm_run *run,
2198 struct kvm_vcpu *vcpu)
2199 {
2200 struct mips_coproc *cop0 = vcpu->arch.cop0;
2201 struct kvm_vcpu_arch *arch = &vcpu->arch;
2202 enum emulation_result er = EMULATE_DONE;
2203
2204 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2205 /* save old pc */
2206 kvm_write_c0_guest_epc(cop0, arch->pc);
2207 kvm_set_c0_guest_status(cop0, ST0_EXL);
2208
2209 if (cause & CAUSEF_BD)
2210 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2211 else
2212 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2213
2214 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2215
2216 kvm_change_c0_guest_cause(cop0, (0xff),
2217 (EXCCODE_FPE << CAUSEB_EXCCODE));
2218
2219 /* Set PC to the exception entry point */
2220 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2221
2222 } else {
2223 kvm_err("Trying to deliver FPE when EXL is already set\n");
2224 er = EMULATE_FAIL;
2225 }
2226
2227 return er;
2228 }
2229
2230 enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
2231 u32 *opc,
2232 struct kvm_run *run,
2233 struct kvm_vcpu *vcpu)
2234 {
2235 struct mips_coproc *cop0 = vcpu->arch.cop0;
2236 struct kvm_vcpu_arch *arch = &vcpu->arch;
2237 enum emulation_result er = EMULATE_DONE;
2238
2239 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2240 /* save old pc */
2241 kvm_write_c0_guest_epc(cop0, arch->pc);
2242 kvm_set_c0_guest_status(cop0, ST0_EXL);
2243
2244 if (cause & CAUSEF_BD)
2245 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2246 else
2247 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2248
2249 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2250
2251 kvm_change_c0_guest_cause(cop0, (0xff),
2252 (EXCCODE_MSADIS << CAUSEB_EXCCODE));
2253
2254 /* Set PC to the exception entry point */
2255 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2256
2257 } else {
2258 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2259 er = EMULATE_FAIL;
2260 }
2261
2262 return er;
2263 }
2264
2265 /* ll/sc, rdhwr, sync emulation */
2266
2267 #define OPCODE 0xfc000000
2268 #define BASE 0x03e00000
2269 #define RT 0x001f0000
2270 #define OFFSET 0x0000ffff
2271 #define LL 0xc0000000
2272 #define SC 0xe0000000
2273 #define SPEC0 0x00000000
2274 #define SPEC3 0x7c000000
2275 #define RD 0x0000f800
2276 #define FUNC 0x0000003f
2277 #define SYNC 0x0000000f
2278 #define RDHWR 0x0000003b
2279
2280 enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
2281 struct kvm_run *run,
2282 struct kvm_vcpu *vcpu)
2283 {
2284 struct mips_coproc *cop0 = vcpu->arch.cop0;
2285 struct kvm_vcpu_arch *arch = &vcpu->arch;
2286 enum emulation_result er = EMULATE_DONE;
2287 unsigned long curr_pc;
2288 u32 inst;
2289
2290 /*
2291 * Update PC and hold onto current PC in case there is
2292 * an error and we want to rollback the PC
2293 */
2294 curr_pc = vcpu->arch.pc;
2295 er = update_pc(vcpu, cause);
2296 if (er == EMULATE_FAIL)
2297 return er;
2298
2299 /* Fetch the instruction. */
2300 if (cause & CAUSEF_BD)
2301 opc += 1;
2302
2303 inst = kvm_get_inst(opc, vcpu);
2304
2305 if (inst == KVM_INVALID_INST) {
2306 kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
2307 return EMULATE_FAIL;
2308 }
2309
2310 if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
2311 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2312 int rd = (inst & RD) >> 11;
2313 int rt = (inst & RT) >> 16;
2314 int sel = (inst >> 6) & 0x7;
2315
2316 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2317 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2318 kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2319 rd, opc);
2320 goto emulate_ri;
2321 }
2322 switch (rd) {
2323 case 0: /* CPU number */
2324 arch->gprs[rt] = 0;
2325 break;
2326 case 1: /* SYNCI length */
2327 arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2328 current_cpu_data.icache.linesz);
2329 break;
2330 case 2: /* Read count register */
2331 arch->gprs[rt] = kvm_mips_read_count(vcpu);
2332 break;
2333 case 3: /* Count register resolution */
2334 switch (current_cpu_data.cputype) {
2335 case CPU_20KC:
2336 case CPU_25KF:
2337 arch->gprs[rt] = 1;
2338 break;
2339 default:
2340 arch->gprs[rt] = 2;
2341 }
2342 break;
2343 case 29:
2344 arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2345 break;
2346
2347 default:
2348 kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2349 goto emulate_ri;
2350 }
2351
2352 trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel),
2353 vcpu->arch.gprs[rt]);
2354 } else {
2355 kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
2356 goto emulate_ri;
2357 }
2358
2359 return EMULATE_DONE;
2360
2361 emulate_ri:
2362 /*
2363 * Rollback PC (if in branch delay slot then the PC already points to
2364 * branch target), and pass the RI exception to the guest OS.
2365 */
2366 vcpu->arch.pc = curr_pc;
2367 return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
2368 }
2369
2370 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
2371 struct kvm_run *run)
2372 {
2373 unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2374 enum emulation_result er = EMULATE_DONE;
2375
2376 if (run->mmio.len > sizeof(*gpr)) {
2377 kvm_err("Bad MMIO length: %d", run->mmio.len);
2378 er = EMULATE_FAIL;
2379 goto done;
2380 }
2381
2382 er = update_pc(vcpu, vcpu->arch.pending_load_cause);
2383 if (er == EMULATE_FAIL)
2384 return er;
2385
2386 switch (run->mmio.len) {
2387 case 4:
2388 *gpr = *(s32 *) run->mmio.data;
2389 break;
2390
2391 case 2:
2392 if (vcpu->mmio_needed == 2)
2393 *gpr = *(s16 *) run->mmio.data;
2394 else
2395 *gpr = *(u16 *)run->mmio.data;
2396
2397 break;
2398 case 1:
2399 if (vcpu->mmio_needed == 2)
2400 *gpr = *(s8 *) run->mmio.data;
2401 else
2402 *gpr = *(u8 *) run->mmio.data;
2403 break;
2404 }
2405
2406 if (vcpu->arch.pending_load_cause & CAUSEF_BD)
2407 kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n",
2408 vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr,
2409 vcpu->mmio_needed);
2410
2411 done:
2412 return er;
2413 }
2414
2415 static enum emulation_result kvm_mips_emulate_exc(u32 cause,
2416 u32 *opc,
2417 struct kvm_run *run,
2418 struct kvm_vcpu *vcpu)
2419 {
2420 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2421 struct mips_coproc *cop0 = vcpu->arch.cop0;
2422 struct kvm_vcpu_arch *arch = &vcpu->arch;
2423 enum emulation_result er = EMULATE_DONE;
2424
2425 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2426 /* save old pc */
2427 kvm_write_c0_guest_epc(cop0, arch->pc);
2428 kvm_set_c0_guest_status(cop0, ST0_EXL);
2429
2430 if (cause & CAUSEF_BD)
2431 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2432 else
2433 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2434
2435 kvm_change_c0_guest_cause(cop0, (0xff),
2436 (exccode << CAUSEB_EXCCODE));
2437
2438 /* Set PC to the exception entry point */
2439 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2440 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2441
2442 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
2443 exccode, kvm_read_c0_guest_epc(cop0),
2444 kvm_read_c0_guest_badvaddr(cop0));
2445 } else {
2446 kvm_err("Trying to deliver EXC when EXL is already set\n");
2447 er = EMULATE_FAIL;
2448 }
2449
2450 return er;
2451 }
2452
2453 enum emulation_result kvm_mips_check_privilege(u32 cause,
2454 u32 *opc,
2455 struct kvm_run *run,
2456 struct kvm_vcpu *vcpu)
2457 {
2458 enum emulation_result er = EMULATE_DONE;
2459 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2460 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
2461
2462 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2463
2464 if (usermode) {
2465 switch (exccode) {
2466 case EXCCODE_INT:
2467 case EXCCODE_SYS:
2468 case EXCCODE_BP:
2469 case EXCCODE_RI:
2470 case EXCCODE_TR:
2471 case EXCCODE_MSAFPE:
2472 case EXCCODE_FPE:
2473 case EXCCODE_MSADIS:
2474 break;
2475
2476 case EXCCODE_CPU:
2477 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
2478 er = EMULATE_PRIV_FAIL;
2479 break;
2480
2481 case EXCCODE_MOD:
2482 break;
2483
2484 case EXCCODE_TLBL:
2485 /*
2486 * We we are accessing Guest kernel space, then send an
2487 * address error exception to the guest
2488 */
2489 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2490 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
2491 badvaddr);
2492 cause &= ~0xff;
2493 cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE);
2494 er = EMULATE_PRIV_FAIL;
2495 }
2496 break;
2497
2498 case EXCCODE_TLBS:
2499 /*
2500 * We we are accessing Guest kernel space, then send an
2501 * address error exception to the guest
2502 */
2503 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2504 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
2505 badvaddr);
2506 cause &= ~0xff;
2507 cause |= (EXCCODE_ADES << CAUSEB_EXCCODE);
2508 er = EMULATE_PRIV_FAIL;
2509 }
2510 break;
2511
2512 case EXCCODE_ADES:
2513 kvm_debug("%s: address error ST @ %#lx\n", __func__,
2514 badvaddr);
2515 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2516 cause &= ~0xff;
2517 cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE);
2518 }
2519 er = EMULATE_PRIV_FAIL;
2520 break;
2521 case EXCCODE_ADEL:
2522 kvm_debug("%s: address error LD @ %#lx\n", __func__,
2523 badvaddr);
2524 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2525 cause &= ~0xff;
2526 cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE);
2527 }
2528 er = EMULATE_PRIV_FAIL;
2529 break;
2530 default:
2531 er = EMULATE_PRIV_FAIL;
2532 break;
2533 }
2534 }
2535
2536 if (er == EMULATE_PRIV_FAIL)
2537 kvm_mips_emulate_exc(cause, opc, run, vcpu);
2538
2539 return er;
2540 }
2541
2542 /*
2543 * User Address (UA) fault, this could happen if
2544 * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
2545 * case we pass on the fault to the guest kernel and let it handle it.
2546 * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
2547 * case we inject the TLB from the Guest TLB into the shadow host TLB
2548 */
2549 enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
2550 u32 *opc,
2551 struct kvm_run *run,
2552 struct kvm_vcpu *vcpu)
2553 {
2554 enum emulation_result er = EMULATE_DONE;
2555 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2556 unsigned long va = vcpu->arch.host_cp0_badvaddr;
2557 int index;
2558
2559 kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n",
2560 vcpu->arch.host_cp0_badvaddr);
2561
2562 /*
2563 * KVM would not have got the exception if this entry was valid in the
2564 * shadow host TLB. Check the Guest TLB, if the entry is not there then
2565 * send the guest an exception. The guest exc handler should then inject
2566 * an entry into the guest TLB.
2567 */
2568 index = kvm_mips_guest_tlb_lookup(vcpu,
2569 (va & VPN2_MASK) |
2570 (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) &
2571 KVM_ENTRYHI_ASID));
2572 if (index < 0) {
2573 if (exccode == EXCCODE_TLBL) {
2574 er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
2575 } else if (exccode == EXCCODE_TLBS) {
2576 er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
2577 } else {
2578 kvm_err("%s: invalid exc code: %d\n", __func__,
2579 exccode);
2580 er = EMULATE_FAIL;
2581 }
2582 } else {
2583 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
2584
2585 /*
2586 * Check if the entry is valid, if not then setup a TLB invalid
2587 * exception to the guest
2588 */
2589 if (!TLB_IS_VALID(*tlb, va)) {
2590 if (exccode == EXCCODE_TLBL) {
2591 er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
2592 vcpu);
2593 } else if (exccode == EXCCODE_TLBS) {
2594 er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
2595 vcpu);
2596 } else {
2597 kvm_err("%s: invalid exc code: %d\n", __func__,
2598 exccode);
2599 er = EMULATE_FAIL;
2600 }
2601 } else {
2602 kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
2603 tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]);
2604 /*
2605 * OK we have a Guest TLB entry, now inject it into the
2606 * shadow host TLB
2607 */
2608 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb);
2609 }
2610 }
2611
2612 return er;
2613 }
Linux kernel - Deliverables
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