projects / deliverable / linux.git / blob
? search:


7c76768ff364ed5bfedaf1191a367fbef95c7e32
[deliverable/linux.git] / arch / mips / kvm / mips.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/fs.h>
19 #include <linux/bootmem.h>
20 #include <asm/fpu.h>
21 #include <asm/page.h>
22 #include <asm/cacheflush.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25
26 #include <linux/kvm_host.h>
27
28 #include "interrupt.h"
29 #include "commpage.h"
30
31 #define CREATE_TRACE_POINTS
32 #include "trace.h"
33
34 #ifndef VECTORSPACING
35 #define VECTORSPACING 0x100 /* for EI/VI mode */
36 #endif
37
38 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
39 struct kvm_stats_debugfs_item debugfs_entries[] = {
40 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
41 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
42 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
43 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
44 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
45 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
46 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
47 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
48 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
49 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
50 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
51 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
52 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
53 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
54 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
55 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
56 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
57 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
58 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
59 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
60 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
61 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
62 {NULL}
63 };
64
65 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
66 {
67 int i;
68
69 for_each_possible_cpu(i) {
70 vcpu->arch.guest_kernel_asid[i] = 0;
71 vcpu->arch.guest_user_asid[i] = 0;
72 }
73
74 return 0;
75 }
76
77 /*
78 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
79 * Config7, so we are "runnable" if interrupts are pending
80 */
81 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
82 {
83 return !!(vcpu->arch.pending_exceptions);
84 }
85
86 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
87 {
88 return 1;
89 }
90
91 int kvm_arch_hardware_enable(void)
92 {
93 return 0;
94 }
95
96 int kvm_arch_hardware_setup(void)
97 {
98 return 0;
99 }
100
101 void kvm_arch_check_processor_compat(void *rtn)
102 {
103 *(int *)rtn = 0;
104 }
105
106 static void kvm_mips_init_tlbs(struct kvm *kvm)
107 {
108 unsigned long wired;
109
110 /*
111 * Add a wired entry to the TLB, it is used to map the commpage to
112 * the Guest kernel
113 */
114 wired = read_c0_wired();
115 write_c0_wired(wired + 1);
116 mtc0_tlbw_hazard();
117 kvm->arch.commpage_tlb = wired;
118
119 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
120 kvm->arch.commpage_tlb);
121 }
122
123 static void kvm_mips_init_vm_percpu(void *arg)
124 {
125 struct kvm *kvm = (struct kvm *)arg;
126
127 kvm_mips_init_tlbs(kvm);
128 kvm_mips_callbacks->vm_init(kvm);
129
130 }
131
132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
133 {
134 if (atomic_inc_return(&kvm_mips_instance) == 1) {
135 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
136 __func__);
137 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
138 }
139
140 return 0;
141 }
142
143 void kvm_mips_free_vcpus(struct kvm *kvm)
144 {
145 unsigned int i;
146 struct kvm_vcpu *vcpu;
147
148 /* Put the pages we reserved for the guest pmap */
149 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
150 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
151 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
152 }
153 kfree(kvm->arch.guest_pmap);
154
155 kvm_for_each_vcpu(i, vcpu, kvm) {
156 kvm_arch_vcpu_free(vcpu);
157 }
158
159 mutex_lock(&kvm->lock);
160
161 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
162 kvm->vcpus[i] = NULL;
163
164 atomic_set(&kvm->online_vcpus, 0);
165
166 mutex_unlock(&kvm->lock);
167 }
168
169 static void kvm_mips_uninit_tlbs(void *arg)
170 {
171 /* Restore wired count */
172 write_c0_wired(0);
173 mtc0_tlbw_hazard();
174 /* Clear out all the TLBs */
175 kvm_local_flush_tlb_all();
176 }
177
178 void kvm_arch_destroy_vm(struct kvm *kvm)
179 {
180 kvm_mips_free_vcpus(kvm);
181
182 /* If this is the last instance, restore wired count */
183 if (atomic_dec_return(&kvm_mips_instance) == 0) {
184 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
185 __func__);
186 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
187 }
188 }
189
190 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
191 unsigned long arg)
192 {
193 return -ENOIOCTLCMD;
194 }
195
196 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
197 unsigned long npages)
198 {
199 return 0;
200 }
201
202 int kvm_arch_prepare_memory_region(struct kvm *kvm,
203 struct kvm_memory_slot *memslot,
204 const struct kvm_userspace_memory_region *mem,
205 enum kvm_mr_change change)
206 {
207 return 0;
208 }
209
210 void kvm_arch_commit_memory_region(struct kvm *kvm,
211 const struct kvm_userspace_memory_region *mem,
212 const struct kvm_memory_slot *old,
213 const struct kvm_memory_slot *new,
214 enum kvm_mr_change change)
215 {
216 unsigned long npages = 0;
217 int i;
218
219 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
220 __func__, kvm, mem->slot, mem->guest_phys_addr,
221 mem->memory_size, mem->userspace_addr);
222
223 /* Setup Guest PMAP table */
224 if (!kvm->arch.guest_pmap) {
225 if (mem->slot == 0)
226 npages = mem->memory_size >> PAGE_SHIFT;
227
228 if (npages) {
229 kvm->arch.guest_pmap_npages = npages;
230 kvm->arch.guest_pmap =
231 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
232
233 if (!kvm->arch.guest_pmap) {
234 kvm_err("Failed to allocate guest PMAP\n");
235 return;
236 }
237
238 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
239 npages, kvm->arch.guest_pmap);
240
241 /* Now setup the page table */
242 for (i = 0; i < npages; i++)
243 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
244 }
245 }
246 }
247
248 static inline void dump_handler(const char *symbol, void *start, void *end)
249 {
250 u32 *p;
251
252 pr_debug("LEAF(%s)\n", symbol);
253
254 pr_debug("\t.set push\n");
255 pr_debug("\t.set noreorder\n");
256
257 for (p = start; p < (u32 *)end; ++p)
258 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
259
260 pr_debug("\t.set\tpop\n");
261
262 pr_debug("\tEND(%s)\n", symbol);
263 }
264
265 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
266 {
267 int err, size;
268 void *gebase, *p, *handler;
269 int i;
270
271 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
272
273 if (!vcpu) {
274 err = -ENOMEM;
275 goto out;
276 }
277
278 err = kvm_vcpu_init(vcpu, kvm, id);
279
280 if (err)
281 goto out_free_cpu;
282
283 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
284
285 /*
286 * Allocate space for host mode exception handlers that handle
287 * guest mode exits
288 */
289 if (cpu_has_veic || cpu_has_vint)
290 size = 0x200 + VECTORSPACING * 64;
291 else
292 size = 0x4000;
293
294 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
295
296 if (!gebase) {
297 err = -ENOMEM;
298 goto out_uninit_cpu;
299 }
300 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
301 ALIGN(size, PAGE_SIZE), gebase);
302
303 /* Save new ebase */
304 vcpu->arch.guest_ebase = gebase;
305
306 /* Build guest exception vectors dynamically in unmapped memory */
307 handler = gebase + 0x2000;
308
309 /* TLB Refill, EXL = 0 */
310 kvm_mips_build_exception(gebase, handler);
311
312 /* General Exception Entry point */
313 kvm_mips_build_exception(gebase + 0x180, handler);
314
315 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
316 for (i = 0; i < 8; i++) {
317 kvm_debug("L1 Vectored handler @ %p\n",
318 gebase + 0x200 + (i * VECTORSPACING));
319 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
320 handler);
321 }
322
323 /* General exit handler */
324 p = handler;
325 p = kvm_mips_build_exit(p);
326
327 /* Guest entry routine */
328 vcpu->arch.vcpu_run = p;
329 p = kvm_mips_build_vcpu_run(p);
330
331 /* Dump the generated code */
332 pr_debug("#include <asm/asm.h>\n");
333 pr_debug("#include <asm/regdef.h>\n");
334 pr_debug("\n");
335 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
336 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
337 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
338
339 /* Invalidate the icache for these ranges */
340 local_flush_icache_range((unsigned long)gebase,
341 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
342
343 /*
344 * Allocate comm page for guest kernel, a TLB will be reserved for
345 * mapping GVA @ 0xFFFF8000 to this page
346 */
347 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
348
349 if (!vcpu->arch.kseg0_commpage) {
350 err = -ENOMEM;
351 goto out_free_gebase;
352 }
353
354 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
355 kvm_mips_commpage_init(vcpu);
356
357 /* Init */
358 vcpu->arch.last_sched_cpu = -1;
359
360 /* Start off the timer */
361 kvm_mips_init_count(vcpu);
362
363 return vcpu;
364
365 out_free_gebase:
366 kfree(gebase);
367
368 out_uninit_cpu:
369 kvm_vcpu_uninit(vcpu);
370
371 out_free_cpu:
372 kfree(vcpu);
373
374 out:
375 return ERR_PTR(err);
376 }
377
378 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
379 {
380 hrtimer_cancel(&vcpu->arch.comparecount_timer);
381
382 kvm_vcpu_uninit(vcpu);
383
384 kvm_mips_dump_stats(vcpu);
385
386 kfree(vcpu->arch.guest_ebase);
387 kfree(vcpu->arch.kseg0_commpage);
388 kfree(vcpu);
389 }
390
391 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
392 {
393 kvm_arch_vcpu_free(vcpu);
394 }
395
396 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
397 struct kvm_guest_debug *dbg)
398 {
399 return -ENOIOCTLCMD;
400 }
401
402 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
403 {
404 int r = 0;
405 sigset_t sigsaved;
406
407 if (vcpu->sigset_active)
408 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
409
410 if (vcpu->mmio_needed) {
411 if (!vcpu->mmio_is_write)
412 kvm_mips_complete_mmio_load(vcpu, run);
413 vcpu->mmio_needed = 0;
414 }
415
416 lose_fpu(1);
417
418 local_irq_disable();
419 /* Check if we have any exceptions/interrupts pending */
420 kvm_mips_deliver_interrupts(vcpu,
421 kvm_read_c0_guest_cause(vcpu->arch.cop0));
422
423 guest_enter_irqoff();
424
425 /* Disable hardware page table walking while in guest */
426 htw_stop();
427
428 trace_kvm_enter(vcpu);
429 r = vcpu->arch.vcpu_run(run, vcpu);
430 trace_kvm_out(vcpu);
431
432 /* Re-enable HTW before enabling interrupts */
433 htw_start();
434
435 guest_exit_irqoff();
436 local_irq_enable();
437
438 if (vcpu->sigset_active)
439 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
440
441 return r;
442 }
443
444 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
445 struct kvm_mips_interrupt *irq)
446 {
447 int intr = (int)irq->irq;
448 struct kvm_vcpu *dvcpu = NULL;
449
450 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
451 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
452 (int)intr);
453
454 if (irq->cpu == -1)
455 dvcpu = vcpu;
456 else
457 dvcpu = vcpu->kvm->vcpus[irq->cpu];
458
459 if (intr == 2 || intr == 3 || intr == 4) {
460 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
461
462 } else if (intr == -2 || intr == -3 || intr == -4) {
463 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
464 } else {
465 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
466 irq->cpu, irq->irq);
467 return -EINVAL;
468 }
469
470 dvcpu->arch.wait = 0;
471
472 if (swait_active(&dvcpu->wq))
473 swake_up(&dvcpu->wq);
474
475 return 0;
476 }
477
478 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
479 struct kvm_mp_state *mp_state)
480 {
481 return -ENOIOCTLCMD;
482 }
483
484 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
485 struct kvm_mp_state *mp_state)
486 {
487 return -ENOIOCTLCMD;
488 }
489
490 static u64 kvm_mips_get_one_regs[] = {
491 KVM_REG_MIPS_R0,
492 KVM_REG_MIPS_R1,
493 KVM_REG_MIPS_R2,
494 KVM_REG_MIPS_R3,
495 KVM_REG_MIPS_R4,
496 KVM_REG_MIPS_R5,
497 KVM_REG_MIPS_R6,
498 KVM_REG_MIPS_R7,
499 KVM_REG_MIPS_R8,
500 KVM_REG_MIPS_R9,
501 KVM_REG_MIPS_R10,
502 KVM_REG_MIPS_R11,
503 KVM_REG_MIPS_R12,
504 KVM_REG_MIPS_R13,
505 KVM_REG_MIPS_R14,
506 KVM_REG_MIPS_R15,
507 KVM_REG_MIPS_R16,
508 KVM_REG_MIPS_R17,
509 KVM_REG_MIPS_R18,
510 KVM_REG_MIPS_R19,
511 KVM_REG_MIPS_R20,
512 KVM_REG_MIPS_R21,
513 KVM_REG_MIPS_R22,
514 KVM_REG_MIPS_R23,
515 KVM_REG_MIPS_R24,
516 KVM_REG_MIPS_R25,
517 KVM_REG_MIPS_R26,
518 KVM_REG_MIPS_R27,
519 KVM_REG_MIPS_R28,
520 KVM_REG_MIPS_R29,
521 KVM_REG_MIPS_R30,
522 KVM_REG_MIPS_R31,
523
524 KVM_REG_MIPS_HI,
525 KVM_REG_MIPS_LO,
526 KVM_REG_MIPS_PC,
527
528 KVM_REG_MIPS_CP0_INDEX,
529 KVM_REG_MIPS_CP0_CONTEXT,
530 KVM_REG_MIPS_CP0_USERLOCAL,
531 KVM_REG_MIPS_CP0_PAGEMASK,
532 KVM_REG_MIPS_CP0_WIRED,
533 KVM_REG_MIPS_CP0_HWRENA,
534 KVM_REG_MIPS_CP0_BADVADDR,
535 KVM_REG_MIPS_CP0_COUNT,
536 KVM_REG_MIPS_CP0_ENTRYHI,
537 KVM_REG_MIPS_CP0_COMPARE,
538 KVM_REG_MIPS_CP0_STATUS,
539 KVM_REG_MIPS_CP0_CAUSE,
540 KVM_REG_MIPS_CP0_EPC,
541 KVM_REG_MIPS_CP0_PRID,
542 KVM_REG_MIPS_CP0_CONFIG,
543 KVM_REG_MIPS_CP0_CONFIG1,
544 KVM_REG_MIPS_CP0_CONFIG2,
545 KVM_REG_MIPS_CP0_CONFIG3,
546 KVM_REG_MIPS_CP0_CONFIG4,
547 KVM_REG_MIPS_CP0_CONFIG5,
548 KVM_REG_MIPS_CP0_CONFIG7,
549 KVM_REG_MIPS_CP0_ERROREPC,
550
551 KVM_REG_MIPS_COUNT_CTL,
552 KVM_REG_MIPS_COUNT_RESUME,
553 KVM_REG_MIPS_COUNT_HZ,
554 };
555
556 static u64 kvm_mips_get_one_regs_fpu[] = {
557 KVM_REG_MIPS_FCR_IR,
558 KVM_REG_MIPS_FCR_CSR,
559 };
560
561 static u64 kvm_mips_get_one_regs_msa[] = {
562 KVM_REG_MIPS_MSA_IR,
563 KVM_REG_MIPS_MSA_CSR,
564 };
565
566 static u64 kvm_mips_get_one_regs_kscratch[] = {
567 KVM_REG_MIPS_CP0_KSCRATCH1,
568 KVM_REG_MIPS_CP0_KSCRATCH2,
569 KVM_REG_MIPS_CP0_KSCRATCH3,
570 KVM_REG_MIPS_CP0_KSCRATCH4,
571 KVM_REG_MIPS_CP0_KSCRATCH5,
572 KVM_REG_MIPS_CP0_KSCRATCH6,
573 };
574
575 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
576 {
577 unsigned long ret;
578
579 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
580 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
581 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
582 /* odd doubles */
583 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
584 ret += 16;
585 }
586 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
587 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
588 ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
589 ret += kvm_mips_callbacks->num_regs(vcpu);
590
591 return ret;
592 }
593
594 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
595 {
596 u64 index;
597 unsigned int i;
598
599 if (copy_to_user(indices, kvm_mips_get_one_regs,
600 sizeof(kvm_mips_get_one_regs)))
601 return -EFAULT;
602 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
603
604 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
605 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
606 sizeof(kvm_mips_get_one_regs_fpu)))
607 return -EFAULT;
608 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
609
610 for (i = 0; i < 32; ++i) {
611 index = KVM_REG_MIPS_FPR_32(i);
612 if (copy_to_user(indices, &index, sizeof(index)))
613 return -EFAULT;
614 ++indices;
615
616 /* skip odd doubles if no F64 */
617 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
618 continue;
619
620 index = KVM_REG_MIPS_FPR_64(i);
621 if (copy_to_user(indices, &index, sizeof(index)))
622 return -EFAULT;
623 ++indices;
624 }
625 }
626
627 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
628 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
629 sizeof(kvm_mips_get_one_regs_msa)))
630 return -EFAULT;
631 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
632
633 for (i = 0; i < 32; ++i) {
634 index = KVM_REG_MIPS_VEC_128(i);
635 if (copy_to_user(indices, &index, sizeof(index)))
636 return -EFAULT;
637 ++indices;
638 }
639 }
640
641 for (i = 0; i < 6; ++i) {
642 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
643 continue;
644
645 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
646 sizeof(kvm_mips_get_one_regs_kscratch[i])))
647 return -EFAULT;
648 ++indices;
649 }
650
651 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
652 }
653
654 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
655 const struct kvm_one_reg *reg)
656 {
657 struct mips_coproc *cop0 = vcpu->arch.cop0;
658 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
659 int ret;
660 s64 v;
661 s64 vs[2];
662 unsigned int idx;
663
664 switch (reg->id) {
665 /* General purpose registers */
666 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
667 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
668 break;
669 case KVM_REG_MIPS_HI:
670 v = (long)vcpu->arch.hi;
671 break;
672 case KVM_REG_MIPS_LO:
673 v = (long)vcpu->arch.lo;
674 break;
675 case KVM_REG_MIPS_PC:
676 v = (long)vcpu->arch.pc;
677 break;
678
679 /* Floating point registers */
680 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
681 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
682 return -EINVAL;
683 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
684 /* Odd singles in top of even double when FR=0 */
685 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
686 v = get_fpr32(&fpu->fpr[idx], 0);
687 else
688 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
689 break;
690 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
691 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
692 return -EINVAL;
693 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
694 /* Can't access odd doubles in FR=0 mode */
695 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
696 return -EINVAL;
697 v = get_fpr64(&fpu->fpr[idx], 0);
698 break;
699 case KVM_REG_MIPS_FCR_IR:
700 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
701 return -EINVAL;
702 v = boot_cpu_data.fpu_id;
703 break;
704 case KVM_REG_MIPS_FCR_CSR:
705 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
706 return -EINVAL;
707 v = fpu->fcr31;
708 break;
709
710 /* MIPS SIMD Architecture (MSA) registers */
711 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
712 if (!kvm_mips_guest_has_msa(&vcpu->arch))
713 return -EINVAL;
714 /* Can't access MSA registers in FR=0 mode */
715 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
716 return -EINVAL;
717 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
718 #ifdef CONFIG_CPU_LITTLE_ENDIAN
719 /* least significant byte first */
720 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
721 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
722 #else
723 /* most significant byte first */
724 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
725 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
726 #endif
727 break;
728 case KVM_REG_MIPS_MSA_IR:
729 if (!kvm_mips_guest_has_msa(&vcpu->arch))
730 return -EINVAL;
731 v = boot_cpu_data.msa_id;
732 break;
733 case KVM_REG_MIPS_MSA_CSR:
734 if (!kvm_mips_guest_has_msa(&vcpu->arch))
735 return -EINVAL;
736 v = fpu->msacsr;
737 break;
738
739 /* Co-processor 0 registers */
740 case KVM_REG_MIPS_CP0_INDEX:
741 v = (long)kvm_read_c0_guest_index(cop0);
742 break;
743 case KVM_REG_MIPS_CP0_CONTEXT:
744 v = (long)kvm_read_c0_guest_context(cop0);
745 break;
746 case KVM_REG_MIPS_CP0_USERLOCAL:
747 v = (long)kvm_read_c0_guest_userlocal(cop0);
748 break;
749 case KVM_REG_MIPS_CP0_PAGEMASK:
750 v = (long)kvm_read_c0_guest_pagemask(cop0);
751 break;
752 case KVM_REG_MIPS_CP0_WIRED:
753 v = (long)kvm_read_c0_guest_wired(cop0);
754 break;
755 case KVM_REG_MIPS_CP0_HWRENA:
756 v = (long)kvm_read_c0_guest_hwrena(cop0);
757 break;
758 case KVM_REG_MIPS_CP0_BADVADDR:
759 v = (long)kvm_read_c0_guest_badvaddr(cop0);
760 break;
761 case KVM_REG_MIPS_CP0_ENTRYHI:
762 v = (long)kvm_read_c0_guest_entryhi(cop0);
763 break;
764 case KVM_REG_MIPS_CP0_COMPARE:
765 v = (long)kvm_read_c0_guest_compare(cop0);
766 break;
767 case KVM_REG_MIPS_CP0_STATUS:
768 v = (long)kvm_read_c0_guest_status(cop0);
769 break;
770 case KVM_REG_MIPS_CP0_CAUSE:
771 v = (long)kvm_read_c0_guest_cause(cop0);
772 break;
773 case KVM_REG_MIPS_CP0_EPC:
774 v = (long)kvm_read_c0_guest_epc(cop0);
775 break;
776 case KVM_REG_MIPS_CP0_PRID:
777 v = (long)kvm_read_c0_guest_prid(cop0);
778 break;
779 case KVM_REG_MIPS_CP0_CONFIG:
780 v = (long)kvm_read_c0_guest_config(cop0);
781 break;
782 case KVM_REG_MIPS_CP0_CONFIG1:
783 v = (long)kvm_read_c0_guest_config1(cop0);
784 break;
785 case KVM_REG_MIPS_CP0_CONFIG2:
786 v = (long)kvm_read_c0_guest_config2(cop0);
787 break;
788 case KVM_REG_MIPS_CP0_CONFIG3:
789 v = (long)kvm_read_c0_guest_config3(cop0);
790 break;
791 case KVM_REG_MIPS_CP0_CONFIG4:
792 v = (long)kvm_read_c0_guest_config4(cop0);
793 break;
794 case KVM_REG_MIPS_CP0_CONFIG5:
795 v = (long)kvm_read_c0_guest_config5(cop0);
796 break;
797 case KVM_REG_MIPS_CP0_CONFIG7:
798 v = (long)kvm_read_c0_guest_config7(cop0);
799 break;
800 case KVM_REG_MIPS_CP0_ERROREPC:
801 v = (long)kvm_read_c0_guest_errorepc(cop0);
802 break;
803 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
804 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
805 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
806 return -EINVAL;
807 switch (idx) {
808 case 2:
809 v = (long)kvm_read_c0_guest_kscratch1(cop0);
810 break;
811 case 3:
812 v = (long)kvm_read_c0_guest_kscratch2(cop0);
813 break;
814 case 4:
815 v = (long)kvm_read_c0_guest_kscratch3(cop0);
816 break;
817 case 5:
818 v = (long)kvm_read_c0_guest_kscratch4(cop0);
819 break;
820 case 6:
821 v = (long)kvm_read_c0_guest_kscratch5(cop0);
822 break;
823 case 7:
824 v = (long)kvm_read_c0_guest_kscratch6(cop0);
825 break;
826 }
827 break;
828 /* registers to be handled specially */
829 default:
830 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
831 if (ret)
832 return ret;
833 break;
834 }
835 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
836 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
837
838 return put_user(v, uaddr64);
839 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
840 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
841 u32 v32 = (u32)v;
842
843 return put_user(v32, uaddr32);
844 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
845 void __user *uaddr = (void __user *)(long)reg->addr;
846
847 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
848 } else {
849 return -EINVAL;
850 }
851 }
852
853 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
854 const struct kvm_one_reg *reg)
855 {
856 struct mips_coproc *cop0 = vcpu->arch.cop0;
857 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
858 s64 v;
859 s64 vs[2];
860 unsigned int idx;
861
862 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
863 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
864
865 if (get_user(v, uaddr64) != 0)
866 return -EFAULT;
867 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
868 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
869 s32 v32;
870
871 if (get_user(v32, uaddr32) != 0)
872 return -EFAULT;
873 v = (s64)v32;
874 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
875 void __user *uaddr = (void __user *)(long)reg->addr;
876
877 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
878 } else {
879 return -EINVAL;
880 }
881
882 switch (reg->id) {
883 /* General purpose registers */
884 case KVM_REG_MIPS_R0:
885 /* Silently ignore requests to set $0 */
886 break;
887 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
888 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
889 break;
890 case KVM_REG_MIPS_HI:
891 vcpu->arch.hi = v;
892 break;
893 case KVM_REG_MIPS_LO:
894 vcpu->arch.lo = v;
895 break;
896 case KVM_REG_MIPS_PC:
897 vcpu->arch.pc = v;
898 break;
899
900 /* Floating point registers */
901 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
902 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
903 return -EINVAL;
904 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
905 /* Odd singles in top of even double when FR=0 */
906 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
907 set_fpr32(&fpu->fpr[idx], 0, v);
908 else
909 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
910 break;
911 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
912 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
913 return -EINVAL;
914 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
915 /* Can't access odd doubles in FR=0 mode */
916 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
917 return -EINVAL;
918 set_fpr64(&fpu->fpr[idx], 0, v);
919 break;
920 case KVM_REG_MIPS_FCR_IR:
921 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
922 return -EINVAL;
923 /* Read-only */
924 break;
925 case KVM_REG_MIPS_FCR_CSR:
926 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
927 return -EINVAL;
928 fpu->fcr31 = v;
929 break;
930
931 /* MIPS SIMD Architecture (MSA) registers */
932 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
933 if (!kvm_mips_guest_has_msa(&vcpu->arch))
934 return -EINVAL;
935 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
936 #ifdef CONFIG_CPU_LITTLE_ENDIAN
937 /* least significant byte first */
938 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
939 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
940 #else
941 /* most significant byte first */
942 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
943 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
944 #endif
945 break;
946 case KVM_REG_MIPS_MSA_IR:
947 if (!kvm_mips_guest_has_msa(&vcpu->arch))
948 return -EINVAL;
949 /* Read-only */
950 break;
951 case KVM_REG_MIPS_MSA_CSR:
952 if (!kvm_mips_guest_has_msa(&vcpu->arch))
953 return -EINVAL;
954 fpu->msacsr = v;
955 break;
956
957 /* Co-processor 0 registers */
958 case KVM_REG_MIPS_CP0_INDEX:
959 kvm_write_c0_guest_index(cop0, v);
960 break;
961 case KVM_REG_MIPS_CP0_CONTEXT:
962 kvm_write_c0_guest_context(cop0, v);
963 break;
964 case KVM_REG_MIPS_CP0_USERLOCAL:
965 kvm_write_c0_guest_userlocal(cop0, v);
966 break;
967 case KVM_REG_MIPS_CP0_PAGEMASK:
968 kvm_write_c0_guest_pagemask(cop0, v);
969 break;
970 case KVM_REG_MIPS_CP0_WIRED:
971 kvm_write_c0_guest_wired(cop0, v);
972 break;
973 case KVM_REG_MIPS_CP0_HWRENA:
974 kvm_write_c0_guest_hwrena(cop0, v);
975 break;
976 case KVM_REG_MIPS_CP0_BADVADDR:
977 kvm_write_c0_guest_badvaddr(cop0, v);
978 break;
979 case KVM_REG_MIPS_CP0_ENTRYHI:
980 kvm_write_c0_guest_entryhi(cop0, v);
981 break;
982 case KVM_REG_MIPS_CP0_STATUS:
983 kvm_write_c0_guest_status(cop0, v);
984 break;
985 case KVM_REG_MIPS_CP0_EPC:
986 kvm_write_c0_guest_epc(cop0, v);
987 break;
988 case KVM_REG_MIPS_CP0_PRID:
989 kvm_write_c0_guest_prid(cop0, v);
990 break;
991 case KVM_REG_MIPS_CP0_ERROREPC:
992 kvm_write_c0_guest_errorepc(cop0, v);
993 break;
994 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
995 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
996 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
997 return -EINVAL;
998 switch (idx) {
999 case 2:
1000 kvm_write_c0_guest_kscratch1(cop0, v);
1001 break;
1002 case 3:
1003 kvm_write_c0_guest_kscratch2(cop0, v);
1004 break;
1005 case 4:
1006 kvm_write_c0_guest_kscratch3(cop0, v);
1007 break;
1008 case 5:
1009 kvm_write_c0_guest_kscratch4(cop0, v);
1010 break;
1011 case 6:
1012 kvm_write_c0_guest_kscratch5(cop0, v);
1013 break;
1014 case 7:
1015 kvm_write_c0_guest_kscratch6(cop0, v);
1016 break;
1017 }
1018 break;
1019 /* registers to be handled specially */
1020 default:
1021 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
1022 }
1023 return 0;
1024 }
1025
1026 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1027 struct kvm_enable_cap *cap)
1028 {
1029 int r = 0;
1030
1031 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1032 return -EINVAL;
1033 if (cap->flags)
1034 return -EINVAL;
1035 if (cap->args[0])
1036 return -EINVAL;
1037
1038 switch (cap->cap) {
1039 case KVM_CAP_MIPS_FPU:
1040 vcpu->arch.fpu_enabled = true;
1041 break;
1042 case KVM_CAP_MIPS_MSA:
1043 vcpu->arch.msa_enabled = true;
1044 break;
1045 default:
1046 r = -EINVAL;
1047 break;
1048 }
1049
1050 return r;
1051 }
1052
1053 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1054 unsigned long arg)
1055 {
1056 struct kvm_vcpu *vcpu = filp->private_data;
1057 void __user *argp = (void __user *)arg;
1058 long r;
1059
1060 switch (ioctl) {
1061 case KVM_SET_ONE_REG:
1062 case KVM_GET_ONE_REG: {
1063 struct kvm_one_reg reg;
1064
1065 if (copy_from_user(&reg, argp, sizeof(reg)))
1066 return -EFAULT;
1067 if (ioctl == KVM_SET_ONE_REG)
1068 return kvm_mips_set_reg(vcpu, &reg);
1069 else
1070 return kvm_mips_get_reg(vcpu, &reg);
1071 }
1072 case KVM_GET_REG_LIST: {
1073 struct kvm_reg_list __user *user_list = argp;
1074 struct kvm_reg_list reg_list;
1075 unsigned n;
1076
1077 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1078 return -EFAULT;
1079 n = reg_list.n;
1080 reg_list.n = kvm_mips_num_regs(vcpu);
1081 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1082 return -EFAULT;
1083 if (n < reg_list.n)
1084 return -E2BIG;
1085 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1086 }
1087 case KVM_NMI:
1088 /* Treat the NMI as a CPU reset */
1089 r = kvm_mips_reset_vcpu(vcpu);
1090 break;
1091 case KVM_INTERRUPT:
1092 {
1093 struct kvm_mips_interrupt irq;
1094
1095 r = -EFAULT;
1096 if (copy_from_user(&irq, argp, sizeof(irq)))
1097 goto out;
1098
1099 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1100 irq.irq);
1101
1102 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1103 break;
1104 }
1105 case KVM_ENABLE_CAP: {
1106 struct kvm_enable_cap cap;
1107
1108 r = -EFAULT;
1109 if (copy_from_user(&cap, argp, sizeof(cap)))
1110 goto out;
1111 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1112 break;
1113 }
1114 default:
1115 r = -ENOIOCTLCMD;
1116 }
1117
1118 out:
1119 return r;
1120 }
1121
1122 /* Get (and clear) the dirty memory log for a memory slot. */
1123 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1124 {
1125 struct kvm_memslots *slots;
1126 struct kvm_memory_slot *memslot;
1127 unsigned long ga, ga_end;
1128 int is_dirty = 0;
1129 int r;
1130 unsigned long n;
1131
1132 mutex_lock(&kvm->slots_lock);
1133
1134 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1135 if (r)
1136 goto out;
1137
1138 /* If nothing is dirty, don't bother messing with page tables. */
1139 if (is_dirty) {
1140 slots = kvm_memslots(kvm);
1141 memslot = id_to_memslot(slots, log->slot);
1142
1143 ga = memslot->base_gfn << PAGE_SHIFT;
1144 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1145
1146 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1147 ga_end);
1148
1149 n = kvm_dirty_bitmap_bytes(memslot);
1150 memset(memslot->dirty_bitmap, 0, n);
1151 }
1152
1153 r = 0;
1154 out:
1155 mutex_unlock(&kvm->slots_lock);
1156 return r;
1157
1158 }
1159
1160 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1161 {
1162 long r;
1163
1164 switch (ioctl) {
1165 default:
1166 r = -ENOIOCTLCMD;
1167 }
1168
1169 return r;
1170 }
1171
1172 int kvm_arch_init(void *opaque)
1173 {
1174 if (kvm_mips_callbacks) {
1175 kvm_err("kvm: module already exists\n");
1176 return -EEXIST;
1177 }
1178
1179 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1180 }
1181
1182 void kvm_arch_exit(void)
1183 {
1184 kvm_mips_callbacks = NULL;
1185 }
1186
1187 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1188 struct kvm_sregs *sregs)
1189 {
1190 return -ENOIOCTLCMD;
1191 }
1192
1193 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1194 struct kvm_sregs *sregs)
1195 {
1196 return -ENOIOCTLCMD;
1197 }
1198
1199 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1200 {
1201 }
1202
1203 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1204 {
1205 return -ENOIOCTLCMD;
1206 }
1207
1208 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1209 {
1210 return -ENOIOCTLCMD;
1211 }
1212
1213 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1214 {
1215 return VM_FAULT_SIGBUS;
1216 }
1217
1218 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1219 {
1220 int r;
1221
1222 switch (ext) {
1223 case KVM_CAP_ONE_REG:
1224 case KVM_CAP_ENABLE_CAP:
1225 r = 1;
1226 break;
1227 case KVM_CAP_COALESCED_MMIO:
1228 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1229 break;
1230 case KVM_CAP_MIPS_FPU:
1231 /* We don't handle systems with inconsistent cpu_has_fpu */
1232 r = !!raw_cpu_has_fpu;
1233 break;
1234 case KVM_CAP_MIPS_MSA:
1235 /*
1236 * We don't support MSA vector partitioning yet:
1237 * 1) It would require explicit support which can't be tested
1238 * yet due to lack of support in current hardware.
1239 * 2) It extends the state that would need to be saved/restored
1240 * by e.g. QEMU for migration.
1241 *
1242 * When vector partitioning hardware becomes available, support
1243 * could be added by requiring a flag when enabling
1244 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1245 * to save/restore the appropriate extra state.
1246 */
1247 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1248 break;
1249 default:
1250 r = 0;
1251 break;
1252 }
1253 return r;
1254 }
1255
1256 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1257 {
1258 return kvm_mips_pending_timer(vcpu);
1259 }
1260
1261 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1262 {
1263 int i;
1264 struct mips_coproc *cop0;
1265
1266 if (!vcpu)
1267 return -1;
1268
1269 kvm_debug("VCPU Register Dump:\n");
1270 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1271 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1272
1273 for (i = 0; i < 32; i += 4) {
1274 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1275 vcpu->arch.gprs[i],
1276 vcpu->arch.gprs[i + 1],
1277 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1278 }
1279 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1280 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1281
1282 cop0 = vcpu->arch.cop0;
1283 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1284 kvm_read_c0_guest_status(cop0),
1285 kvm_read_c0_guest_cause(cop0));
1286
1287 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1288
1289 return 0;
1290 }
1291
1292 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1293 {
1294 int i;
1295
1296 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1297 vcpu->arch.gprs[i] = regs->gpr[i];
1298 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1299 vcpu->arch.hi = regs->hi;
1300 vcpu->arch.lo = regs->lo;
1301 vcpu->arch.pc = regs->pc;
1302
1303 return 0;
1304 }
1305
1306 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1307 {
1308 int i;
1309
1310 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1311 regs->gpr[i] = vcpu->arch.gprs[i];
1312
1313 regs->hi = vcpu->arch.hi;
1314 regs->lo = vcpu->arch.lo;
1315 regs->pc = vcpu->arch.pc;
1316
1317 return 0;
1318 }
1319
1320 static void kvm_mips_comparecount_func(unsigned long data)
1321 {
1322 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1323
1324 kvm_mips_callbacks->queue_timer_int(vcpu);
1325
1326 vcpu->arch.wait = 0;
1327 if (swait_active(&vcpu->wq))
1328 swake_up(&vcpu->wq);
1329 }
1330
1331 /* low level hrtimer wake routine */
1332 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1333 {
1334 struct kvm_vcpu *vcpu;
1335
1336 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1337 kvm_mips_comparecount_func((unsigned long) vcpu);
1338 return kvm_mips_count_timeout(vcpu);
1339 }
1340
1341 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1342 {
1343 kvm_mips_callbacks->vcpu_init(vcpu);
1344 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1345 HRTIMER_MODE_REL);
1346 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1347 return 0;
1348 }
1349
1350 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1351 struct kvm_translation *tr)
1352 {
1353 return 0;
1354 }
1355
1356 /* Initial guest state */
1357 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1358 {
1359 return kvm_mips_callbacks->vcpu_setup(vcpu);
1360 }
1361
1362 static void kvm_mips_set_c0_status(void)
1363 {
1364 u32 status = read_c0_status();
1365
1366 if (cpu_has_dsp)
1367 status |= (ST0_MX);
1368
1369 write_c0_status(status);
1370 ehb();
1371 }
1372
1373 /*
1374 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1375 */
1376 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1377 {
1378 u32 cause = vcpu->arch.host_cp0_cause;
1379 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1380 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1381 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1382 enum emulation_result er = EMULATE_DONE;
1383 int ret = RESUME_GUEST;
1384
1385 /* re-enable HTW before enabling interrupts */
1386 htw_start();
1387
1388 /* Set a default exit reason */
1389 run->exit_reason = KVM_EXIT_UNKNOWN;
1390 run->ready_for_interrupt_injection = 1;
1391
1392 /*
1393 * Set the appropriate status bits based on host CPU features,
1394 * before we hit the scheduler
1395 */
1396 kvm_mips_set_c0_status();
1397
1398 local_irq_enable();
1399
1400 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1401 cause, opc, run, vcpu);
1402 trace_kvm_exit(vcpu, exccode);
1403
1404 /*
1405 * Do a privilege check, if in UM most of these exit conditions end up
1406 * causing an exception to be delivered to the Guest Kernel
1407 */
1408 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1409 if (er == EMULATE_PRIV_FAIL) {
1410 goto skip_emul;
1411 } else if (er == EMULATE_FAIL) {
1412 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1413 ret = RESUME_HOST;
1414 goto skip_emul;
1415 }
1416
1417 switch (exccode) {
1418 case EXCCODE_INT:
1419 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1420
1421 ++vcpu->stat.int_exits;
1422
1423 if (need_resched())
1424 cond_resched();
1425
1426 ret = RESUME_GUEST;
1427 break;
1428
1429 case EXCCODE_CPU:
1430 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1431
1432 ++vcpu->stat.cop_unusable_exits;
1433 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1434 /* XXXKYMA: Might need to return to user space */
1435 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1436 ret = RESUME_HOST;
1437 break;
1438
1439 case EXCCODE_MOD:
1440 ++vcpu->stat.tlbmod_exits;
1441 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1442 break;
1443
1444 case EXCCODE_TLBS:
1445 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1446 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1447 badvaddr);
1448
1449 ++vcpu->stat.tlbmiss_st_exits;
1450 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1451 break;
1452
1453 case EXCCODE_TLBL:
1454 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1455 cause, opc, badvaddr);
1456
1457 ++vcpu->stat.tlbmiss_ld_exits;
1458 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1459 break;
1460
1461 case EXCCODE_ADES:
1462 ++vcpu->stat.addrerr_st_exits;
1463 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1464 break;
1465
1466 case EXCCODE_ADEL:
1467 ++vcpu->stat.addrerr_ld_exits;
1468 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1469 break;
1470
1471 case EXCCODE_SYS:
1472 ++vcpu->stat.syscall_exits;
1473 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1474 break;
1475
1476 case EXCCODE_RI:
1477 ++vcpu->stat.resvd_inst_exits;
1478 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1479 break;
1480
1481 case EXCCODE_BP:
1482 ++vcpu->stat.break_inst_exits;
1483 ret = kvm_mips_callbacks->handle_break(vcpu);
1484 break;
1485
1486 case EXCCODE_TR:
1487 ++vcpu->stat.trap_inst_exits;
1488 ret = kvm_mips_callbacks->handle_trap(vcpu);
1489 break;
1490
1491 case EXCCODE_MSAFPE:
1492 ++vcpu->stat.msa_fpe_exits;
1493 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1494 break;
1495
1496 case EXCCODE_FPE:
1497 ++vcpu->stat.fpe_exits;
1498 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1499 break;
1500
1501 case EXCCODE_MSADIS:
1502 ++vcpu->stat.msa_disabled_exits;
1503 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1504 break;
1505
1506 default:
1507 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1508 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1509 kvm_read_c0_guest_status(vcpu->arch.cop0));
1510 kvm_arch_vcpu_dump_regs(vcpu);
1511 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1512 ret = RESUME_HOST;
1513 break;
1514
1515 }
1516
1517 skip_emul:
1518 local_irq_disable();
1519
1520 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1521 kvm_mips_deliver_interrupts(vcpu, cause);
1522
1523 if (!(ret & RESUME_HOST)) {
1524 /* Only check for signals if not already exiting to userspace */
1525 if (signal_pending(current)) {
1526 run->exit_reason = KVM_EXIT_INTR;
1527 ret = (-EINTR << 2) | RESUME_HOST;
1528 ++vcpu->stat.signal_exits;
1529 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1530 }
1531 }
1532
1533 if (ret == RESUME_GUEST) {
1534 trace_kvm_reenter(vcpu);
1535
1536 /*
1537 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1538 * is live), restore FCR31 / MSACSR.
1539 *
1540 * This should be before returning to the guest exception
1541 * vector, as it may well cause an [MSA] FP exception if there
1542 * are pending exception bits unmasked. (see
1543 * kvm_mips_csr_die_notifier() for how that is handled).
1544 */
1545 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1546 read_c0_status() & ST0_CU1)
1547 __kvm_restore_fcsr(&vcpu->arch);
1548
1549 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1550 read_c0_config5() & MIPS_CONF5_MSAEN)
1551 __kvm_restore_msacsr(&vcpu->arch);
1552 }
1553
1554 /* Disable HTW before returning to guest or host */
1555 htw_stop();
1556
1557 return ret;
1558 }
1559
1560 /* Enable FPU for guest and restore context */
1561 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1562 {
1563 struct mips_coproc *cop0 = vcpu->arch.cop0;
1564 unsigned int sr, cfg5;
1565
1566 preempt_disable();
1567
1568 sr = kvm_read_c0_guest_status(cop0);
1569
1570 /*
1571 * If MSA state is already live, it is undefined how it interacts with
1572 * FR=0 FPU state, and we don't want to hit reserved instruction
1573 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1574 * play it safe and save it first.
1575 *
1576 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1577 * get called when guest CU1 is set, however we can't trust the guest
1578 * not to clobber the status register directly via the commpage.
1579 */
1580 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1581 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1582 kvm_lose_fpu(vcpu);
1583
1584 /*
1585 * Enable FPU for guest
1586 * We set FR and FRE according to guest context
1587 */
1588 change_c0_status(ST0_CU1 | ST0_FR, sr);
1589 if (cpu_has_fre) {
1590 cfg5 = kvm_read_c0_guest_config5(cop0);
1591 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1592 }
1593 enable_fpu_hazard();
1594
1595 /* If guest FPU state not active, restore it now */
1596 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1597 __kvm_restore_fpu(&vcpu->arch);
1598 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1599 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1600 } else {
1601 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1602 }
1603
1604 preempt_enable();
1605 }
1606
1607 #ifdef CONFIG_CPU_HAS_MSA
1608 /* Enable MSA for guest and restore context */
1609 void kvm_own_msa(struct kvm_vcpu *vcpu)
1610 {
1611 struct mips_coproc *cop0 = vcpu->arch.cop0;
1612 unsigned int sr, cfg5;
1613
1614 preempt_disable();
1615
1616 /*
1617 * Enable FPU if enabled in guest, since we're restoring FPU context
1618 * anyway. We set FR and FRE according to guest context.
1619 */
1620 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1621 sr = kvm_read_c0_guest_status(cop0);
1622
1623 /*
1624 * If FR=0 FPU state is already live, it is undefined how it
1625 * interacts with MSA state, so play it safe and save it first.
1626 */
1627 if (!(sr & ST0_FR) &&
1628 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1629 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1630 kvm_lose_fpu(vcpu);
1631
1632 change_c0_status(ST0_CU1 | ST0_FR, sr);
1633 if (sr & ST0_CU1 && cpu_has_fre) {
1634 cfg5 = kvm_read_c0_guest_config5(cop0);
1635 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1636 }
1637 }
1638
1639 /* Enable MSA for guest */
1640 set_c0_config5(MIPS_CONF5_MSAEN);
1641 enable_fpu_hazard();
1642
1643 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1644 case KVM_MIPS_AUX_FPU:
1645 /*
1646 * Guest FPU state already loaded, only restore upper MSA state
1647 */
1648 __kvm_restore_msa_upper(&vcpu->arch);
1649 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1650 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1651 break;
1652 case 0:
1653 /* Neither FPU or MSA already active, restore full MSA state */
1654 __kvm_restore_msa(&vcpu->arch);
1655 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1656 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1657 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1658 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1659 KVM_TRACE_AUX_FPU_MSA);
1660 break;
1661 default:
1662 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1663 break;
1664 }
1665
1666 preempt_enable();
1667 }
1668 #endif
1669
1670 /* Drop FPU & MSA without saving it */
1671 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1672 {
1673 preempt_disable();
1674 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1675 disable_msa();
1676 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1677 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1678 }
1679 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1680 clear_c0_status(ST0_CU1 | ST0_FR);
1681 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1682 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1683 }
1684 preempt_enable();
1685 }
1686
1687 /* Save and disable FPU & MSA */
1688 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1689 {
1690 /*
1691 * FPU & MSA get disabled in root context (hardware) when it is disabled
1692 * in guest context (software), but the register state in the hardware
1693 * may still be in use. This is why we explicitly re-enable the hardware
1694 * before saving.
1695 */
1696
1697 preempt_disable();
1698 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1699 set_c0_config5(MIPS_CONF5_MSAEN);
1700 enable_fpu_hazard();
1701
1702 __kvm_save_msa(&vcpu->arch);
1703 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1704
1705 /* Disable MSA & FPU */
1706 disable_msa();
1707 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1708 clear_c0_status(ST0_CU1 | ST0_FR);
1709 disable_fpu_hazard();
1710 }
1711 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1712 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1713 set_c0_status(ST0_CU1);
1714 enable_fpu_hazard();
1715
1716 __kvm_save_fpu(&vcpu->arch);
1717 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1718 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1719
1720 /* Disable FPU */
1721 clear_c0_status(ST0_CU1 | ST0_FR);
1722 disable_fpu_hazard();
1723 }
1724 preempt_enable();
1725 }
1726
1727 /*
1728 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1729 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1730 * exception if cause bits are set in the value being written.
1731 */
1732 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1733 unsigned long cmd, void *ptr)
1734 {
1735 struct die_args *args = (struct die_args *)ptr;
1736 struct pt_regs *regs = args->regs;
1737 unsigned long pc;
1738
1739 /* Only interested in FPE and MSAFPE */
1740 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1741 return NOTIFY_DONE;
1742
1743 /* Return immediately if guest context isn't active */
1744 if (!(current->flags & PF_VCPU))
1745 return NOTIFY_DONE;
1746
1747 /* Should never get here from user mode */
1748 BUG_ON(user_mode(regs));
1749
1750 pc = instruction_pointer(regs);
1751 switch (cmd) {
1752 case DIE_FP:
1753 /* match 2nd instruction in __kvm_restore_fcsr */
1754 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1755 return NOTIFY_DONE;
1756 break;
1757 case DIE_MSAFP:
1758 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1759 if (!cpu_has_msa ||
1760 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1761 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1762 return NOTIFY_DONE;
1763 break;
1764 }
1765
1766 /* Move PC forward a little and continue executing */
1767 instruction_pointer(regs) += 4;
1768
1769 return NOTIFY_STOP;
1770 }
1771
1772 static struct notifier_block kvm_mips_csr_die_notifier = {
1773 .notifier_call = kvm_mips_csr_die_notify,
1774 };
1775
1776 static int __init kvm_mips_init(void)
1777 {
1778 int ret;
1779
1780 ret = kvm_mips_entry_setup();
1781 if (ret)
1782 return ret;
1783
1784 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1785
1786 if (ret)
1787 return ret;
1788
1789 register_die_notifier(&kvm_mips_csr_die_notifier);
1790
1791 return 0;
1792 }
1793
1794 static void __exit kvm_mips_exit(void)
1795 {
1796 kvm_exit();
1797
1798 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1799 }
1800
1801 module_init(kvm_mips_init);
1802 module_exit(kvm_mips_exit);
1803
1804 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
This page took 0.162967 seconds and 4 git commands to generate.