2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kdebug.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
18 #include <linux/bootmem.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
23 #include <asm/pgtable.h>
25 #include <linux/kvm_host.h>
27 #include "interrupt.h"
30 #define CREATE_TRACE_POINTS
34 #define VECTORSPACING 0x100 /* for EI/VI mode */
37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
38 struct kvm_stats_debugfs_item debugfs_entries
[] = {
39 { "wait", VCPU_STAT(wait_exits
), KVM_STAT_VCPU
},
40 { "cache", VCPU_STAT(cache_exits
), KVM_STAT_VCPU
},
41 { "signal", VCPU_STAT(signal_exits
), KVM_STAT_VCPU
},
42 { "interrupt", VCPU_STAT(int_exits
), KVM_STAT_VCPU
},
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits
), KVM_STAT_VCPU
},
44 { "tlbmod", VCPU_STAT(tlbmod_exits
), KVM_STAT_VCPU
},
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits
), KVM_STAT_VCPU
},
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits
), KVM_STAT_VCPU
},
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits
), KVM_STAT_VCPU
},
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits
), KVM_STAT_VCPU
},
49 { "syscall", VCPU_STAT(syscall_exits
), KVM_STAT_VCPU
},
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits
), KVM_STAT_VCPU
},
51 { "break_inst", VCPU_STAT(break_inst_exits
), KVM_STAT_VCPU
},
52 { "trap_inst", VCPU_STAT(trap_inst_exits
), KVM_STAT_VCPU
},
53 { "msa_fpe", VCPU_STAT(msa_fpe_exits
), KVM_STAT_VCPU
},
54 { "fpe", VCPU_STAT(fpe_exits
), KVM_STAT_VCPU
},
55 { "msa_disabled", VCPU_STAT(msa_disabled_exits
), KVM_STAT_VCPU
},
56 { "flush_dcache", VCPU_STAT(flush_dcache_exits
), KVM_STAT_VCPU
},
57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll
), KVM_STAT_VCPU
},
58 { "halt_wakeup", VCPU_STAT(halt_wakeup
), KVM_STAT_VCPU
},
62 static int kvm_mips_reset_vcpu(struct kvm_vcpu
*vcpu
)
66 for_each_possible_cpu(i
) {
67 vcpu
->arch
.guest_kernel_asid
[i
] = 0;
68 vcpu
->arch
.guest_user_asid
[i
] = 0;
75 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
76 * Config7, so we are "runnable" if interrupts are pending
78 int kvm_arch_vcpu_runnable(struct kvm_vcpu
*vcpu
)
80 return !!(vcpu
->arch
.pending_exceptions
);
83 int kvm_arch_vcpu_should_kick(struct kvm_vcpu
*vcpu
)
88 int kvm_arch_hardware_enable(void)
93 int kvm_arch_hardware_setup(void)
98 void kvm_arch_check_processor_compat(void *rtn
)
103 static void kvm_mips_init_tlbs(struct kvm
*kvm
)
108 * Add a wired entry to the TLB, it is used to map the commpage to
111 wired
= read_c0_wired();
112 write_c0_wired(wired
+ 1);
114 kvm
->arch
.commpage_tlb
= wired
;
116 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
117 kvm
->arch
.commpage_tlb
);
120 static void kvm_mips_init_vm_percpu(void *arg
)
122 struct kvm
*kvm
= (struct kvm
*)arg
;
124 kvm_mips_init_tlbs(kvm
);
125 kvm_mips_callbacks
->vm_init(kvm
);
129 int kvm_arch_init_vm(struct kvm
*kvm
, unsigned long type
)
131 if (atomic_inc_return(&kvm_mips_instance
) == 1) {
132 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
134 on_each_cpu(kvm_mips_init_vm_percpu
, kvm
, 1);
140 void kvm_mips_free_vcpus(struct kvm
*kvm
)
143 struct kvm_vcpu
*vcpu
;
145 /* Put the pages we reserved for the guest pmap */
146 for (i
= 0; i
< kvm
->arch
.guest_pmap_npages
; i
++) {
147 if (kvm
->arch
.guest_pmap
[i
] != KVM_INVALID_PAGE
)
148 kvm_mips_release_pfn_clean(kvm
->arch
.guest_pmap
[i
]);
150 kfree(kvm
->arch
.guest_pmap
);
152 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
153 kvm_arch_vcpu_free(vcpu
);
156 mutex_lock(&kvm
->lock
);
158 for (i
= 0; i
< atomic_read(&kvm
->online_vcpus
); i
++)
159 kvm
->vcpus
[i
] = NULL
;
161 atomic_set(&kvm
->online_vcpus
, 0);
163 mutex_unlock(&kvm
->lock
);
166 static void kvm_mips_uninit_tlbs(void *arg
)
168 /* Restore wired count */
171 /* Clear out all the TLBs */
172 kvm_local_flush_tlb_all();
175 void kvm_arch_destroy_vm(struct kvm
*kvm
)
177 kvm_mips_free_vcpus(kvm
);
179 /* If this is the last instance, restore wired count */
180 if (atomic_dec_return(&kvm_mips_instance
) == 0) {
181 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
183 on_each_cpu(kvm_mips_uninit_tlbs
, NULL
, 1);
187 long kvm_arch_dev_ioctl(struct file
*filp
, unsigned int ioctl
,
193 int kvm_arch_create_memslot(struct kvm
*kvm
, struct kvm_memory_slot
*slot
,
194 unsigned long npages
)
199 int kvm_arch_prepare_memory_region(struct kvm
*kvm
,
200 struct kvm_memory_slot
*memslot
,
201 struct kvm_userspace_memory_region
*mem
,
202 enum kvm_mr_change change
)
207 void kvm_arch_commit_memory_region(struct kvm
*kvm
,
208 struct kvm_userspace_memory_region
*mem
,
209 const struct kvm_memory_slot
*old
,
210 enum kvm_mr_change change
)
212 unsigned long npages
= 0;
215 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
216 __func__
, kvm
, mem
->slot
, mem
->guest_phys_addr
,
217 mem
->memory_size
, mem
->userspace_addr
);
219 /* Setup Guest PMAP table */
220 if (!kvm
->arch
.guest_pmap
) {
222 npages
= mem
->memory_size
>> PAGE_SHIFT
;
225 kvm
->arch
.guest_pmap_npages
= npages
;
226 kvm
->arch
.guest_pmap
=
227 kzalloc(npages
* sizeof(unsigned long), GFP_KERNEL
);
229 if (!kvm
->arch
.guest_pmap
) {
230 kvm_err("Failed to allocate guest PMAP");
234 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
235 npages
, kvm
->arch
.guest_pmap
);
237 /* Now setup the page table */
238 for (i
= 0; i
< npages
; i
++)
239 kvm
->arch
.guest_pmap
[i
] = KVM_INVALID_PAGE
;
244 struct kvm_vcpu
*kvm_arch_vcpu_create(struct kvm
*kvm
, unsigned int id
)
246 int err
, size
, offset
;
250 struct kvm_vcpu
*vcpu
= kzalloc(sizeof(struct kvm_vcpu
), GFP_KERNEL
);
257 err
= kvm_vcpu_init(vcpu
, kvm
, id
);
262 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm
, id
, vcpu
);
265 * Allocate space for host mode exception handlers that handle
268 if (cpu_has_veic
|| cpu_has_vint
)
269 size
= 0x200 + VECTORSPACING
* 64;
273 /* Save Linux EBASE */
274 vcpu
->arch
.host_ebase
= (void *)read_c0_ebase();
276 gebase
= kzalloc(ALIGN(size
, PAGE_SIZE
), GFP_KERNEL
);
282 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
283 ALIGN(size
, PAGE_SIZE
), gebase
);
286 vcpu
->arch
.guest_ebase
= gebase
;
288 /* Copy L1 Guest Exception handler to correct offset */
290 /* TLB Refill, EXL = 0 */
291 memcpy(gebase
, mips32_exception
,
292 mips32_exceptionEnd
- mips32_exception
);
294 /* General Exception Entry point */
295 memcpy(gebase
+ 0x180, mips32_exception
,
296 mips32_exceptionEnd
- mips32_exception
);
298 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
299 for (i
= 0; i
< 8; i
++) {
300 kvm_debug("L1 Vectored handler @ %p\n",
301 gebase
+ 0x200 + (i
* VECTORSPACING
));
302 memcpy(gebase
+ 0x200 + (i
* VECTORSPACING
), mips32_exception
,
303 mips32_exceptionEnd
- mips32_exception
);
306 /* General handler, relocate to unmapped space for sanity's sake */
308 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
310 mips32_GuestExceptionEnd
- mips32_GuestException
);
312 memcpy(gebase
+ offset
, mips32_GuestException
,
313 mips32_GuestExceptionEnd
- mips32_GuestException
);
315 /* Invalidate the icache for these ranges */
316 local_flush_icache_range((unsigned long)gebase
,
317 (unsigned long)gebase
+ ALIGN(size
, PAGE_SIZE
));
320 * Allocate comm page for guest kernel, a TLB will be reserved for
321 * mapping GVA @ 0xFFFF8000 to this page
323 vcpu
->arch
.kseg0_commpage
= kzalloc(PAGE_SIZE
<< 1, GFP_KERNEL
);
325 if (!vcpu
->arch
.kseg0_commpage
) {
327 goto out_free_gebase
;
330 kvm_debug("Allocated COMM page @ %p\n", vcpu
->arch
.kseg0_commpage
);
331 kvm_mips_commpage_init(vcpu
);
334 vcpu
->arch
.last_sched_cpu
= -1;
336 /* Start off the timer */
337 kvm_mips_init_count(vcpu
);
351 void kvm_arch_vcpu_free(struct kvm_vcpu
*vcpu
)
353 hrtimer_cancel(&vcpu
->arch
.comparecount_timer
);
355 kvm_vcpu_uninit(vcpu
);
357 kvm_mips_dump_stats(vcpu
);
359 kfree(vcpu
->arch
.guest_ebase
);
360 kfree(vcpu
->arch
.kseg0_commpage
);
364 void kvm_arch_vcpu_destroy(struct kvm_vcpu
*vcpu
)
366 kvm_arch_vcpu_free(vcpu
);
369 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu
*vcpu
,
370 struct kvm_guest_debug
*dbg
)
375 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
380 if (vcpu
->sigset_active
)
381 sigprocmask(SIG_SETMASK
, &vcpu
->sigset
, &sigsaved
);
383 if (vcpu
->mmio_needed
) {
384 if (!vcpu
->mmio_is_write
)
385 kvm_mips_complete_mmio_load(vcpu
, run
);
386 vcpu
->mmio_needed
= 0;
392 /* Check if we have any exceptions/interrupts pending */
393 kvm_mips_deliver_interrupts(vcpu
,
394 kvm_read_c0_guest_cause(vcpu
->arch
.cop0
));
398 /* Disable hardware page table walking while in guest */
401 r
= __kvm_mips_vcpu_run(run
, vcpu
);
403 /* Re-enable HTW before enabling interrupts */
409 if (vcpu
->sigset_active
)
410 sigprocmask(SIG_SETMASK
, &sigsaved
, NULL
);
415 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu
*vcpu
,
416 struct kvm_mips_interrupt
*irq
)
418 int intr
= (int)irq
->irq
;
419 struct kvm_vcpu
*dvcpu
= NULL
;
421 if (intr
== 3 || intr
== -3 || intr
== 4 || intr
== -4)
422 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__
, irq
->cpu
,
428 dvcpu
= vcpu
->kvm
->vcpus
[irq
->cpu
];
430 if (intr
== 2 || intr
== 3 || intr
== 4) {
431 kvm_mips_callbacks
->queue_io_int(dvcpu
, irq
);
433 } else if (intr
== -2 || intr
== -3 || intr
== -4) {
434 kvm_mips_callbacks
->dequeue_io_int(dvcpu
, irq
);
436 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__
,
441 dvcpu
->arch
.wait
= 0;
443 if (waitqueue_active(&dvcpu
->wq
))
444 wake_up_interruptible(&dvcpu
->wq
);
449 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu
*vcpu
,
450 struct kvm_mp_state
*mp_state
)
455 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu
*vcpu
,
456 struct kvm_mp_state
*mp_state
)
461 static u64 kvm_mips_get_one_regs
[] = {
499 KVM_REG_MIPS_CP0_INDEX
,
500 KVM_REG_MIPS_CP0_CONTEXT
,
501 KVM_REG_MIPS_CP0_USERLOCAL
,
502 KVM_REG_MIPS_CP0_PAGEMASK
,
503 KVM_REG_MIPS_CP0_WIRED
,
504 KVM_REG_MIPS_CP0_HWRENA
,
505 KVM_REG_MIPS_CP0_BADVADDR
,
506 KVM_REG_MIPS_CP0_COUNT
,
507 KVM_REG_MIPS_CP0_ENTRYHI
,
508 KVM_REG_MIPS_CP0_COMPARE
,
509 KVM_REG_MIPS_CP0_STATUS
,
510 KVM_REG_MIPS_CP0_CAUSE
,
511 KVM_REG_MIPS_CP0_EPC
,
512 KVM_REG_MIPS_CP0_PRID
,
513 KVM_REG_MIPS_CP0_CONFIG
,
514 KVM_REG_MIPS_CP0_CONFIG1
,
515 KVM_REG_MIPS_CP0_CONFIG2
,
516 KVM_REG_MIPS_CP0_CONFIG3
,
517 KVM_REG_MIPS_CP0_CONFIG4
,
518 KVM_REG_MIPS_CP0_CONFIG5
,
519 KVM_REG_MIPS_CP0_CONFIG7
,
520 KVM_REG_MIPS_CP0_ERROREPC
,
522 KVM_REG_MIPS_COUNT_CTL
,
523 KVM_REG_MIPS_COUNT_RESUME
,
524 KVM_REG_MIPS_COUNT_HZ
,
527 static int kvm_mips_get_reg(struct kvm_vcpu
*vcpu
,
528 const struct kvm_one_reg
*reg
)
530 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
531 struct mips_fpu_struct
*fpu
= &vcpu
->arch
.fpu
;
538 /* General purpose registers */
539 case KVM_REG_MIPS_R0
... KVM_REG_MIPS_R31
:
540 v
= (long)vcpu
->arch
.gprs
[reg
->id
- KVM_REG_MIPS_R0
];
542 case KVM_REG_MIPS_HI
:
543 v
= (long)vcpu
->arch
.hi
;
545 case KVM_REG_MIPS_LO
:
546 v
= (long)vcpu
->arch
.lo
;
548 case KVM_REG_MIPS_PC
:
549 v
= (long)vcpu
->arch
.pc
;
552 /* Floating point registers */
553 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
554 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
556 idx
= reg
->id
- KVM_REG_MIPS_FPR_32(0);
557 /* Odd singles in top of even double when FR=0 */
558 if (kvm_read_c0_guest_status(cop0
) & ST0_FR
)
559 v
= get_fpr32(&fpu
->fpr
[idx
], 0);
561 v
= get_fpr32(&fpu
->fpr
[idx
& ~1], idx
& 1);
563 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
564 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
566 idx
= reg
->id
- KVM_REG_MIPS_FPR_64(0);
567 /* Can't access odd doubles in FR=0 mode */
568 if (idx
& 1 && !(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
570 v
= get_fpr64(&fpu
->fpr
[idx
], 0);
572 case KVM_REG_MIPS_FCR_IR
:
573 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
575 v
= boot_cpu_data
.fpu_id
;
577 case KVM_REG_MIPS_FCR_CSR
:
578 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
583 /* MIPS SIMD Architecture (MSA) registers */
584 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
585 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
587 /* Can't access MSA registers in FR=0 mode */
588 if (!(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
590 idx
= reg
->id
- KVM_REG_MIPS_VEC_128(0);
591 #ifdef CONFIG_CPU_LITTLE_ENDIAN
592 /* least significant byte first */
593 vs
[0] = get_fpr64(&fpu
->fpr
[idx
], 0);
594 vs
[1] = get_fpr64(&fpu
->fpr
[idx
], 1);
596 /* most significant byte first */
597 vs
[0] = get_fpr64(&fpu
->fpr
[idx
], 1);
598 vs
[1] = get_fpr64(&fpu
->fpr
[idx
], 0);
601 case KVM_REG_MIPS_MSA_IR
:
602 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
604 v
= boot_cpu_data
.msa_id
;
606 case KVM_REG_MIPS_MSA_CSR
:
607 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
612 /* Co-processor 0 registers */
613 case KVM_REG_MIPS_CP0_INDEX
:
614 v
= (long)kvm_read_c0_guest_index(cop0
);
616 case KVM_REG_MIPS_CP0_CONTEXT
:
617 v
= (long)kvm_read_c0_guest_context(cop0
);
619 case KVM_REG_MIPS_CP0_USERLOCAL
:
620 v
= (long)kvm_read_c0_guest_userlocal(cop0
);
622 case KVM_REG_MIPS_CP0_PAGEMASK
:
623 v
= (long)kvm_read_c0_guest_pagemask(cop0
);
625 case KVM_REG_MIPS_CP0_WIRED
:
626 v
= (long)kvm_read_c0_guest_wired(cop0
);
628 case KVM_REG_MIPS_CP0_HWRENA
:
629 v
= (long)kvm_read_c0_guest_hwrena(cop0
);
631 case KVM_REG_MIPS_CP0_BADVADDR
:
632 v
= (long)kvm_read_c0_guest_badvaddr(cop0
);
634 case KVM_REG_MIPS_CP0_ENTRYHI
:
635 v
= (long)kvm_read_c0_guest_entryhi(cop0
);
637 case KVM_REG_MIPS_CP0_COMPARE
:
638 v
= (long)kvm_read_c0_guest_compare(cop0
);
640 case KVM_REG_MIPS_CP0_STATUS
:
641 v
= (long)kvm_read_c0_guest_status(cop0
);
643 case KVM_REG_MIPS_CP0_CAUSE
:
644 v
= (long)kvm_read_c0_guest_cause(cop0
);
646 case KVM_REG_MIPS_CP0_EPC
:
647 v
= (long)kvm_read_c0_guest_epc(cop0
);
649 case KVM_REG_MIPS_CP0_PRID
:
650 v
= (long)kvm_read_c0_guest_prid(cop0
);
652 case KVM_REG_MIPS_CP0_CONFIG
:
653 v
= (long)kvm_read_c0_guest_config(cop0
);
655 case KVM_REG_MIPS_CP0_CONFIG1
:
656 v
= (long)kvm_read_c0_guest_config1(cop0
);
658 case KVM_REG_MIPS_CP0_CONFIG2
:
659 v
= (long)kvm_read_c0_guest_config2(cop0
);
661 case KVM_REG_MIPS_CP0_CONFIG3
:
662 v
= (long)kvm_read_c0_guest_config3(cop0
);
664 case KVM_REG_MIPS_CP0_CONFIG4
:
665 v
= (long)kvm_read_c0_guest_config4(cop0
);
667 case KVM_REG_MIPS_CP0_CONFIG5
:
668 v
= (long)kvm_read_c0_guest_config5(cop0
);
670 case KVM_REG_MIPS_CP0_CONFIG7
:
671 v
= (long)kvm_read_c0_guest_config7(cop0
);
673 case KVM_REG_MIPS_CP0_ERROREPC
:
674 v
= (long)kvm_read_c0_guest_errorepc(cop0
);
676 /* registers to be handled specially */
677 case KVM_REG_MIPS_CP0_COUNT
:
678 case KVM_REG_MIPS_COUNT_CTL
:
679 case KVM_REG_MIPS_COUNT_RESUME
:
680 case KVM_REG_MIPS_COUNT_HZ
:
681 ret
= kvm_mips_callbacks
->get_one_reg(vcpu
, reg
, &v
);
688 if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
) {
689 u64 __user
*uaddr64
= (u64 __user
*)(long)reg
->addr
;
691 return put_user(v
, uaddr64
);
692 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
) {
693 u32 __user
*uaddr32
= (u32 __user
*)(long)reg
->addr
;
696 return put_user(v32
, uaddr32
);
697 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U128
) {
698 void __user
*uaddr
= (void __user
*)(long)reg
->addr
;
700 return copy_to_user(uaddr
, vs
, 16);
706 static int kvm_mips_set_reg(struct kvm_vcpu
*vcpu
,
707 const struct kvm_one_reg
*reg
)
709 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
710 struct mips_fpu_struct
*fpu
= &vcpu
->arch
.fpu
;
715 if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
) {
716 u64 __user
*uaddr64
= (u64 __user
*)(long)reg
->addr
;
718 if (get_user(v
, uaddr64
) != 0)
720 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
) {
721 u32 __user
*uaddr32
= (u32 __user
*)(long)reg
->addr
;
724 if (get_user(v32
, uaddr32
) != 0)
727 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U128
) {
728 void __user
*uaddr
= (void __user
*)(long)reg
->addr
;
730 return copy_from_user(vs
, uaddr
, 16);
736 /* General purpose registers */
737 case KVM_REG_MIPS_R0
:
738 /* Silently ignore requests to set $0 */
740 case KVM_REG_MIPS_R1
... KVM_REG_MIPS_R31
:
741 vcpu
->arch
.gprs
[reg
->id
- KVM_REG_MIPS_R0
] = v
;
743 case KVM_REG_MIPS_HI
:
746 case KVM_REG_MIPS_LO
:
749 case KVM_REG_MIPS_PC
:
753 /* Floating point registers */
754 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
755 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
757 idx
= reg
->id
- KVM_REG_MIPS_FPR_32(0);
758 /* Odd singles in top of even double when FR=0 */
759 if (kvm_read_c0_guest_status(cop0
) & ST0_FR
)
760 set_fpr32(&fpu
->fpr
[idx
], 0, v
);
762 set_fpr32(&fpu
->fpr
[idx
& ~1], idx
& 1, v
);
764 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
765 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
767 idx
= reg
->id
- KVM_REG_MIPS_FPR_64(0);
768 /* Can't access odd doubles in FR=0 mode */
769 if (idx
& 1 && !(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
771 set_fpr64(&fpu
->fpr
[idx
], 0, v
);
773 case KVM_REG_MIPS_FCR_IR
:
774 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
778 case KVM_REG_MIPS_FCR_CSR
:
779 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
784 /* MIPS SIMD Architecture (MSA) registers */
785 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
786 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
788 idx
= reg
->id
- KVM_REG_MIPS_VEC_128(0);
789 #ifdef CONFIG_CPU_LITTLE_ENDIAN
790 /* least significant byte first */
791 set_fpr64(&fpu
->fpr
[idx
], 0, vs
[0]);
792 set_fpr64(&fpu
->fpr
[idx
], 1, vs
[1]);
794 /* most significant byte first */
795 set_fpr64(&fpu
->fpr
[idx
], 1, vs
[0]);
796 set_fpr64(&fpu
->fpr
[idx
], 0, vs
[1]);
799 case KVM_REG_MIPS_MSA_IR
:
800 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
804 case KVM_REG_MIPS_MSA_CSR
:
805 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
810 /* Co-processor 0 registers */
811 case KVM_REG_MIPS_CP0_INDEX
:
812 kvm_write_c0_guest_index(cop0
, v
);
814 case KVM_REG_MIPS_CP0_CONTEXT
:
815 kvm_write_c0_guest_context(cop0
, v
);
817 case KVM_REG_MIPS_CP0_USERLOCAL
:
818 kvm_write_c0_guest_userlocal(cop0
, v
);
820 case KVM_REG_MIPS_CP0_PAGEMASK
:
821 kvm_write_c0_guest_pagemask(cop0
, v
);
823 case KVM_REG_MIPS_CP0_WIRED
:
824 kvm_write_c0_guest_wired(cop0
, v
);
826 case KVM_REG_MIPS_CP0_HWRENA
:
827 kvm_write_c0_guest_hwrena(cop0
, v
);
829 case KVM_REG_MIPS_CP0_BADVADDR
:
830 kvm_write_c0_guest_badvaddr(cop0
, v
);
832 case KVM_REG_MIPS_CP0_ENTRYHI
:
833 kvm_write_c0_guest_entryhi(cop0
, v
);
835 case KVM_REG_MIPS_CP0_STATUS
:
836 kvm_write_c0_guest_status(cop0
, v
);
838 case KVM_REG_MIPS_CP0_EPC
:
839 kvm_write_c0_guest_epc(cop0
, v
);
841 case KVM_REG_MIPS_CP0_PRID
:
842 kvm_write_c0_guest_prid(cop0
, v
);
844 case KVM_REG_MIPS_CP0_ERROREPC
:
845 kvm_write_c0_guest_errorepc(cop0
, v
);
847 /* registers to be handled specially */
848 case KVM_REG_MIPS_CP0_COUNT
:
849 case KVM_REG_MIPS_CP0_COMPARE
:
850 case KVM_REG_MIPS_CP0_CAUSE
:
851 case KVM_REG_MIPS_CP0_CONFIG
:
852 case KVM_REG_MIPS_CP0_CONFIG1
:
853 case KVM_REG_MIPS_CP0_CONFIG2
:
854 case KVM_REG_MIPS_CP0_CONFIG3
:
855 case KVM_REG_MIPS_CP0_CONFIG4
:
856 case KVM_REG_MIPS_CP0_CONFIG5
:
857 case KVM_REG_MIPS_COUNT_CTL
:
858 case KVM_REG_MIPS_COUNT_RESUME
:
859 case KVM_REG_MIPS_COUNT_HZ
:
860 return kvm_mips_callbacks
->set_one_reg(vcpu
, reg
, v
);
867 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu
*vcpu
,
868 struct kvm_enable_cap
*cap
)
872 if (!kvm_vm_ioctl_check_extension(vcpu
->kvm
, cap
->cap
))
880 case KVM_CAP_MIPS_FPU
:
881 vcpu
->arch
.fpu_enabled
= true;
883 case KVM_CAP_MIPS_MSA
:
884 vcpu
->arch
.msa_enabled
= true;
894 long kvm_arch_vcpu_ioctl(struct file
*filp
, unsigned int ioctl
,
897 struct kvm_vcpu
*vcpu
= filp
->private_data
;
898 void __user
*argp
= (void __user
*)arg
;
902 case KVM_SET_ONE_REG
:
903 case KVM_GET_ONE_REG
: {
904 struct kvm_one_reg reg
;
906 if (copy_from_user(®
, argp
, sizeof(reg
)))
908 if (ioctl
== KVM_SET_ONE_REG
)
909 return kvm_mips_set_reg(vcpu
, ®
);
911 return kvm_mips_get_reg(vcpu
, ®
);
913 case KVM_GET_REG_LIST
: {
914 struct kvm_reg_list __user
*user_list
= argp
;
915 u64 __user
*reg_dest
;
916 struct kvm_reg_list reg_list
;
919 if (copy_from_user(®_list
, user_list
, sizeof(reg_list
)))
922 reg_list
.n
= ARRAY_SIZE(kvm_mips_get_one_regs
);
923 if (copy_to_user(user_list
, ®_list
, sizeof(reg_list
)))
927 reg_dest
= user_list
->reg
;
928 if (copy_to_user(reg_dest
, kvm_mips_get_one_regs
,
929 sizeof(kvm_mips_get_one_regs
)))
934 /* Treat the NMI as a CPU reset */
935 r
= kvm_mips_reset_vcpu(vcpu
);
939 struct kvm_mips_interrupt irq
;
942 if (copy_from_user(&irq
, argp
, sizeof(irq
)))
945 kvm_debug("[%d] %s: irq: %d\n", vcpu
->vcpu_id
, __func__
,
948 r
= kvm_vcpu_ioctl_interrupt(vcpu
, &irq
);
951 case KVM_ENABLE_CAP
: {
952 struct kvm_enable_cap cap
;
955 if (copy_from_user(&cap
, argp
, sizeof(cap
)))
957 r
= kvm_vcpu_ioctl_enable_cap(vcpu
, &cap
);
968 /* Get (and clear) the dirty memory log for a memory slot. */
969 int kvm_vm_ioctl_get_dirty_log(struct kvm
*kvm
, struct kvm_dirty_log
*log
)
971 struct kvm_memory_slot
*memslot
;
972 unsigned long ga
, ga_end
;
977 mutex_lock(&kvm
->slots_lock
);
979 r
= kvm_get_dirty_log(kvm
, log
, &is_dirty
);
983 /* If nothing is dirty, don't bother messing with page tables. */
985 memslot
= &kvm
->memslots
->memslots
[log
->slot
];
987 ga
= memslot
->base_gfn
<< PAGE_SHIFT
;
988 ga_end
= ga
+ (memslot
->npages
<< PAGE_SHIFT
);
990 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__
, ga
,
993 n
= kvm_dirty_bitmap_bytes(memslot
);
994 memset(memslot
->dirty_bitmap
, 0, n
);
999 mutex_unlock(&kvm
->slots_lock
);
1004 long kvm_arch_vm_ioctl(struct file
*filp
, unsigned int ioctl
, unsigned long arg
)
1016 int kvm_arch_init(void *opaque
)
1018 if (kvm_mips_callbacks
) {
1019 kvm_err("kvm: module already exists\n");
1023 return kvm_mips_emulation_init(&kvm_mips_callbacks
);
1026 void kvm_arch_exit(void)
1028 kvm_mips_callbacks
= NULL
;
1031 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu
*vcpu
,
1032 struct kvm_sregs
*sregs
)
1034 return -ENOIOCTLCMD
;
1037 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu
*vcpu
,
1038 struct kvm_sregs
*sregs
)
1040 return -ENOIOCTLCMD
;
1043 void kvm_arch_vcpu_postcreate(struct kvm_vcpu
*vcpu
)
1047 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu
*vcpu
, struct kvm_fpu
*fpu
)
1049 return -ENOIOCTLCMD
;
1052 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu
*vcpu
, struct kvm_fpu
*fpu
)
1054 return -ENOIOCTLCMD
;
1057 int kvm_arch_vcpu_fault(struct kvm_vcpu
*vcpu
, struct vm_fault
*vmf
)
1059 return VM_FAULT_SIGBUS
;
1062 int kvm_vm_ioctl_check_extension(struct kvm
*kvm
, long ext
)
1067 case KVM_CAP_ONE_REG
:
1068 case KVM_CAP_ENABLE_CAP
:
1071 case KVM_CAP_COALESCED_MMIO
:
1072 r
= KVM_COALESCED_MMIO_PAGE_OFFSET
;
1074 case KVM_CAP_MIPS_FPU
:
1077 case KVM_CAP_MIPS_MSA
:
1079 * We don't support MSA vector partitioning yet:
1080 * 1) It would require explicit support which can't be tested
1081 * yet due to lack of support in current hardware.
1082 * 2) It extends the state that would need to be saved/restored
1083 * by e.g. QEMU for migration.
1085 * When vector partitioning hardware becomes available, support
1086 * could be added by requiring a flag when enabling
1087 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1088 * to save/restore the appropriate extra state.
1090 r
= cpu_has_msa
&& !(boot_cpu_data
.msa_id
& MSA_IR_WRPF
);
1099 int kvm_cpu_has_pending_timer(struct kvm_vcpu
*vcpu
)
1101 return kvm_mips_pending_timer(vcpu
);
1104 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu
*vcpu
)
1107 struct mips_coproc
*cop0
;
1112 kvm_debug("VCPU Register Dump:\n");
1113 kvm_debug("\tpc = 0x%08lx\n", vcpu
->arch
.pc
);
1114 kvm_debug("\texceptions: %08lx\n", vcpu
->arch
.pending_exceptions
);
1116 for (i
= 0; i
< 32; i
+= 4) {
1117 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i
,
1119 vcpu
->arch
.gprs
[i
+ 1],
1120 vcpu
->arch
.gprs
[i
+ 2], vcpu
->arch
.gprs
[i
+ 3]);
1122 kvm_debug("\thi: 0x%08lx\n", vcpu
->arch
.hi
);
1123 kvm_debug("\tlo: 0x%08lx\n", vcpu
->arch
.lo
);
1125 cop0
= vcpu
->arch
.cop0
;
1126 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1127 kvm_read_c0_guest_status(cop0
),
1128 kvm_read_c0_guest_cause(cop0
));
1130 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0
));
1135 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu
*vcpu
, struct kvm_regs
*regs
)
1139 for (i
= 1; i
< ARRAY_SIZE(vcpu
->arch
.gprs
); i
++)
1140 vcpu
->arch
.gprs
[i
] = regs
->gpr
[i
];
1141 vcpu
->arch
.gprs
[0] = 0; /* zero is special, and cannot be set. */
1142 vcpu
->arch
.hi
= regs
->hi
;
1143 vcpu
->arch
.lo
= regs
->lo
;
1144 vcpu
->arch
.pc
= regs
->pc
;
1149 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu
*vcpu
, struct kvm_regs
*regs
)
1153 for (i
= 0; i
< ARRAY_SIZE(vcpu
->arch
.gprs
); i
++)
1154 regs
->gpr
[i
] = vcpu
->arch
.gprs
[i
];
1156 regs
->hi
= vcpu
->arch
.hi
;
1157 regs
->lo
= vcpu
->arch
.lo
;
1158 regs
->pc
= vcpu
->arch
.pc
;
1163 static void kvm_mips_comparecount_func(unsigned long data
)
1165 struct kvm_vcpu
*vcpu
= (struct kvm_vcpu
*)data
;
1167 kvm_mips_callbacks
->queue_timer_int(vcpu
);
1169 vcpu
->arch
.wait
= 0;
1170 if (waitqueue_active(&vcpu
->wq
))
1171 wake_up_interruptible(&vcpu
->wq
);
1174 /* low level hrtimer wake routine */
1175 static enum hrtimer_restart
kvm_mips_comparecount_wakeup(struct hrtimer
*timer
)
1177 struct kvm_vcpu
*vcpu
;
1179 vcpu
= container_of(timer
, struct kvm_vcpu
, arch
.comparecount_timer
);
1180 kvm_mips_comparecount_func((unsigned long) vcpu
);
1181 return kvm_mips_count_timeout(vcpu
);
1184 int kvm_arch_vcpu_init(struct kvm_vcpu
*vcpu
)
1186 kvm_mips_callbacks
->vcpu_init(vcpu
);
1187 hrtimer_init(&vcpu
->arch
.comparecount_timer
, CLOCK_MONOTONIC
,
1189 vcpu
->arch
.comparecount_timer
.function
= kvm_mips_comparecount_wakeup
;
1193 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu
*vcpu
,
1194 struct kvm_translation
*tr
)
1199 /* Initial guest state */
1200 int kvm_arch_vcpu_setup(struct kvm_vcpu
*vcpu
)
1202 return kvm_mips_callbacks
->vcpu_setup(vcpu
);
1205 static void kvm_mips_set_c0_status(void)
1207 uint32_t status
= read_c0_status();
1212 write_c0_status(status
);
1217 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1219 int kvm_mips_handle_exit(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
)
1221 uint32_t cause
= vcpu
->arch
.host_cp0_cause
;
1222 uint32_t exccode
= (cause
>> CAUSEB_EXCCODE
) & 0x1f;
1223 uint32_t __user
*opc
= (uint32_t __user
*) vcpu
->arch
.pc
;
1224 unsigned long badvaddr
= vcpu
->arch
.host_cp0_badvaddr
;
1225 enum emulation_result er
= EMULATE_DONE
;
1226 int ret
= RESUME_GUEST
;
1228 /* re-enable HTW before enabling interrupts */
1231 /* Set a default exit reason */
1232 run
->exit_reason
= KVM_EXIT_UNKNOWN
;
1233 run
->ready_for_interrupt_injection
= 1;
1236 * Set the appropriate status bits based on host CPU features,
1237 * before we hit the scheduler
1239 kvm_mips_set_c0_status();
1243 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1244 cause
, opc
, run
, vcpu
);
1247 * Do a privilege check, if in UM most of these exit conditions end up
1248 * causing an exception to be delivered to the Guest Kernel
1250 er
= kvm_mips_check_privilege(cause
, opc
, run
, vcpu
);
1251 if (er
== EMULATE_PRIV_FAIL
) {
1253 } else if (er
== EMULATE_FAIL
) {
1254 run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
1261 kvm_debug("[%d]T_INT @ %p\n", vcpu
->vcpu_id
, opc
);
1263 ++vcpu
->stat
.int_exits
;
1264 trace_kvm_exit(vcpu
, INT_EXITS
);
1272 case T_COP_UNUSABLE
:
1273 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc
);
1275 ++vcpu
->stat
.cop_unusable_exits
;
1276 trace_kvm_exit(vcpu
, COP_UNUSABLE_EXITS
);
1277 ret
= kvm_mips_callbacks
->handle_cop_unusable(vcpu
);
1278 /* XXXKYMA: Might need to return to user space */
1279 if (run
->exit_reason
== KVM_EXIT_IRQ_WINDOW_OPEN
)
1284 ++vcpu
->stat
.tlbmod_exits
;
1285 trace_kvm_exit(vcpu
, TLBMOD_EXITS
);
1286 ret
= kvm_mips_callbacks
->handle_tlb_mod(vcpu
);
1290 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1291 cause
, kvm_read_c0_guest_status(vcpu
->arch
.cop0
), opc
,
1294 ++vcpu
->stat
.tlbmiss_st_exits
;
1295 trace_kvm_exit(vcpu
, TLBMISS_ST_EXITS
);
1296 ret
= kvm_mips_callbacks
->handle_tlb_st_miss(vcpu
);
1300 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1301 cause
, opc
, badvaddr
);
1303 ++vcpu
->stat
.tlbmiss_ld_exits
;
1304 trace_kvm_exit(vcpu
, TLBMISS_LD_EXITS
);
1305 ret
= kvm_mips_callbacks
->handle_tlb_ld_miss(vcpu
);
1309 ++vcpu
->stat
.addrerr_st_exits
;
1310 trace_kvm_exit(vcpu
, ADDRERR_ST_EXITS
);
1311 ret
= kvm_mips_callbacks
->handle_addr_err_st(vcpu
);
1315 ++vcpu
->stat
.addrerr_ld_exits
;
1316 trace_kvm_exit(vcpu
, ADDRERR_LD_EXITS
);
1317 ret
= kvm_mips_callbacks
->handle_addr_err_ld(vcpu
);
1321 ++vcpu
->stat
.syscall_exits
;
1322 trace_kvm_exit(vcpu
, SYSCALL_EXITS
);
1323 ret
= kvm_mips_callbacks
->handle_syscall(vcpu
);
1327 ++vcpu
->stat
.resvd_inst_exits
;
1328 trace_kvm_exit(vcpu
, RESVD_INST_EXITS
);
1329 ret
= kvm_mips_callbacks
->handle_res_inst(vcpu
);
1333 ++vcpu
->stat
.break_inst_exits
;
1334 trace_kvm_exit(vcpu
, BREAK_INST_EXITS
);
1335 ret
= kvm_mips_callbacks
->handle_break(vcpu
);
1339 ++vcpu
->stat
.trap_inst_exits
;
1340 trace_kvm_exit(vcpu
, TRAP_INST_EXITS
);
1341 ret
= kvm_mips_callbacks
->handle_trap(vcpu
);
1345 ++vcpu
->stat
.msa_fpe_exits
;
1346 trace_kvm_exit(vcpu
, MSA_FPE_EXITS
);
1347 ret
= kvm_mips_callbacks
->handle_msa_fpe(vcpu
);
1351 ++vcpu
->stat
.fpe_exits
;
1352 trace_kvm_exit(vcpu
, FPE_EXITS
);
1353 ret
= kvm_mips_callbacks
->handle_fpe(vcpu
);
1357 ++vcpu
->stat
.msa_disabled_exits
;
1358 trace_kvm_exit(vcpu
, MSA_DISABLED_EXITS
);
1359 ret
= kvm_mips_callbacks
->handle_msa_disabled(vcpu
);
1363 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1364 exccode
, opc
, kvm_get_inst(opc
, vcpu
), badvaddr
,
1365 kvm_read_c0_guest_status(vcpu
->arch
.cop0
));
1366 kvm_arch_vcpu_dump_regs(vcpu
);
1367 run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
1374 local_irq_disable();
1376 if (er
== EMULATE_DONE
&& !(ret
& RESUME_HOST
))
1377 kvm_mips_deliver_interrupts(vcpu
, cause
);
1379 if (!(ret
& RESUME_HOST
)) {
1380 /* Only check for signals if not already exiting to userspace */
1381 if (signal_pending(current
)) {
1382 run
->exit_reason
= KVM_EXIT_INTR
;
1383 ret
= (-EINTR
<< 2) | RESUME_HOST
;
1384 ++vcpu
->stat
.signal_exits
;
1385 trace_kvm_exit(vcpu
, SIGNAL_EXITS
);
1389 if (ret
== RESUME_GUEST
) {
1391 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1392 * is live), restore FCR31 / MSACSR.
1394 * This should be before returning to the guest exception
1395 * vector, as it may well cause an [MSA] FP exception if there
1396 * are pending exception bits unmasked. (see
1397 * kvm_mips_csr_die_notifier() for how that is handled).
1399 if (kvm_mips_guest_has_fpu(&vcpu
->arch
) &&
1400 read_c0_status() & ST0_CU1
)
1401 __kvm_restore_fcsr(&vcpu
->arch
);
1403 if (kvm_mips_guest_has_msa(&vcpu
->arch
) &&
1404 read_c0_config5() & MIPS_CONF5_MSAEN
)
1405 __kvm_restore_msacsr(&vcpu
->arch
);
1408 /* Disable HTW before returning to guest or host */
1414 /* Enable FPU for guest and restore context */
1415 void kvm_own_fpu(struct kvm_vcpu
*vcpu
)
1417 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
1418 unsigned int sr
, cfg5
;
1422 sr
= kvm_read_c0_guest_status(cop0
);
1425 * If MSA state is already live, it is undefined how it interacts with
1426 * FR=0 FPU state, and we don't want to hit reserved instruction
1427 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1428 * play it safe and save it first.
1430 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1431 * get called when guest CU1 is set, however we can't trust the guest
1432 * not to clobber the status register directly via the commpage.
1434 if (cpu_has_msa
&& sr
& ST0_CU1
&& !(sr
& ST0_FR
) &&
1435 vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_MSA
)
1439 * Enable FPU for guest
1440 * We set FR and FRE according to guest context
1442 change_c0_status(ST0_CU1
| ST0_FR
, sr
);
1444 cfg5
= kvm_read_c0_guest_config5(cop0
);
1445 change_c0_config5(MIPS_CONF5_FRE
, cfg5
);
1447 enable_fpu_hazard();
1449 /* If guest FPU state not active, restore it now */
1450 if (!(vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_FPU
)) {
1451 __kvm_restore_fpu(&vcpu
->arch
);
1452 vcpu
->arch
.fpu_inuse
|= KVM_MIPS_FPU_FPU
;
1458 #ifdef CONFIG_CPU_HAS_MSA
1459 /* Enable MSA for guest and restore context */
1460 void kvm_own_msa(struct kvm_vcpu
*vcpu
)
1462 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
1463 unsigned int sr
, cfg5
;
1468 * Enable FPU if enabled in guest, since we're restoring FPU context
1469 * anyway. We set FR and FRE according to guest context.
1471 if (kvm_mips_guest_has_fpu(&vcpu
->arch
)) {
1472 sr
= kvm_read_c0_guest_status(cop0
);
1475 * If FR=0 FPU state is already live, it is undefined how it
1476 * interacts with MSA state, so play it safe and save it first.
1478 if (!(sr
& ST0_FR
) &&
1479 (vcpu
->arch
.fpu_inuse
& (KVM_MIPS_FPU_FPU
|
1480 KVM_MIPS_FPU_MSA
)) == KVM_MIPS_FPU_FPU
)
1483 change_c0_status(ST0_CU1
| ST0_FR
, sr
);
1484 if (sr
& ST0_CU1
&& cpu_has_fre
) {
1485 cfg5
= kvm_read_c0_guest_config5(cop0
);
1486 change_c0_config5(MIPS_CONF5_FRE
, cfg5
);
1490 /* Enable MSA for guest */
1491 set_c0_config5(MIPS_CONF5_MSAEN
);
1492 enable_fpu_hazard();
1494 switch (vcpu
->arch
.fpu_inuse
& (KVM_MIPS_FPU_FPU
| KVM_MIPS_FPU_MSA
)) {
1495 case KVM_MIPS_FPU_FPU
:
1497 * Guest FPU state already loaded, only restore upper MSA state
1499 __kvm_restore_msa_upper(&vcpu
->arch
);
1500 vcpu
->arch
.fpu_inuse
|= KVM_MIPS_FPU_MSA
;
1503 /* Neither FPU or MSA already active, restore full MSA state */
1504 __kvm_restore_msa(&vcpu
->arch
);
1505 vcpu
->arch
.fpu_inuse
|= KVM_MIPS_FPU_MSA
;
1506 if (kvm_mips_guest_has_fpu(&vcpu
->arch
))
1507 vcpu
->arch
.fpu_inuse
|= KVM_MIPS_FPU_FPU
;
1517 /* Drop FPU & MSA without saving it */
1518 void kvm_drop_fpu(struct kvm_vcpu
*vcpu
)
1521 if (cpu_has_msa
&& vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_MSA
) {
1523 vcpu
->arch
.fpu_inuse
&= ~KVM_MIPS_FPU_MSA
;
1525 if (vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_FPU
) {
1526 clear_c0_status(ST0_CU1
| ST0_FR
);
1527 vcpu
->arch
.fpu_inuse
&= ~KVM_MIPS_FPU_FPU
;
1532 /* Save and disable FPU & MSA */
1533 void kvm_lose_fpu(struct kvm_vcpu
*vcpu
)
1536 * FPU & MSA get disabled in root context (hardware) when it is disabled
1537 * in guest context (software), but the register state in the hardware
1538 * may still be in use. This is why we explicitly re-enable the hardware
1543 if (cpu_has_msa
&& vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_MSA
) {
1544 set_c0_config5(MIPS_CONF5_MSAEN
);
1545 enable_fpu_hazard();
1547 __kvm_save_msa(&vcpu
->arch
);
1549 /* Disable MSA & FPU */
1551 if (vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_FPU
)
1552 clear_c0_status(ST0_CU1
| ST0_FR
);
1553 vcpu
->arch
.fpu_inuse
&= ~(KVM_MIPS_FPU_FPU
| KVM_MIPS_FPU_MSA
);
1554 } else if (vcpu
->arch
.fpu_inuse
& KVM_MIPS_FPU_FPU
) {
1555 set_c0_status(ST0_CU1
);
1556 enable_fpu_hazard();
1558 __kvm_save_fpu(&vcpu
->arch
);
1559 vcpu
->arch
.fpu_inuse
&= ~KVM_MIPS_FPU_FPU
;
1562 clear_c0_status(ST0_CU1
| ST0_FR
);
1568 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1569 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1570 * exception if cause bits are set in the value being written.
1572 static int kvm_mips_csr_die_notify(struct notifier_block
*self
,
1573 unsigned long cmd
, void *ptr
)
1575 struct die_args
*args
= (struct die_args
*)ptr
;
1576 struct pt_regs
*regs
= args
->regs
;
1579 /* Only interested in FPE and MSAFPE */
1580 if (cmd
!= DIE_FP
&& cmd
!= DIE_MSAFP
)
1583 /* Return immediately if guest context isn't active */
1584 if (!(current
->flags
& PF_VCPU
))
1587 /* Should never get here from user mode */
1588 BUG_ON(user_mode(regs
));
1590 pc
= instruction_pointer(regs
);
1593 /* match 2nd instruction in __kvm_restore_fcsr */
1594 if (pc
!= (unsigned long)&__kvm_restore_fcsr
+ 4)
1598 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1600 pc
< (unsigned long)&__kvm_restore_msacsr
+ 4 ||
1601 pc
> (unsigned long)&__kvm_restore_msacsr
+ 8)
1606 /* Move PC forward a little and continue executing */
1607 instruction_pointer(regs
) += 4;
1612 static struct notifier_block kvm_mips_csr_die_notifier
= {
1613 .notifier_call
= kvm_mips_csr_die_notify
,
1616 int __init
kvm_mips_init(void)
1620 ret
= kvm_init(NULL
, sizeof(struct kvm_vcpu
), 0, THIS_MODULE
);
1625 register_die_notifier(&kvm_mips_csr_die_notifier
);
1628 * On MIPS, kernel modules are executed from "mapped space", which
1629 * requires TLBs. The TLB handling code is statically linked with
1630 * the rest of the kernel (tlb.c) to avoid the possibility of
1631 * double faulting. The issue is that the TLB code references
1632 * routines that are part of the the KVM module, which are only
1633 * available once the module is loaded.
1635 kvm_mips_gfn_to_pfn
= gfn_to_pfn
;
1636 kvm_mips_release_pfn_clean
= kvm_release_pfn_clean
;
1637 kvm_mips_is_error_pfn
= is_error_pfn
;
1642 void __exit
kvm_mips_exit(void)
1646 kvm_mips_gfn_to_pfn
= NULL
;
1647 kvm_mips_release_pfn_clean
= NULL
;
1648 kvm_mips_is_error_pfn
= NULL
;
1650 unregister_die_notifier(&kvm_mips_csr_die_notifier
);
1653 module_init(kvm_mips_init
);
1654 module_exit(kvm_mips_exit
);
1656 EXPORT_TRACEPOINT_SYMBOL(kvm_exit
);