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Merge tag 'topic/drm-fixes-2016-04-07' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / arch / mips / math-emu / cp1emu.c
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74 FPU_CSR_COND,
75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
382 case mm_mfhc1_op:
383 case mm_mthc1_op:
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 op = ctc_op;
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
421 }
422 break;
423 default:
424 return SIGILL;
425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429 }
430
431 /*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
439 {
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
445 case spec_op:
446 switch (insn.r_format.func) {
447 case jalr_op:
448 regs->regs[insn.r_format.rd] =
449 regs->cp0_epc + dec_insn.pc_inc +
450 dec_insn.next_pc_inc;
451 /* Fall through */
452 case jr_op:
453 /* For R6, JR already emulated in jalr_op */
454 if (NO_R6EMU && insn.r_format.func == jr_op)
455 break;
456 *contpc = regs->regs[insn.r_format.rs];
457 return 1;
458 }
459 break;
460 case bcond_op:
461 switch (insn.i_format.rt) {
462 case bltzal_op:
463 case bltzall_op:
464 if (NO_R6EMU && (insn.i_format.rs ||
465 insn.i_format.rt == bltzall_op))
466 break;
467
468 regs->regs[31] = regs->cp0_epc +
469 dec_insn.pc_inc +
470 dec_insn.next_pc_inc;
471 /* Fall through */
472 case bltzl_op:
473 if (NO_R6EMU)
474 break;
475 case bltz_op:
476 if ((long)regs->regs[insn.i_format.rs] < 0)
477 *contpc = regs->cp0_epc +
478 dec_insn.pc_inc +
479 (insn.i_format.simmediate << 2);
480 else
481 *contpc = regs->cp0_epc +
482 dec_insn.pc_inc +
483 dec_insn.next_pc_inc;
484 return 1;
485 case bgezal_op:
486 case bgezall_op:
487 if (NO_R6EMU && (insn.i_format.rs ||
488 insn.i_format.rt == bgezall_op))
489 break;
490
491 regs->regs[31] = regs->cp0_epc +
492 dec_insn.pc_inc +
493 dec_insn.next_pc_inc;
494 /* Fall through */
495 case bgezl_op:
496 if (NO_R6EMU)
497 break;
498 case bgez_op:
499 if ((long)regs->regs[insn.i_format.rs] >= 0)
500 *contpc = regs->cp0_epc +
501 dec_insn.pc_inc +
502 (insn.i_format.simmediate << 2);
503 else
504 *contpc = regs->cp0_epc +
505 dec_insn.pc_inc +
506 dec_insn.next_pc_inc;
507 return 1;
508 }
509 break;
510 case jalx_op:
511 set_isa16_mode(bit);
512 case jal_op:
513 regs->regs[31] = regs->cp0_epc +
514 dec_insn.pc_inc +
515 dec_insn.next_pc_inc;
516 /* Fall through */
517 case j_op:
518 *contpc = regs->cp0_epc + dec_insn.pc_inc;
519 *contpc >>= 28;
520 *contpc <<= 28;
521 *contpc |= (insn.j_format.target << 2);
522 /* Set microMIPS mode bit: XOR for jalx. */
523 *contpc ^= bit;
524 return 1;
525 case beql_op:
526 if (NO_R6EMU)
527 break;
528 case beq_op:
529 if (regs->regs[insn.i_format.rs] ==
530 regs->regs[insn.i_format.rt])
531 *contpc = regs->cp0_epc +
532 dec_insn.pc_inc +
533 (insn.i_format.simmediate << 2);
534 else
535 *contpc = regs->cp0_epc +
536 dec_insn.pc_inc +
537 dec_insn.next_pc_inc;
538 return 1;
539 case bnel_op:
540 if (NO_R6EMU)
541 break;
542 case bne_op:
543 if (regs->regs[insn.i_format.rs] !=
544 regs->regs[insn.i_format.rt])
545 *contpc = regs->cp0_epc +
546 dec_insn.pc_inc +
547 (insn.i_format.simmediate << 2);
548 else
549 *contpc = regs->cp0_epc +
550 dec_insn.pc_inc +
551 dec_insn.next_pc_inc;
552 return 1;
553 case blezl_op:
554 if (!insn.i_format.rt && NO_R6EMU)
555 break;
556 case blez_op:
557
558 /*
559 * Compact branches for R6 for the
560 * blez and blezl opcodes.
561 * BLEZ | rs = 0 | rt != 0 == BLEZALC
562 * BLEZ | rs = rt != 0 == BGEZALC
563 * BLEZ | rs != 0 | rt != 0 == BGEUC
564 * BLEZL | rs = 0 | rt != 0 == BLEZC
565 * BLEZL | rs = rt != 0 == BGEZC
566 * BLEZL | rs != 0 | rt != 0 == BGEC
567 *
568 * For real BLEZ{,L}, rt is always 0.
569 */
570 if (cpu_has_mips_r6 && insn.i_format.rt) {
571 if ((insn.i_format.opcode == blez_op) &&
572 ((!insn.i_format.rs && insn.i_format.rt) ||
573 (insn.i_format.rs == insn.i_format.rt)))
574 regs->regs[31] = regs->cp0_epc +
575 dec_insn.pc_inc;
576 *contpc = regs->cp0_epc + dec_insn.pc_inc +
577 dec_insn.next_pc_inc;
578
579 return 1;
580 }
581 if ((long)regs->regs[insn.i_format.rs] <= 0)
582 *contpc = regs->cp0_epc +
583 dec_insn.pc_inc +
584 (insn.i_format.simmediate << 2);
585 else
586 *contpc = regs->cp0_epc +
587 dec_insn.pc_inc +
588 dec_insn.next_pc_inc;
589 return 1;
590 case bgtzl_op:
591 if (!insn.i_format.rt && NO_R6EMU)
592 break;
593 case bgtz_op:
594 /*
595 * Compact branches for R6 for the
596 * bgtz and bgtzl opcodes.
597 * BGTZ | rs = 0 | rt != 0 == BGTZALC
598 * BGTZ | rs = rt != 0 == BLTZALC
599 * BGTZ | rs != 0 | rt != 0 == BLTUC
600 * BGTZL | rs = 0 | rt != 0 == BGTZC
601 * BGTZL | rs = rt != 0 == BLTZC
602 * BGTZL | rs != 0 | rt != 0 == BLTC
603 *
604 * *ZALC varint for BGTZ &&& rt != 0
605 * For real GTZ{,L}, rt is always 0.
606 */
607 if (cpu_has_mips_r6 && insn.i_format.rt) {
608 if ((insn.i_format.opcode == blez_op) &&
609 ((!insn.i_format.rs && insn.i_format.rt) ||
610 (insn.i_format.rs == insn.i_format.rt)))
611 regs->regs[31] = regs->cp0_epc +
612 dec_insn.pc_inc;
613 *contpc = regs->cp0_epc + dec_insn.pc_inc +
614 dec_insn.next_pc_inc;
615
616 return 1;
617 }
618
619 if ((long)regs->regs[insn.i_format.rs] > 0)
620 *contpc = regs->cp0_epc +
621 dec_insn.pc_inc +
622 (insn.i_format.simmediate << 2);
623 else
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 dec_insn.next_pc_inc;
627 return 1;
628 case cbcond0_op:
629 case cbcond1_op:
630 if (!cpu_has_mips_r6)
631 break;
632 if (insn.i_format.rt && !insn.i_format.rs)
633 regs->regs[31] = regs->cp0_epc + 4;
634 *contpc = regs->cp0_epc + dec_insn.pc_inc +
635 dec_insn.next_pc_inc;
636
637 return 1;
638 #ifdef CONFIG_CPU_CAVIUM_OCTEON
639 case lwc2_op: /* This is bbit0 on Octeon */
640 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
641 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
642 else
643 *contpc = regs->cp0_epc + 8;
644 return 1;
645 case ldc2_op: /* This is bbit032 on Octeon */
646 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
647 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
648 else
649 *contpc = regs->cp0_epc + 8;
650 return 1;
651 case swc2_op: /* This is bbit1 on Octeon */
652 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
653 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
654 else
655 *contpc = regs->cp0_epc + 8;
656 return 1;
657 case sdc2_op: /* This is bbit132 on Octeon */
658 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
659 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
660 else
661 *contpc = regs->cp0_epc + 8;
662 return 1;
663 #else
664 case bc6_op:
665 /*
666 * Only valid for MIPS R6 but we can still end up
667 * here from a broken userland so just tell emulator
668 * this is not a branch and let it break later on.
669 */
670 if (!cpu_has_mips_r6)
671 break;
672 *contpc = regs->cp0_epc + dec_insn.pc_inc +
673 dec_insn.next_pc_inc;
674
675 return 1;
676 case balc6_op:
677 if (!cpu_has_mips_r6)
678 break;
679 regs->regs[31] = regs->cp0_epc + 4;
680 *contpc = regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
682
683 return 1;
684 case beqzcjic_op:
685 if (!cpu_has_mips_r6)
686 break;
687 *contpc = regs->cp0_epc + dec_insn.pc_inc +
688 dec_insn.next_pc_inc;
689
690 return 1;
691 case bnezcjialc_op:
692 if (!cpu_has_mips_r6)
693 break;
694 if (!insn.i_format.rs)
695 regs->regs[31] = regs->cp0_epc + 4;
696 *contpc = regs->cp0_epc + dec_insn.pc_inc +
697 dec_insn.next_pc_inc;
698
699 return 1;
700 #endif
701 case cop0_op:
702 case cop1_op:
703 /* Need to check for R6 bc1nez and bc1eqz branches */
704 if (cpu_has_mips_r6 &&
705 ((insn.i_format.rs == bc1eqz_op) ||
706 (insn.i_format.rs == bc1nez_op))) {
707 bit = 0;
708 switch (insn.i_format.rs) {
709 case bc1eqz_op:
710 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
711 bit = 1;
712 break;
713 case bc1nez_op:
714 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
715 bit = 1;
716 break;
717 }
718 if (bit)
719 *contpc = regs->cp0_epc +
720 dec_insn.pc_inc +
721 (insn.i_format.simmediate << 2);
722 else
723 *contpc = regs->cp0_epc +
724 dec_insn.pc_inc +
725 dec_insn.next_pc_inc;
726
727 return 1;
728 }
729 /* R2/R6 compatible cop1 instruction. Fall through */
730 case cop2_op:
731 case cop1x_op:
732 if (insn.i_format.rs == bc_op) {
733 preempt_disable();
734 if (is_fpu_owner())
735 fcr31 = read_32bit_cp1_register(CP1_STATUS);
736 else
737 fcr31 = current->thread.fpu.fcr31;
738 preempt_enable();
739
740 bit = (insn.i_format.rt >> 2);
741 bit += (bit != 0);
742 bit += 23;
743 switch (insn.i_format.rt & 3) {
744 case 0: /* bc1f */
745 case 2: /* bc1fl */
746 if (~fcr31 & (1 << bit))
747 *contpc = regs->cp0_epc +
748 dec_insn.pc_inc +
749 (insn.i_format.simmediate << 2);
750 else
751 *contpc = regs->cp0_epc +
752 dec_insn.pc_inc +
753 dec_insn.next_pc_inc;
754 return 1;
755 case 1: /* bc1t */
756 case 3: /* bc1tl */
757 if (fcr31 & (1 << bit))
758 *contpc = regs->cp0_epc +
759 dec_insn.pc_inc +
760 (insn.i_format.simmediate << 2);
761 else
762 *contpc = regs->cp0_epc +
763 dec_insn.pc_inc +
764 dec_insn.next_pc_inc;
765 return 1;
766 }
767 }
768 break;
769 }
770 return 0;
771 }
772
773 /*
774 * In the Linux kernel, we support selection of FPR format on the
775 * basis of the Status.FR bit. If an FPU is not present, the FR bit
776 * is hardwired to zero, which would imply a 32-bit FPU even for
777 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
778 * FPU emu is slow and bulky and optimizing this function offers fairly
779 * sizeable benefits so we try to be clever and make this function return
780 * a constant whenever possible, that is on 64-bit kernels without O32
781 * compatibility enabled and on 32-bit without 64-bit FPU support.
782 */
783 static inline int cop1_64bit(struct pt_regs *xcp)
784 {
785 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
786 return 1;
787 else if (config_enabled(CONFIG_32BIT) &&
788 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
789 return 0;
790
791 return !test_thread_flag(TIF_32BIT_FPREGS);
792 }
793
794 static inline bool hybrid_fprs(void)
795 {
796 return test_thread_flag(TIF_HYBRID_FPREGS);
797 }
798
799 #define SIFROMREG(si, x) \
800 do { \
801 if (cop1_64bit(xcp) && !hybrid_fprs()) \
802 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
803 else \
804 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
805 } while (0)
806
807 #define SITOREG(si, x) \
808 do { \
809 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
810 unsigned i; \
811 set_fpr32(&ctx->fpr[x], 0, si); \
812 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
813 set_fpr32(&ctx->fpr[x], i, 0); \
814 } else { \
815 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
816 } \
817 } while (0)
818
819 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
820
821 #define SITOHREG(si, x) \
822 do { \
823 unsigned i; \
824 set_fpr32(&ctx->fpr[x], 1, si); \
825 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
826 set_fpr32(&ctx->fpr[x], i, 0); \
827 } while (0)
828
829 #define DIFROMREG(di, x) \
830 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
831
832 #define DITOREG(di, x) \
833 do { \
834 unsigned fpr, i; \
835 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
836 set_fpr64(&ctx->fpr[fpr], 0, di); \
837 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
838 set_fpr64(&ctx->fpr[fpr], i, 0); \
839 } while (0)
840
841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
842 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
843 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
844 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
845
846 /*
847 * Emulate a CFC1 instruction.
848 */
849 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
850 mips_instruction ir)
851 {
852 u32 fcr31 = ctx->fcr31;
853 u32 value = 0;
854
855 switch (MIPSInst_RD(ir)) {
856 case FPCREG_CSR:
857 value = fcr31;
858 pr_debug("%p gpr[%d]<-csr=%08x\n",
859 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
860 break;
861
862 case FPCREG_FENR:
863 if (!cpu_has_mips_r)
864 break;
865 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
866 MIPS_FENR_FS;
867 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
868 pr_debug("%p gpr[%d]<-enr=%08x\n",
869 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
870 break;
871
872 case FPCREG_FEXR:
873 if (!cpu_has_mips_r)
874 break;
875 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
876 pr_debug("%p gpr[%d]<-exr=%08x\n",
877 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
878 break;
879
880 case FPCREG_FCCR:
881 if (!cpu_has_mips_r)
882 break;
883 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
884 MIPS_FCCR_COND0;
885 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
886 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
887 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
889 break;
890
891 case FPCREG_RID:
892 value = boot_cpu_data.fpu_id;
893 break;
894
895 default:
896 break;
897 }
898
899 if (MIPSInst_RT(ir))
900 xcp->regs[MIPSInst_RT(ir)] = value;
901 }
902
903 /*
904 * Emulate a CTC1 instruction.
905 */
906 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
907 mips_instruction ir)
908 {
909 u32 fcr31 = ctx->fcr31;
910 u32 value;
911 u32 mask;
912
913 if (MIPSInst_RT(ir) == 0)
914 value = 0;
915 else
916 value = xcp->regs[MIPSInst_RT(ir)];
917
918 switch (MIPSInst_RD(ir)) {
919 case FPCREG_CSR:
920 pr_debug("%p gpr[%d]->csr=%08x\n",
921 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
922
923 /* Preserve read-only bits. */
924 mask = boot_cpu_data.fpu_msk31;
925 fcr31 = (value & ~mask) | (fcr31 & mask);
926 break;
927
928 case FPCREG_FENR:
929 if (!cpu_has_mips_r)
930 break;
931 pr_debug("%p gpr[%d]->enr=%08x\n",
932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
933 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
934 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
935 FPU_CSR_FS;
936 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
937 break;
938
939 case FPCREG_FEXR:
940 if (!cpu_has_mips_r)
941 break;
942 pr_debug("%p gpr[%d]->exr=%08x\n",
943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
945 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
946 break;
947
948 case FPCREG_FCCR:
949 if (!cpu_has_mips_r)
950 break;
951 pr_debug("%p gpr[%d]->ccr=%08x\n",
952 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
953 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
954 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
955 FPU_CSR_COND;
956 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
957 FPU_CSR_CONDX;
958 break;
959
960 default:
961 break;
962 }
963
964 ctx->fcr31 = fcr31;
965 }
966
967 /*
968 * Emulate the single floating point instruction pointed at by EPC.
969 * Two instructions if the instruction is in a branch delay slot.
970 */
971
972 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
973 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
974 {
975 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
976 unsigned int cond, cbit;
977 mips_instruction ir;
978 int likely, pc_inc;
979 u32 __user *wva;
980 u64 __user *dva;
981 u32 wval;
982 u64 dval;
983 int sig;
984
985 /*
986 * These are giving gcc a gentle hint about what to expect in
987 * dec_inst in order to do better optimization.
988 */
989 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
990 unreachable();
991
992 /* XXX NEC Vr54xx bug workaround */
993 if (delay_slot(xcp)) {
994 if (dec_insn.micro_mips_mode) {
995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
996 clear_delay_slot(xcp);
997 } else {
998 if (!isBranchInstr(xcp, dec_insn, &contpc))
999 clear_delay_slot(xcp);
1000 }
1001 }
1002
1003 if (delay_slot(xcp)) {
1004 /*
1005 * The instruction to be emulated is in a branch delay slot
1006 * which means that we have to emulate the branch instruction
1007 * BEFORE we do the cop1 instruction.
1008 *
1009 * This branch could be a COP1 branch, but in that case we
1010 * would have had a trap for that instruction, and would not
1011 * come through this route.
1012 *
1013 * Linux MIPS branch emulator operates on context, updating the
1014 * cp0_epc.
1015 */
1016 ir = dec_insn.next_insn; /* process delay slot instr */
1017 pc_inc = dec_insn.next_pc_inc;
1018 } else {
1019 ir = dec_insn.insn; /* process current instr */
1020 pc_inc = dec_insn.pc_inc;
1021 }
1022
1023 /*
1024 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1025 * instructions, we want to convert microMIPS FPU instructions
1026 * into MIPS32 instructions so that we could reuse all of the
1027 * FPU emulation code.
1028 *
1029 * NOTE: We cannot do this for branch instructions since they
1030 * are not a subset. Example: Cannot emulate a 16-bit
1031 * aligned target address with a MIPS32 instruction.
1032 */
1033 if (dec_insn.micro_mips_mode) {
1034 /*
1035 * If next instruction is a 16-bit instruction, then it
1036 * it cannot be a FPU instruction. This could happen
1037 * since we can be called for non-FPU instructions.
1038 */
1039 if ((pc_inc == 2) ||
1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1041 == SIGILL))
1042 return SIGILL;
1043 }
1044
1045 emul:
1046 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1047 MIPS_FPU_EMU_INC_STATS(emulated);
1048 switch (MIPSInst_OPCODE(ir)) {
1049 case ldc1_op:
1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1051 MIPSInst_SIMM(ir));
1052 MIPS_FPU_EMU_INC_STATS(loads);
1053
1054 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1055 MIPS_FPU_EMU_INC_STATS(errors);
1056 *fault_addr = dva;
1057 return SIGBUS;
1058 }
1059 if (__get_user(dval, dva)) {
1060 MIPS_FPU_EMU_INC_STATS(errors);
1061 *fault_addr = dva;
1062 return SIGSEGV;
1063 }
1064 DITOREG(dval, MIPSInst_RT(ir));
1065 break;
1066
1067 case sdc1_op:
1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1069 MIPSInst_SIMM(ir));
1070 MIPS_FPU_EMU_INC_STATS(stores);
1071 DIFROMREG(dval, MIPSInst_RT(ir));
1072 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1073 MIPS_FPU_EMU_INC_STATS(errors);
1074 *fault_addr = dva;
1075 return SIGBUS;
1076 }
1077 if (__put_user(dval, dva)) {
1078 MIPS_FPU_EMU_INC_STATS(errors);
1079 *fault_addr = dva;
1080 return SIGSEGV;
1081 }
1082 break;
1083
1084 case lwc1_op:
1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1086 MIPSInst_SIMM(ir));
1087 MIPS_FPU_EMU_INC_STATS(loads);
1088 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1089 MIPS_FPU_EMU_INC_STATS(errors);
1090 *fault_addr = wva;
1091 return SIGBUS;
1092 }
1093 if (__get_user(wval, wva)) {
1094 MIPS_FPU_EMU_INC_STATS(errors);
1095 *fault_addr = wva;
1096 return SIGSEGV;
1097 }
1098 SITOREG(wval, MIPSInst_RT(ir));
1099 break;
1100
1101 case swc1_op:
1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1103 MIPSInst_SIMM(ir));
1104 MIPS_FPU_EMU_INC_STATS(stores);
1105 SIFROMREG(wval, MIPSInst_RT(ir));
1106 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1107 MIPS_FPU_EMU_INC_STATS(errors);
1108 *fault_addr = wva;
1109 return SIGBUS;
1110 }
1111 if (__put_user(wval, wva)) {
1112 MIPS_FPU_EMU_INC_STATS(errors);
1113 *fault_addr = wva;
1114 return SIGSEGV;
1115 }
1116 break;
1117
1118 case cop1_op:
1119 switch (MIPSInst_RS(ir)) {
1120 case dmfc_op:
1121 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1122 return SIGILL;
1123
1124 /* copregister fs -> gpr[rt] */
1125 if (MIPSInst_RT(ir) != 0) {
1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1127 MIPSInst_RD(ir));
1128 }
1129 break;
1130
1131 case dmtc_op:
1132 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1133 return SIGILL;
1134
1135 /* copregister fs <- rt */
1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1137 break;
1138
1139 case mfhc_op:
1140 if (!cpu_has_mips_r2_r6)
1141 goto sigill;
1142
1143 /* copregister rd -> gpr[rt] */
1144 if (MIPSInst_RT(ir) != 0) {
1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1146 MIPSInst_RD(ir));
1147 }
1148 break;
1149
1150 case mthc_op:
1151 if (!cpu_has_mips_r2_r6)
1152 goto sigill;
1153
1154 /* copregister rd <- gpr[rt] */
1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1156 break;
1157
1158 case mfc_op:
1159 /* copregister rd -> gpr[rt] */
1160 if (MIPSInst_RT(ir) != 0) {
1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1162 MIPSInst_RD(ir));
1163 }
1164 break;
1165
1166 case mtc_op:
1167 /* copregister rd <- rt */
1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1169 break;
1170
1171 case cfc_op:
1172 /* cop control register rd -> gpr[rt] */
1173 cop1_cfc(xcp, ctx, ir);
1174 break;
1175
1176 case ctc_op:
1177 /* copregister rd <- rt */
1178 cop1_ctc(xcp, ctx, ir);
1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1180 return SIGFPE;
1181 }
1182 break;
1183
1184 case bc1eqz_op:
1185 case bc1nez_op:
1186 if (!cpu_has_mips_r6 || delay_slot(xcp))
1187 return SIGILL;
1188
1189 cond = likely = 0;
1190 switch (MIPSInst_RS(ir)) {
1191 case bc1eqz_op:
1192 if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1193 cond = 1;
1194 break;
1195 case bc1nez_op:
1196 if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1197 cond = 1;
1198 break;
1199 }
1200 goto branch_common;
1201
1202 case bc_op:
1203 if (delay_slot(xcp))
1204 return SIGILL;
1205
1206 if (cpu_has_mips_4_5_r)
1207 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1208 else
1209 cbit = FPU_CSR_COND;
1210 cond = ctx->fcr31 & cbit;
1211
1212 likely = 0;
1213 switch (MIPSInst_RT(ir) & 3) {
1214 case bcfl_op:
1215 if (cpu_has_mips_2_3_4_5_r)
1216 likely = 1;
1217 /* Fall through */
1218 case bcf_op:
1219 cond = !cond;
1220 break;
1221 case bctl_op:
1222 if (cpu_has_mips_2_3_4_5_r)
1223 likely = 1;
1224 /* Fall through */
1225 case bct_op:
1226 break;
1227 }
1228 branch_common:
1229 set_delay_slot(xcp);
1230 if (cond) {
1231 /*
1232 * Branch taken: emulate dslot instruction
1233 */
1234 unsigned long bcpc;
1235
1236 /*
1237 * Remember EPC at the branch to point back
1238 * at so that any delay-slot instruction
1239 * signal is not silently ignored.
1240 */
1241 bcpc = xcp->cp0_epc;
1242 xcp->cp0_epc += dec_insn.pc_inc;
1243
1244 contpc = MIPSInst_SIMM(ir);
1245 ir = dec_insn.next_insn;
1246 if (dec_insn.micro_mips_mode) {
1247 contpc = (xcp->cp0_epc + (contpc << 1));
1248
1249 /* If 16-bit instruction, not FPU. */
1250 if ((dec_insn.next_pc_inc == 2) ||
1251 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1252
1253 /*
1254 * Since this instruction will
1255 * be put on the stack with
1256 * 32-bit words, get around
1257 * this problem by putting a
1258 * NOP16 as the second one.
1259 */
1260 if (dec_insn.next_pc_inc == 2)
1261 ir = (ir & (~0xffff)) | MM_NOP16;
1262
1263 /*
1264 * Single step the non-CP1
1265 * instruction in the dslot.
1266 */
1267 sig = mips_dsemul(xcp, ir,
1268 contpc);
1269 if (sig < 0)
1270 break;
1271 if (sig)
1272 xcp->cp0_epc = bcpc;
1273 /*
1274 * SIGILL forces out of
1275 * the emulation loop.
1276 */
1277 return sig ? sig : SIGILL;
1278 }
1279 } else
1280 contpc = (xcp->cp0_epc + (contpc << 2));
1281
1282 switch (MIPSInst_OPCODE(ir)) {
1283 case lwc1_op:
1284 case swc1_op:
1285 goto emul;
1286
1287 case ldc1_op:
1288 case sdc1_op:
1289 if (cpu_has_mips_2_3_4_5_r)
1290 goto emul;
1291
1292 goto bc_sigill;
1293
1294 case cop1_op:
1295 goto emul;
1296
1297 case cop1x_op:
1298 if (cpu_has_mips_4_5_64_r2_r6)
1299 /* its one of ours */
1300 goto emul;
1301
1302 goto bc_sigill;
1303
1304 case spec_op:
1305 switch (MIPSInst_FUNC(ir)) {
1306 case movc_op:
1307 if (cpu_has_mips_4_5_r)
1308 goto emul;
1309
1310 goto bc_sigill;
1311 }
1312 break;
1313
1314 bc_sigill:
1315 xcp->cp0_epc = bcpc;
1316 return SIGILL;
1317 }
1318
1319 /*
1320 * Single step the non-cp1
1321 * instruction in the dslot
1322 */
1323 sig = mips_dsemul(xcp, ir, contpc);
1324 if (sig < 0)
1325 break;
1326 if (sig)
1327 xcp->cp0_epc = bcpc;
1328 /* SIGILL forces out of the emulation loop. */
1329 return sig ? sig : SIGILL;
1330 } else if (likely) { /* branch not taken */
1331 /*
1332 * branch likely nullifies
1333 * dslot if not taken
1334 */
1335 xcp->cp0_epc += dec_insn.pc_inc;
1336 contpc += dec_insn.pc_inc;
1337 /*
1338 * else continue & execute
1339 * dslot as normal insn
1340 */
1341 }
1342 break;
1343
1344 default:
1345 if (!(MIPSInst_RS(ir) & 0x10))
1346 return SIGILL;
1347
1348 /* a real fpu computation instruction */
1349 if ((sig = fpu_emu(xcp, ctx, ir)))
1350 return sig;
1351 }
1352 break;
1353
1354 case cop1x_op:
1355 if (!cpu_has_mips_4_5_64_r2_r6)
1356 return SIGILL;
1357
1358 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1359 if (sig)
1360 return sig;
1361 break;
1362
1363 case spec_op:
1364 if (!cpu_has_mips_4_5_r)
1365 return SIGILL;
1366
1367 if (MIPSInst_FUNC(ir) != movc_op)
1368 return SIGILL;
1369 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1370 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1371 xcp->regs[MIPSInst_RD(ir)] =
1372 xcp->regs[MIPSInst_RS(ir)];
1373 break;
1374 default:
1375 sigill:
1376 return SIGILL;
1377 }
1378
1379 /* we did it !! */
1380 xcp->cp0_epc = contpc;
1381 clear_delay_slot(xcp);
1382
1383 return 0;
1384 }
1385
1386 /*
1387 * Conversion table from MIPS compare ops 48-63
1388 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1389 */
1390 static const unsigned char cmptab[8] = {
1391 0, /* cmp_0 (sig) cmp_sf */
1392 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1393 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1394 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1395 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1396 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1397 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1398 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1399 };
1400
1401 static const unsigned char negative_cmptab[8] = {
1402 0, /* Reserved */
1403 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1404 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1405 IEEE754_CLT | IEEE754_CGT,
1406 /* Reserved */
1407 };
1408
1409
1410 /*
1411 * Additional MIPS4 instructions
1412 */
1413
1414 #define DEF3OP(name, p, f1, f2, f3) \
1415 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1416 union ieee754##p s, union ieee754##p t) \
1417 { \
1418 struct _ieee754_csr ieee754_csr_save; \
1419 s = f1(s, t); \
1420 ieee754_csr_save = ieee754_csr; \
1421 s = f2(s, r); \
1422 ieee754_csr_save.cx |= ieee754_csr.cx; \
1423 ieee754_csr_save.sx |= ieee754_csr.sx; \
1424 s = f3(s); \
1425 ieee754_csr.cx |= ieee754_csr_save.cx; \
1426 ieee754_csr.sx |= ieee754_csr_save.sx; \
1427 return s; \
1428 }
1429
1430 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1431 {
1432 return ieee754dp_div(ieee754dp_one(0), d);
1433 }
1434
1435 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1436 {
1437 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1438 }
1439
1440 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1441 {
1442 return ieee754sp_div(ieee754sp_one(0), s);
1443 }
1444
1445 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1446 {
1447 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1448 }
1449
1450 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1451 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1452 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1453 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1454 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1455 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1456 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1457 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1458
1459 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1460 mips_instruction ir, void *__user *fault_addr)
1461 {
1462 unsigned rcsr = 0; /* resulting csr */
1463
1464 MIPS_FPU_EMU_INC_STATS(cp1xops);
1465
1466 switch (MIPSInst_FMA_FFMT(ir)) {
1467 case s_fmt:{ /* 0 */
1468
1469 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1470 union ieee754sp fd, fr, fs, ft;
1471 u32 __user *va;
1472 u32 val;
1473
1474 switch (MIPSInst_FUNC(ir)) {
1475 case lwxc1_op:
1476 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1477 xcp->regs[MIPSInst_FT(ir)]);
1478
1479 MIPS_FPU_EMU_INC_STATS(loads);
1480 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1481 MIPS_FPU_EMU_INC_STATS(errors);
1482 *fault_addr = va;
1483 return SIGBUS;
1484 }
1485 if (__get_user(val, va)) {
1486 MIPS_FPU_EMU_INC_STATS(errors);
1487 *fault_addr = va;
1488 return SIGSEGV;
1489 }
1490 SITOREG(val, MIPSInst_FD(ir));
1491 break;
1492
1493 case swxc1_op:
1494 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1495 xcp->regs[MIPSInst_FT(ir)]);
1496
1497 MIPS_FPU_EMU_INC_STATS(stores);
1498
1499 SIFROMREG(val, MIPSInst_FS(ir));
1500 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1501 MIPS_FPU_EMU_INC_STATS(errors);
1502 *fault_addr = va;
1503 return SIGBUS;
1504 }
1505 if (put_user(val, va)) {
1506 MIPS_FPU_EMU_INC_STATS(errors);
1507 *fault_addr = va;
1508 return SIGSEGV;
1509 }
1510 break;
1511
1512 case madd_s_op:
1513 handler = fpemu_sp_madd;
1514 goto scoptop;
1515 case msub_s_op:
1516 handler = fpemu_sp_msub;
1517 goto scoptop;
1518 case nmadd_s_op:
1519 handler = fpemu_sp_nmadd;
1520 goto scoptop;
1521 case nmsub_s_op:
1522 handler = fpemu_sp_nmsub;
1523 goto scoptop;
1524
1525 scoptop:
1526 SPFROMREG(fr, MIPSInst_FR(ir));
1527 SPFROMREG(fs, MIPSInst_FS(ir));
1528 SPFROMREG(ft, MIPSInst_FT(ir));
1529 fd = (*handler) (fr, fs, ft);
1530 SPTOREG(fd, MIPSInst_FD(ir));
1531
1532 copcsr:
1533 if (ieee754_cxtest(IEEE754_INEXACT)) {
1534 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1535 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1536 }
1537 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1538 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1539 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1540 }
1541 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1542 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1543 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1544 }
1545 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1546 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1547 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1548 }
1549
1550 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1551 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1552 /*printk ("SIGFPE: FPU csr = %08x\n",
1553 ctx->fcr31); */
1554 return SIGFPE;
1555 }
1556
1557 break;
1558
1559 default:
1560 return SIGILL;
1561 }
1562 break;
1563 }
1564
1565 case d_fmt:{ /* 1 */
1566 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1567 union ieee754dp fd, fr, fs, ft;
1568 u64 __user *va;
1569 u64 val;
1570
1571 switch (MIPSInst_FUNC(ir)) {
1572 case ldxc1_op:
1573 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1574 xcp->regs[MIPSInst_FT(ir)]);
1575
1576 MIPS_FPU_EMU_INC_STATS(loads);
1577 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1578 MIPS_FPU_EMU_INC_STATS(errors);
1579 *fault_addr = va;
1580 return SIGBUS;
1581 }
1582 if (__get_user(val, va)) {
1583 MIPS_FPU_EMU_INC_STATS(errors);
1584 *fault_addr = va;
1585 return SIGSEGV;
1586 }
1587 DITOREG(val, MIPSInst_FD(ir));
1588 break;
1589
1590 case sdxc1_op:
1591 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1592 xcp->regs[MIPSInst_FT(ir)]);
1593
1594 MIPS_FPU_EMU_INC_STATS(stores);
1595 DIFROMREG(val, MIPSInst_FS(ir));
1596 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1597 MIPS_FPU_EMU_INC_STATS(errors);
1598 *fault_addr = va;
1599 return SIGBUS;
1600 }
1601 if (__put_user(val, va)) {
1602 MIPS_FPU_EMU_INC_STATS(errors);
1603 *fault_addr = va;
1604 return SIGSEGV;
1605 }
1606 break;
1607
1608 case madd_d_op:
1609 handler = fpemu_dp_madd;
1610 goto dcoptop;
1611 case msub_d_op:
1612 handler = fpemu_dp_msub;
1613 goto dcoptop;
1614 case nmadd_d_op:
1615 handler = fpemu_dp_nmadd;
1616 goto dcoptop;
1617 case nmsub_d_op:
1618 handler = fpemu_dp_nmsub;
1619 goto dcoptop;
1620
1621 dcoptop:
1622 DPFROMREG(fr, MIPSInst_FR(ir));
1623 DPFROMREG(fs, MIPSInst_FS(ir));
1624 DPFROMREG(ft, MIPSInst_FT(ir));
1625 fd = (*handler) (fr, fs, ft);
1626 DPTOREG(fd, MIPSInst_FD(ir));
1627 goto copcsr;
1628
1629 default:
1630 return SIGILL;
1631 }
1632 break;
1633 }
1634
1635 case 0x3:
1636 if (MIPSInst_FUNC(ir) != pfetch_op)
1637 return SIGILL;
1638
1639 /* ignore prefx operation */
1640 break;
1641
1642 default:
1643 return SIGILL;
1644 }
1645
1646 return 0;
1647 }
1648
1649
1650
1651 /*
1652 * Emulate a single COP1 arithmetic instruction.
1653 */
1654 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1655 mips_instruction ir)
1656 {
1657 int rfmt; /* resulting format */
1658 unsigned rcsr = 0; /* resulting csr */
1659 unsigned int oldrm;
1660 unsigned int cbit;
1661 unsigned cond;
1662 union {
1663 union ieee754dp d;
1664 union ieee754sp s;
1665 int w;
1666 s64 l;
1667 } rv; /* resulting value */
1668 u64 bits;
1669
1670 MIPS_FPU_EMU_INC_STATS(cp1ops);
1671 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1672 case s_fmt: { /* 0 */
1673 union {
1674 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1675 union ieee754sp(*u) (union ieee754sp);
1676 } handler;
1677 union ieee754sp fs, ft;
1678
1679 switch (MIPSInst_FUNC(ir)) {
1680 /* binary ops */
1681 case fadd_op:
1682 handler.b = ieee754sp_add;
1683 goto scopbop;
1684 case fsub_op:
1685 handler.b = ieee754sp_sub;
1686 goto scopbop;
1687 case fmul_op:
1688 handler.b = ieee754sp_mul;
1689 goto scopbop;
1690 case fdiv_op:
1691 handler.b = ieee754sp_div;
1692 goto scopbop;
1693
1694 /* unary ops */
1695 case fsqrt_op:
1696 if (!cpu_has_mips_2_3_4_5_r)
1697 return SIGILL;
1698
1699 handler.u = ieee754sp_sqrt;
1700 goto scopuop;
1701
1702 /*
1703 * Note that on some MIPS IV implementations such as the
1704 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1705 * achieve full IEEE-754 accuracy - however this emulator does.
1706 */
1707 case frsqrt_op:
1708 if (!cpu_has_mips_4_5_64_r2_r6)
1709 return SIGILL;
1710
1711 handler.u = fpemu_sp_rsqrt;
1712 goto scopuop;
1713
1714 case frecip_op:
1715 if (!cpu_has_mips_4_5_64_r2_r6)
1716 return SIGILL;
1717
1718 handler.u = fpemu_sp_recip;
1719 goto scopuop;
1720
1721 case fmovc_op:
1722 if (!cpu_has_mips_4_5_r)
1723 return SIGILL;
1724
1725 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1726 if (((ctx->fcr31 & cond) != 0) !=
1727 ((MIPSInst_FT(ir) & 1) != 0))
1728 return 0;
1729 SPFROMREG(rv.s, MIPSInst_FS(ir));
1730 break;
1731
1732 case fmovz_op:
1733 if (!cpu_has_mips_4_5_r)
1734 return SIGILL;
1735
1736 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1737 return 0;
1738 SPFROMREG(rv.s, MIPSInst_FS(ir));
1739 break;
1740
1741 case fmovn_op:
1742 if (!cpu_has_mips_4_5_r)
1743 return SIGILL;
1744
1745 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1746 return 0;
1747 SPFROMREG(rv.s, MIPSInst_FS(ir));
1748 break;
1749
1750 case fseleqz_op:
1751 if (!cpu_has_mips_r6)
1752 return SIGILL;
1753
1754 SPFROMREG(rv.s, MIPSInst_FT(ir));
1755 if (rv.w & 0x1)
1756 rv.w = 0;
1757 else
1758 SPFROMREG(rv.s, MIPSInst_FS(ir));
1759 break;
1760
1761 case fselnez_op:
1762 if (!cpu_has_mips_r6)
1763 return SIGILL;
1764
1765 SPFROMREG(rv.s, MIPSInst_FT(ir));
1766 if (rv.w & 0x1)
1767 SPFROMREG(rv.s, MIPSInst_FS(ir));
1768 else
1769 rv.w = 0;
1770 break;
1771
1772 case fmaddf_op: {
1773 union ieee754sp ft, fs, fd;
1774
1775 if (!cpu_has_mips_r6)
1776 return SIGILL;
1777
1778 SPFROMREG(ft, MIPSInst_FT(ir));
1779 SPFROMREG(fs, MIPSInst_FS(ir));
1780 SPFROMREG(fd, MIPSInst_FD(ir));
1781 rv.s = ieee754sp_maddf(fd, fs, ft);
1782 break;
1783 }
1784
1785 case fmsubf_op: {
1786 union ieee754sp ft, fs, fd;
1787
1788 if (!cpu_has_mips_r6)
1789 return SIGILL;
1790
1791 SPFROMREG(ft, MIPSInst_FT(ir));
1792 SPFROMREG(fs, MIPSInst_FS(ir));
1793 SPFROMREG(fd, MIPSInst_FD(ir));
1794 rv.s = ieee754sp_msubf(fd, fs, ft);
1795 break;
1796 }
1797
1798 case frint_op: {
1799 union ieee754sp fs;
1800
1801 if (!cpu_has_mips_r6)
1802 return SIGILL;
1803
1804 SPFROMREG(fs, MIPSInst_FS(ir));
1805 rv.l = ieee754sp_tlong(fs);
1806 rv.s = ieee754sp_flong(rv.l);
1807 goto copcsr;
1808 }
1809
1810 case fclass_op: {
1811 union ieee754sp fs;
1812
1813 if (!cpu_has_mips_r6)
1814 return SIGILL;
1815
1816 SPFROMREG(fs, MIPSInst_FS(ir));
1817 rv.w = ieee754sp_2008class(fs);
1818 rfmt = w_fmt;
1819 break;
1820 }
1821
1822 case fmin_op: {
1823 union ieee754sp fs, ft;
1824
1825 if (!cpu_has_mips_r6)
1826 return SIGILL;
1827
1828 SPFROMREG(ft, MIPSInst_FT(ir));
1829 SPFROMREG(fs, MIPSInst_FS(ir));
1830 rv.s = ieee754sp_fmin(fs, ft);
1831 break;
1832 }
1833
1834 case fmina_op: {
1835 union ieee754sp fs, ft;
1836
1837 if (!cpu_has_mips_r6)
1838 return SIGILL;
1839
1840 SPFROMREG(ft, MIPSInst_FT(ir));
1841 SPFROMREG(fs, MIPSInst_FS(ir));
1842 rv.s = ieee754sp_fmina(fs, ft);
1843 break;
1844 }
1845
1846 case fmax_op: {
1847 union ieee754sp fs, ft;
1848
1849 if (!cpu_has_mips_r6)
1850 return SIGILL;
1851
1852 SPFROMREG(ft, MIPSInst_FT(ir));
1853 SPFROMREG(fs, MIPSInst_FS(ir));
1854 rv.s = ieee754sp_fmax(fs, ft);
1855 break;
1856 }
1857
1858 case fmaxa_op: {
1859 union ieee754sp fs, ft;
1860
1861 if (!cpu_has_mips_r6)
1862 return SIGILL;
1863
1864 SPFROMREG(ft, MIPSInst_FT(ir));
1865 SPFROMREG(fs, MIPSInst_FS(ir));
1866 rv.s = ieee754sp_fmaxa(fs, ft);
1867 break;
1868 }
1869
1870 case fabs_op:
1871 handler.u = ieee754sp_abs;
1872 goto scopuop;
1873
1874 case fneg_op:
1875 handler.u = ieee754sp_neg;
1876 goto scopuop;
1877
1878 case fmov_op:
1879 /* an easy one */
1880 SPFROMREG(rv.s, MIPSInst_FS(ir));
1881 goto copcsr;
1882
1883 /* binary op on handler */
1884 scopbop:
1885 SPFROMREG(fs, MIPSInst_FS(ir));
1886 SPFROMREG(ft, MIPSInst_FT(ir));
1887
1888 rv.s = (*handler.b) (fs, ft);
1889 goto copcsr;
1890 scopuop:
1891 SPFROMREG(fs, MIPSInst_FS(ir));
1892 rv.s = (*handler.u) (fs);
1893 goto copcsr;
1894 copcsr:
1895 if (ieee754_cxtest(IEEE754_INEXACT)) {
1896 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1897 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1898 }
1899 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1900 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1901 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1902 }
1903 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1904 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1905 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1906 }
1907 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1908 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1909 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1910 }
1911 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1912 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1913 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1914 }
1915 break;
1916
1917 /* unary conv ops */
1918 case fcvts_op:
1919 return SIGILL; /* not defined */
1920
1921 case fcvtd_op:
1922 SPFROMREG(fs, MIPSInst_FS(ir));
1923 rv.d = ieee754dp_fsp(fs);
1924 rfmt = d_fmt;
1925 goto copcsr;
1926
1927 case fcvtw_op:
1928 SPFROMREG(fs, MIPSInst_FS(ir));
1929 rv.w = ieee754sp_tint(fs);
1930 rfmt = w_fmt;
1931 goto copcsr;
1932
1933 case fround_op:
1934 case ftrunc_op:
1935 case fceil_op:
1936 case ffloor_op:
1937 if (!cpu_has_mips_2_3_4_5_r)
1938 return SIGILL;
1939
1940 oldrm = ieee754_csr.rm;
1941 SPFROMREG(fs, MIPSInst_FS(ir));
1942 ieee754_csr.rm = MIPSInst_FUNC(ir);
1943 rv.w = ieee754sp_tint(fs);
1944 ieee754_csr.rm = oldrm;
1945 rfmt = w_fmt;
1946 goto copcsr;
1947
1948 case fcvtl_op:
1949 if (!cpu_has_mips_3_4_5_64_r2_r6)
1950 return SIGILL;
1951
1952 SPFROMREG(fs, MIPSInst_FS(ir));
1953 rv.l = ieee754sp_tlong(fs);
1954 rfmt = l_fmt;
1955 goto copcsr;
1956
1957 case froundl_op:
1958 case ftruncl_op:
1959 case fceill_op:
1960 case ffloorl_op:
1961 if (!cpu_has_mips_3_4_5_64_r2_r6)
1962 return SIGILL;
1963
1964 oldrm = ieee754_csr.rm;
1965 SPFROMREG(fs, MIPSInst_FS(ir));
1966 ieee754_csr.rm = MIPSInst_FUNC(ir);
1967 rv.l = ieee754sp_tlong(fs);
1968 ieee754_csr.rm = oldrm;
1969 rfmt = l_fmt;
1970 goto copcsr;
1971
1972 default:
1973 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1974 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1975 union ieee754sp fs, ft;
1976
1977 SPFROMREG(fs, MIPSInst_FS(ir));
1978 SPFROMREG(ft, MIPSInst_FT(ir));
1979 rv.w = ieee754sp_cmp(fs, ft,
1980 cmptab[cmpop & 0x7], cmpop & 0x8);
1981 rfmt = -1;
1982 if ((cmpop & 0x8) && ieee754_cxtest
1983 (IEEE754_INVALID_OPERATION))
1984 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1985 else
1986 goto copcsr;
1987
1988 } else
1989 return SIGILL;
1990 break;
1991 }
1992 break;
1993 }
1994
1995 case d_fmt: {
1996 union ieee754dp fs, ft;
1997 union {
1998 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1999 union ieee754dp(*u) (union ieee754dp);
2000 } handler;
2001
2002 switch (MIPSInst_FUNC(ir)) {
2003 /* binary ops */
2004 case fadd_op:
2005 handler.b = ieee754dp_add;
2006 goto dcopbop;
2007 case fsub_op:
2008 handler.b = ieee754dp_sub;
2009 goto dcopbop;
2010 case fmul_op:
2011 handler.b = ieee754dp_mul;
2012 goto dcopbop;
2013 case fdiv_op:
2014 handler.b = ieee754dp_div;
2015 goto dcopbop;
2016
2017 /* unary ops */
2018 case fsqrt_op:
2019 if (!cpu_has_mips_2_3_4_5_r)
2020 return SIGILL;
2021
2022 handler.u = ieee754dp_sqrt;
2023 goto dcopuop;
2024 /*
2025 * Note that on some MIPS IV implementations such as the
2026 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2027 * achieve full IEEE-754 accuracy - however this emulator does.
2028 */
2029 case frsqrt_op:
2030 if (!cpu_has_mips_4_5_64_r2_r6)
2031 return SIGILL;
2032
2033 handler.u = fpemu_dp_rsqrt;
2034 goto dcopuop;
2035 case frecip_op:
2036 if (!cpu_has_mips_4_5_64_r2_r6)
2037 return SIGILL;
2038
2039 handler.u = fpemu_dp_recip;
2040 goto dcopuop;
2041 case fmovc_op:
2042 if (!cpu_has_mips_4_5_r)
2043 return SIGILL;
2044
2045 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2046 if (((ctx->fcr31 & cond) != 0) !=
2047 ((MIPSInst_FT(ir) & 1) != 0))
2048 return 0;
2049 DPFROMREG(rv.d, MIPSInst_FS(ir));
2050 break;
2051 case fmovz_op:
2052 if (!cpu_has_mips_4_5_r)
2053 return SIGILL;
2054
2055 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2056 return 0;
2057 DPFROMREG(rv.d, MIPSInst_FS(ir));
2058 break;
2059 case fmovn_op:
2060 if (!cpu_has_mips_4_5_r)
2061 return SIGILL;
2062
2063 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2064 return 0;
2065 DPFROMREG(rv.d, MIPSInst_FS(ir));
2066 break;
2067
2068 case fseleqz_op:
2069 if (!cpu_has_mips_r6)
2070 return SIGILL;
2071
2072 DPFROMREG(rv.d, MIPSInst_FT(ir));
2073 if (rv.l & 0x1)
2074 rv.l = 0;
2075 else
2076 DPFROMREG(rv.d, MIPSInst_FS(ir));
2077 break;
2078
2079 case fselnez_op:
2080 if (!cpu_has_mips_r6)
2081 return SIGILL;
2082
2083 DPFROMREG(rv.d, MIPSInst_FT(ir));
2084 if (rv.l & 0x1)
2085 DPFROMREG(rv.d, MIPSInst_FS(ir));
2086 else
2087 rv.l = 0;
2088 break;
2089
2090 case fmaddf_op: {
2091 union ieee754dp ft, fs, fd;
2092
2093 if (!cpu_has_mips_r6)
2094 return SIGILL;
2095
2096 DPFROMREG(ft, MIPSInst_FT(ir));
2097 DPFROMREG(fs, MIPSInst_FS(ir));
2098 DPFROMREG(fd, MIPSInst_FD(ir));
2099 rv.d = ieee754dp_maddf(fd, fs, ft);
2100 break;
2101 }
2102
2103 case fmsubf_op: {
2104 union ieee754dp ft, fs, fd;
2105
2106 if (!cpu_has_mips_r6)
2107 return SIGILL;
2108
2109 DPFROMREG(ft, MIPSInst_FT(ir));
2110 DPFROMREG(fs, MIPSInst_FS(ir));
2111 DPFROMREG(fd, MIPSInst_FD(ir));
2112 rv.d = ieee754dp_msubf(fd, fs, ft);
2113 break;
2114 }
2115
2116 case frint_op: {
2117 union ieee754dp fs;
2118
2119 if (!cpu_has_mips_r6)
2120 return SIGILL;
2121
2122 DPFROMREG(fs, MIPSInst_FS(ir));
2123 rv.l = ieee754dp_tlong(fs);
2124 rv.d = ieee754dp_flong(rv.l);
2125 goto copcsr;
2126 }
2127
2128 case fclass_op: {
2129 union ieee754dp fs;
2130
2131 if (!cpu_has_mips_r6)
2132 return SIGILL;
2133
2134 DPFROMREG(fs, MIPSInst_FS(ir));
2135 rv.w = ieee754dp_2008class(fs);
2136 rfmt = w_fmt;
2137 break;
2138 }
2139
2140 case fmin_op: {
2141 union ieee754dp fs, ft;
2142
2143 if (!cpu_has_mips_r6)
2144 return SIGILL;
2145
2146 DPFROMREG(ft, MIPSInst_FT(ir));
2147 DPFROMREG(fs, MIPSInst_FS(ir));
2148 rv.d = ieee754dp_fmin(fs, ft);
2149 break;
2150 }
2151
2152 case fmina_op: {
2153 union ieee754dp fs, ft;
2154
2155 if (!cpu_has_mips_r6)
2156 return SIGILL;
2157
2158 DPFROMREG(ft, MIPSInst_FT(ir));
2159 DPFROMREG(fs, MIPSInst_FS(ir));
2160 rv.d = ieee754dp_fmina(fs, ft);
2161 break;
2162 }
2163
2164 case fmax_op: {
2165 union ieee754dp fs, ft;
2166
2167 if (!cpu_has_mips_r6)
2168 return SIGILL;
2169
2170 DPFROMREG(ft, MIPSInst_FT(ir));
2171 DPFROMREG(fs, MIPSInst_FS(ir));
2172 rv.d = ieee754dp_fmax(fs, ft);
2173 break;
2174 }
2175
2176 case fmaxa_op: {
2177 union ieee754dp fs, ft;
2178
2179 if (!cpu_has_mips_r6)
2180 return SIGILL;
2181
2182 DPFROMREG(ft, MIPSInst_FT(ir));
2183 DPFROMREG(fs, MIPSInst_FS(ir));
2184 rv.d = ieee754dp_fmaxa(fs, ft);
2185 break;
2186 }
2187
2188 case fabs_op:
2189 handler.u = ieee754dp_abs;
2190 goto dcopuop;
2191
2192 case fneg_op:
2193 handler.u = ieee754dp_neg;
2194 goto dcopuop;
2195
2196 case fmov_op:
2197 /* an easy one */
2198 DPFROMREG(rv.d, MIPSInst_FS(ir));
2199 goto copcsr;
2200
2201 /* binary op on handler */
2202 dcopbop:
2203 DPFROMREG(fs, MIPSInst_FS(ir));
2204 DPFROMREG(ft, MIPSInst_FT(ir));
2205
2206 rv.d = (*handler.b) (fs, ft);
2207 goto copcsr;
2208 dcopuop:
2209 DPFROMREG(fs, MIPSInst_FS(ir));
2210 rv.d = (*handler.u) (fs);
2211 goto copcsr;
2212
2213 /*
2214 * unary conv ops
2215 */
2216 case fcvts_op:
2217 DPFROMREG(fs, MIPSInst_FS(ir));
2218 rv.s = ieee754sp_fdp(fs);
2219 rfmt = s_fmt;
2220 goto copcsr;
2221
2222 case fcvtd_op:
2223 return SIGILL; /* not defined */
2224
2225 case fcvtw_op:
2226 DPFROMREG(fs, MIPSInst_FS(ir));
2227 rv.w = ieee754dp_tint(fs); /* wrong */
2228 rfmt = w_fmt;
2229 goto copcsr;
2230
2231 case fround_op:
2232 case ftrunc_op:
2233 case fceil_op:
2234 case ffloor_op:
2235 if (!cpu_has_mips_2_3_4_5_r)
2236 return SIGILL;
2237
2238 oldrm = ieee754_csr.rm;
2239 DPFROMREG(fs, MIPSInst_FS(ir));
2240 ieee754_csr.rm = MIPSInst_FUNC(ir);
2241 rv.w = ieee754dp_tint(fs);
2242 ieee754_csr.rm = oldrm;
2243 rfmt = w_fmt;
2244 goto copcsr;
2245
2246 case fcvtl_op:
2247 if (!cpu_has_mips_3_4_5_64_r2_r6)
2248 return SIGILL;
2249
2250 DPFROMREG(fs, MIPSInst_FS(ir));
2251 rv.l = ieee754dp_tlong(fs);
2252 rfmt = l_fmt;
2253 goto copcsr;
2254
2255 case froundl_op:
2256 case ftruncl_op:
2257 case fceill_op:
2258 case ffloorl_op:
2259 if (!cpu_has_mips_3_4_5_64_r2_r6)
2260 return SIGILL;
2261
2262 oldrm = ieee754_csr.rm;
2263 DPFROMREG(fs, MIPSInst_FS(ir));
2264 ieee754_csr.rm = MIPSInst_FUNC(ir);
2265 rv.l = ieee754dp_tlong(fs);
2266 ieee754_csr.rm = oldrm;
2267 rfmt = l_fmt;
2268 goto copcsr;
2269
2270 default:
2271 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2272 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2273 union ieee754dp fs, ft;
2274
2275 DPFROMREG(fs, MIPSInst_FS(ir));
2276 DPFROMREG(ft, MIPSInst_FT(ir));
2277 rv.w = ieee754dp_cmp(fs, ft,
2278 cmptab[cmpop & 0x7], cmpop & 0x8);
2279 rfmt = -1;
2280 if ((cmpop & 0x8)
2281 &&
2282 ieee754_cxtest
2283 (IEEE754_INVALID_OPERATION))
2284 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2285 else
2286 goto copcsr;
2287
2288 }
2289 else {
2290 return SIGILL;
2291 }
2292 break;
2293 }
2294 break;
2295 }
2296
2297 case w_fmt: {
2298 union ieee754dp fs;
2299
2300 switch (MIPSInst_FUNC(ir)) {
2301 case fcvts_op:
2302 /* convert word to single precision real */
2303 SPFROMREG(fs, MIPSInst_FS(ir));
2304 rv.s = ieee754sp_fint(fs.bits);
2305 rfmt = s_fmt;
2306 goto copcsr;
2307 case fcvtd_op:
2308 /* convert word to double precision real */
2309 SPFROMREG(fs, MIPSInst_FS(ir));
2310 rv.d = ieee754dp_fint(fs.bits);
2311 rfmt = d_fmt;
2312 goto copcsr;
2313 default: {
2314 /* Emulating the new CMP.condn.fmt R6 instruction */
2315 #define CMPOP_MASK 0x7
2316 #define SIGN_BIT (0x1 << 3)
2317 #define PREDICATE_BIT (0x1 << 4)
2318
2319 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2320 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2321 union ieee754sp fs, ft;
2322
2323 /* This is an R6 only instruction */
2324 if (!cpu_has_mips_r6 ||
2325 (MIPSInst_FUNC(ir) & 0x20))
2326 return SIGILL;
2327
2328 /* fmt is w_fmt for single precision so fix it */
2329 rfmt = s_fmt;
2330 /* default to false */
2331 rv.w = 0;
2332
2333 /* CMP.condn.S */
2334 SPFROMREG(fs, MIPSInst_FS(ir));
2335 SPFROMREG(ft, MIPSInst_FT(ir));
2336
2337 /* positive predicates */
2338 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2339 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2340 sig))
2341 rv.w = -1; /* true, all 1s */
2342 if ((sig) &&
2343 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2344 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2345 else
2346 goto copcsr;
2347 } else {
2348 /* negative predicates */
2349 switch (cmpop) {
2350 case 1:
2351 case 2:
2352 case 3:
2353 if (ieee754sp_cmp(fs, ft,
2354 negative_cmptab[cmpop],
2355 sig))
2356 rv.w = -1; /* true, all 1s */
2357 if (sig &&
2358 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2359 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2360 else
2361 goto copcsr;
2362 break;
2363 default:
2364 /* Reserved R6 ops */
2365 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2366 return SIGILL;
2367 }
2368 }
2369 break;
2370 }
2371 }
2372 }
2373
2374 case l_fmt:
2375
2376 if (!cpu_has_mips_3_4_5_64_r2_r6)
2377 return SIGILL;
2378
2379 DIFROMREG(bits, MIPSInst_FS(ir));
2380
2381 switch (MIPSInst_FUNC(ir)) {
2382 case fcvts_op:
2383 /* convert long to single precision real */
2384 rv.s = ieee754sp_flong(bits);
2385 rfmt = s_fmt;
2386 goto copcsr;
2387 case fcvtd_op:
2388 /* convert long to double precision real */
2389 rv.d = ieee754dp_flong(bits);
2390 rfmt = d_fmt;
2391 goto copcsr;
2392 default: {
2393 /* Emulating the new CMP.condn.fmt R6 instruction */
2394 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2395 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2396 union ieee754dp fs, ft;
2397
2398 if (!cpu_has_mips_r6 ||
2399 (MIPSInst_FUNC(ir) & 0x20))
2400 return SIGILL;
2401
2402 /* fmt is l_fmt for double precision so fix it */
2403 rfmt = d_fmt;
2404 /* default to false */
2405 rv.l = 0;
2406
2407 /* CMP.condn.D */
2408 DPFROMREG(fs, MIPSInst_FS(ir));
2409 DPFROMREG(ft, MIPSInst_FT(ir));
2410
2411 /* positive predicates */
2412 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2413 if (ieee754dp_cmp(fs, ft,
2414 cmptab[cmpop], sig))
2415 rv.l = -1LL; /* true, all 1s */
2416 if (sig &&
2417 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2418 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2419 else
2420 goto copcsr;
2421 } else {
2422 /* negative predicates */
2423 switch (cmpop) {
2424 case 1:
2425 case 2:
2426 case 3:
2427 if (ieee754dp_cmp(fs, ft,
2428 negative_cmptab[cmpop],
2429 sig))
2430 rv.l = -1LL; /* true, all 1s */
2431 if (sig &&
2432 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2433 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2434 else
2435 goto copcsr;
2436 break;
2437 default:
2438 /* Reserved R6 ops */
2439 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2440 return SIGILL;
2441 }
2442 }
2443 break;
2444 }
2445 }
2446 default:
2447 return SIGILL;
2448 }
2449
2450 /*
2451 * Update the fpu CSR register for this operation.
2452 * If an exception is required, generate a tidy SIGFPE exception,
2453 * without updating the result register.
2454 * Note: cause exception bits do not accumulate, they are rewritten
2455 * for each op; only the flag/sticky bits accumulate.
2456 */
2457 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2458 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2459 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2460 return SIGFPE;
2461 }
2462
2463 /*
2464 * Now we can safely write the result back to the register file.
2465 */
2466 switch (rfmt) {
2467 case -1:
2468
2469 if (cpu_has_mips_4_5_r)
2470 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2471 else
2472 cbit = FPU_CSR_COND;
2473 if (rv.w)
2474 ctx->fcr31 |= cbit;
2475 else
2476 ctx->fcr31 &= ~cbit;
2477 break;
2478
2479 case d_fmt:
2480 DPTOREG(rv.d, MIPSInst_FD(ir));
2481 break;
2482 case s_fmt:
2483 SPTOREG(rv.s, MIPSInst_FD(ir));
2484 break;
2485 case w_fmt:
2486 SITOREG(rv.w, MIPSInst_FD(ir));
2487 break;
2488 case l_fmt:
2489 if (!cpu_has_mips_3_4_5_64_r2_r6)
2490 return SIGILL;
2491
2492 DITOREG(rv.l, MIPSInst_FD(ir));
2493 break;
2494 default:
2495 return SIGILL;
2496 }
2497
2498 return 0;
2499 }
2500
2501 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2502 int has_fpu, void *__user *fault_addr)
2503 {
2504 unsigned long oldepc, prevepc;
2505 struct mm_decoded_insn dec_insn;
2506 u16 instr[4];
2507 u16 *instr_ptr;
2508 int sig = 0;
2509
2510 oldepc = xcp->cp0_epc;
2511 do {
2512 prevepc = xcp->cp0_epc;
2513
2514 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2515 /*
2516 * Get next 2 microMIPS instructions and convert them
2517 * into 32-bit instructions.
2518 */
2519 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2520 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2521 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2522 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2523 MIPS_FPU_EMU_INC_STATS(errors);
2524 return SIGBUS;
2525 }
2526 instr_ptr = instr;
2527
2528 /* Get first instruction. */
2529 if (mm_insn_16bit(*instr_ptr)) {
2530 /* Duplicate the half-word. */
2531 dec_insn.insn = (*instr_ptr << 16) |
2532 (*instr_ptr);
2533 /* 16-bit instruction. */
2534 dec_insn.pc_inc = 2;
2535 instr_ptr += 1;
2536 } else {
2537 dec_insn.insn = (*instr_ptr << 16) |
2538 *(instr_ptr+1);
2539 /* 32-bit instruction. */
2540 dec_insn.pc_inc = 4;
2541 instr_ptr += 2;
2542 }
2543 /* Get second instruction. */
2544 if (mm_insn_16bit(*instr_ptr)) {
2545 /* Duplicate the half-word. */
2546 dec_insn.next_insn = (*instr_ptr << 16) |
2547 (*instr_ptr);
2548 /* 16-bit instruction. */
2549 dec_insn.next_pc_inc = 2;
2550 } else {
2551 dec_insn.next_insn = (*instr_ptr << 16) |
2552 *(instr_ptr+1);
2553 /* 32-bit instruction. */
2554 dec_insn.next_pc_inc = 4;
2555 }
2556 dec_insn.micro_mips_mode = 1;
2557 } else {
2558 if ((get_user(dec_insn.insn,
2559 (mips_instruction __user *) xcp->cp0_epc)) ||
2560 (get_user(dec_insn.next_insn,
2561 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2562 MIPS_FPU_EMU_INC_STATS(errors);
2563 return SIGBUS;
2564 }
2565 dec_insn.pc_inc = 4;
2566 dec_insn.next_pc_inc = 4;
2567 dec_insn.micro_mips_mode = 0;
2568 }
2569
2570 if ((dec_insn.insn == 0) ||
2571 ((dec_insn.pc_inc == 2) &&
2572 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2573 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2574 else {
2575 /*
2576 * The 'ieee754_csr' is an alias of ctx->fcr31.
2577 * No need to copy ctx->fcr31 to ieee754_csr.
2578 */
2579 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2580 }
2581
2582 if (has_fpu)
2583 break;
2584 if (sig)
2585 break;
2586
2587 cond_resched();
2588 } while (xcp->cp0_epc > prevepc);
2589
2590 /* SIGILL indicates a non-fpu instruction */
2591 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2592 /* but if EPC has advanced, then ignore it */
2593 sig = 0;
2594
2595 return sig;
2596 }
Linux kernel - Deliverables
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