2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 * http://www.algor.co.uk
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * A complete emulator for MIPS coprocessor 1 instructions. This is
25 * required for #float(switch) or #float(trap), where it catches all
26 * COP1 instructions via the "CoProcessor Unusable" exception.
28 * More surprisingly it is also required for #float(ieee), to help out
29 * the hardware fpu at the boundaries of the IEEE-754 representation
30 * (denormalised values, infinities, underflow, etc). It is made
31 * quite nasty because emulation of some non-COP1 instructions is
32 * required, e.g. in branch delay slots.
34 * Note if you know that you won't have an fpu, then you'll get much
35 * better performance by compiling with -msoft-float!
37 #include <linux/sched.h>
38 #include <linux/module.h>
39 #include <linux/debugfs.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
48 #include <asm/uaccess.h>
49 #include <asm/branch.h>
53 /* Strap kernel emulator for full MIPS IV emulation */
60 /* Function which emulates a floating point instruction. */
62 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
65 #if __mips >= 4 && __mips != 32
66 static int fpux_emu(struct pt_regs
*,
67 struct mips_fpu_struct
*, mips_instruction
);
70 /* Further private data for which no space exists in mips_fpu_struct */
72 #ifdef CONFIG_DEBUG_FS
73 DEFINE_PER_CPU(struct mips_fpu_emulator_stats
, fpuemustats
);
76 /* Control registers */
78 #define FPCREG_RID 0 /* $0 = revision id */
79 #define FPCREG_CSR 31 /* $31 = csr */
81 /* Determine rounding mode from the RM bits of the FCSR */
82 #define modeindex(v) ((v) & FPU_CSR_RM)
84 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
85 static const unsigned char ieee_rm
[4] = {
86 [FPU_CSR_RN
] = IEEE754_RN
,
87 [FPU_CSR_RZ
] = IEEE754_RZ
,
88 [FPU_CSR_RU
] = IEEE754_RU
,
89 [FPU_CSR_RD
] = IEEE754_RD
,
91 /* Convert IEEE library modes to Mips rounding mode (0..3). */
92 static const unsigned char mips_rm
[4] = {
93 [IEEE754_RN
] = FPU_CSR_RN
,
94 [IEEE754_RZ
] = FPU_CSR_RZ
,
95 [IEEE754_RD
] = FPU_CSR_RD
,
96 [IEEE754_RU
] = FPU_CSR_RU
,
100 /* convert condition code register number to csr bit */
101 static const unsigned int fpucondbit
[8] = {
115 * Redundant with logic already in kernel/branch.c,
116 * embedded in compute_return_epc. At some point,
117 * a single subroutine should be used across both
120 static int isBranchInstr(mips_instruction
* i
)
122 switch (MIPSInst_OPCODE(*i
)) {
124 switch (MIPSInst_FUNC(*i
)) {
132 switch (MIPSInst_RT(*i
)) {
162 if (MIPSInst_RS(*i
) == bc_op
)
171 * In the Linux kernel, we support selection of FPR format on the
172 * basis of the Status.FR bit. If an FPU is not present, the FR bit
173 * is hardwired to zero, which would imply a 32-bit FPU even for
174 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
175 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
176 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
177 * even FPRs are used (Status.FR = 0).
179 static inline int cop1_64bit(struct pt_regs
*xcp
)
182 return xcp
->cp0_status
& ST0_FR
;
184 return !test_thread_flag(TIF_32BIT_REGS
);
190 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
191 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
193 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
194 cop1_64bit(xcp) || !(x & 1) ? \
195 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
196 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
198 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
199 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
201 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
202 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
203 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
204 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
207 * Emulate the single floating point instruction pointed at by EPC.
208 * Two instructions if the instruction is in a branch delay slot.
211 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
)
214 unsigned long emulpc
, contpc
;
217 if (get_user(ir
, (mips_instruction __user
*) xcp
->cp0_epc
)) {
218 MIPS_FPU_EMU_INC_STATS(errors
);
222 /* XXX NEC Vr54xx bug workaround */
223 if ((xcp
->cp0_cause
& CAUSEF_BD
) && !isBranchInstr(&ir
))
224 xcp
->cp0_cause
&= ~CAUSEF_BD
;
226 if (xcp
->cp0_cause
& CAUSEF_BD
) {
228 * The instruction to be emulated is in a branch delay slot
229 * which means that we have to emulate the branch instruction
230 * BEFORE we do the cop1 instruction.
232 * This branch could be a COP1 branch, but in that case we
233 * would have had a trap for that instruction, and would not
234 * come through this route.
236 * Linux MIPS branch emulator operates on context, updating the
239 emulpc
= xcp
->cp0_epc
+ 4; /* Snapshot emulation target */
241 if (__compute_return_epc(xcp
)) {
243 printk("failed to emulate branch at %p\n",
244 (void *) (xcp
->cp0_epc
));
248 if (get_user(ir
, (mips_instruction __user
*) emulpc
)) {
249 MIPS_FPU_EMU_INC_STATS(errors
);
252 /* __compute_return_epc() will have updated cp0_epc */
253 contpc
= xcp
->cp0_epc
;
254 /* In order not to confuse ptrace() et al, tweak context */
255 xcp
->cp0_epc
= emulpc
- 4;
257 emulpc
= xcp
->cp0_epc
;
258 contpc
= xcp
->cp0_epc
+ 4;
262 MIPS_FPU_EMU_INC_STATS(emulated
);
263 switch (MIPSInst_OPCODE(ir
)) {
265 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
269 MIPS_FPU_EMU_INC_STATS(loads
);
270 if (get_user(val
, va
)) {
271 MIPS_FPU_EMU_INC_STATS(errors
);
274 DITOREG(val
, MIPSInst_RT(ir
));
279 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
283 MIPS_FPU_EMU_INC_STATS(stores
);
284 DIFROMREG(val
, MIPSInst_RT(ir
));
285 if (put_user(val
, va
)) {
286 MIPS_FPU_EMU_INC_STATS(errors
);
293 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
297 MIPS_FPU_EMU_INC_STATS(loads
);
298 if (get_user(val
, va
)) {
299 MIPS_FPU_EMU_INC_STATS(errors
);
302 SITOREG(val
, MIPSInst_RT(ir
));
307 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
311 MIPS_FPU_EMU_INC_STATS(stores
);
312 SIFROMREG(val
, MIPSInst_RT(ir
));
313 if (put_user(val
, va
)) {
314 MIPS_FPU_EMU_INC_STATS(errors
);
321 switch (MIPSInst_RS(ir
)) {
323 #if defined(__mips64)
325 /* copregister fs -> gpr[rt] */
326 if (MIPSInst_RT(ir
) != 0) {
327 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
333 /* copregister fs <- rt */
334 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
339 /* copregister rd -> gpr[rt] */
340 if (MIPSInst_RT(ir
) != 0) {
341 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
347 /* copregister rd <- rt */
348 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
352 /* cop control register rd -> gpr[rt] */
355 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
357 value
= (value
& ~FPU_CSR_RM
) |
358 mips_rm
[modeindex(value
)];
360 printk("%p gpr[%d]<-csr=%08x\n",
361 (void *) (xcp
->cp0_epc
),
362 MIPSInst_RT(ir
), value
);
365 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
370 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
375 /* copregister rd <- rt */
378 if (MIPSInst_RT(ir
) == 0)
381 value
= xcp
->regs
[MIPSInst_RT(ir
)];
383 /* we only have one writable control reg
385 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
387 printk("%p gpr[%d]->csr=%08x\n",
388 (void *) (xcp
->cp0_epc
),
389 MIPSInst_RT(ir
), value
);
393 * Don't write reserved bits,
394 * and convert to ieee library modes
396 ctx
->fcr31
= (value
&
397 ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
398 ieee_rm
[modeindex(value
)];
400 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
409 if (xcp
->cp0_cause
& CAUSEF_BD
)
413 cond
= ctx
->fcr31
& fpucondbit
[MIPSInst_RT(ir
) >> 2];
415 cond
= ctx
->fcr31
& FPU_CSR_COND
;
417 switch (MIPSInst_RT(ir
) & 3) {
428 /* thats an illegal instruction */
432 xcp
->cp0_cause
|= CAUSEF_BD
;
434 /* branch taken: emulate dslot
438 contpc
= (xcp
->cp0_epc
+
439 (MIPSInst_SIMM(ir
) << 2));
442 (mips_instruction __user
*) xcp
->cp0_epc
)) {
443 MIPS_FPU_EMU_INC_STATS(errors
);
447 switch (MIPSInst_OPCODE(ir
)) {
450 #if (__mips >= 2 || defined(__mips64))
455 #if __mips >= 4 && __mips != 32
458 /* its one of ours */
462 if (MIPSInst_FUNC(ir
) == movc_op
)
469 * Single step the non-cp1
470 * instruction in the dslot
472 return mips_dsemul(xcp
, ir
, contpc
);
475 /* branch not taken */
478 * branch likely nullifies
484 * else continue & execute
485 * dslot as normal insn
493 if (!(MIPSInst_RS(ir
) & 0x10))
498 /* a real fpu computation instruction */
499 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
505 #if __mips >= 4 && __mips != 32
509 if ((sig
= fpux_emu(xcp
, ctx
, ir
)))
517 if (MIPSInst_FUNC(ir
) != movc_op
)
519 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
520 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
521 xcp
->regs
[MIPSInst_RD(ir
)] =
522 xcp
->regs
[MIPSInst_RS(ir
)];
531 xcp
->cp0_epc
= contpc
;
532 xcp
->cp0_cause
&= ~CAUSEF_BD
;
538 * Conversion table from MIPS compare ops 48-63
539 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
541 static const unsigned char cmptab
[8] = {
542 0, /* cmp_0 (sig) cmp_sf */
543 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
544 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
545 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
546 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
547 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
548 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
549 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
553 #if __mips >= 4 && __mips != 32
556 * Additional MIPS4 instructions
559 #define DEF3OP(name, p, f1, f2, f3) \
560 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
563 struct _ieee754_csr ieee754_csr_save; \
565 ieee754_csr_save = ieee754_csr; \
567 ieee754_csr_save.cx |= ieee754_csr.cx; \
568 ieee754_csr_save.sx |= ieee754_csr.sx; \
570 ieee754_csr.cx |= ieee754_csr_save.cx; \
571 ieee754_csr.sx |= ieee754_csr_save.sx; \
575 static ieee754dp
fpemu_dp_recip(ieee754dp d
)
577 return ieee754dp_div(ieee754dp_one(0), d
);
580 static ieee754dp
fpemu_dp_rsqrt(ieee754dp d
)
582 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
585 static ieee754sp
fpemu_sp_recip(ieee754sp s
)
587 return ieee754sp_div(ieee754sp_one(0), s
);
590 static ieee754sp
fpemu_sp_rsqrt(ieee754sp s
)
592 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
595 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
596 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
597 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
598 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
599 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
600 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
601 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
602 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
604 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
607 unsigned rcsr
= 0; /* resulting csr */
609 MIPS_FPU_EMU_INC_STATS(cp1xops
);
611 switch (MIPSInst_FMA_FFMT(ir
)) {
614 ieee754sp(*handler
) (ieee754sp
, ieee754sp
, ieee754sp
);
615 ieee754sp fd
, fr
, fs
, ft
;
619 switch (MIPSInst_FUNC(ir
)) {
621 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
622 xcp
->regs
[MIPSInst_FT(ir
)]);
624 MIPS_FPU_EMU_INC_STATS(loads
);
625 if (get_user(val
, va
)) {
626 MIPS_FPU_EMU_INC_STATS(errors
);
629 SITOREG(val
, MIPSInst_FD(ir
));
633 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
634 xcp
->regs
[MIPSInst_FT(ir
)]);
636 MIPS_FPU_EMU_INC_STATS(stores
);
638 SIFROMREG(val
, MIPSInst_FS(ir
));
639 if (put_user(val
, va
)) {
640 MIPS_FPU_EMU_INC_STATS(errors
);
646 handler
= fpemu_sp_madd
;
649 handler
= fpemu_sp_msub
;
652 handler
= fpemu_sp_nmadd
;
655 handler
= fpemu_sp_nmsub
;
659 SPFROMREG(fr
, MIPSInst_FR(ir
));
660 SPFROMREG(fs
, MIPSInst_FS(ir
));
661 SPFROMREG(ft
, MIPSInst_FT(ir
));
662 fd
= (*handler
) (fr
, fs
, ft
);
663 SPTOREG(fd
, MIPSInst_FD(ir
));
666 if (ieee754_cxtest(IEEE754_INEXACT
))
667 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
668 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
669 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
670 if (ieee754_cxtest(IEEE754_OVERFLOW
))
671 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
672 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
673 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
675 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
676 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
677 /*printk ("SIGFPE: fpu csr = %08x\n",
691 ieee754dp(*handler
) (ieee754dp
, ieee754dp
, ieee754dp
);
692 ieee754dp fd
, fr
, fs
, ft
;
696 switch (MIPSInst_FUNC(ir
)) {
698 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
699 xcp
->regs
[MIPSInst_FT(ir
)]);
701 MIPS_FPU_EMU_INC_STATS(loads
);
702 if (get_user(val
, va
)) {
703 MIPS_FPU_EMU_INC_STATS(errors
);
706 DITOREG(val
, MIPSInst_FD(ir
));
710 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
711 xcp
->regs
[MIPSInst_FT(ir
)]);
713 MIPS_FPU_EMU_INC_STATS(stores
);
714 DIFROMREG(val
, MIPSInst_FS(ir
));
715 if (put_user(val
, va
)) {
716 MIPS_FPU_EMU_INC_STATS(errors
);
722 handler
= fpemu_dp_madd
;
725 handler
= fpemu_dp_msub
;
728 handler
= fpemu_dp_nmadd
;
731 handler
= fpemu_dp_nmsub
;
735 DPFROMREG(fr
, MIPSInst_FR(ir
));
736 DPFROMREG(fs
, MIPSInst_FS(ir
));
737 DPFROMREG(ft
, MIPSInst_FT(ir
));
738 fd
= (*handler
) (fr
, fs
, ft
);
739 DPTOREG(fd
, MIPSInst_FD(ir
));
749 if (MIPSInst_FUNC(ir
) != pfetch_op
) {
752 /* ignore prefx operation */
766 * Emulate a single COP1 arithmetic instruction.
768 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
771 int rfmt
; /* resulting format */
772 unsigned rcsr
= 0; /* resulting csr */
781 } rv
; /* resulting value */
783 MIPS_FPU_EMU_INC_STATS(cp1ops
);
784 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
787 ieee754sp(*b
) (ieee754sp
, ieee754sp
);
788 ieee754sp(*u
) (ieee754sp
);
791 switch (MIPSInst_FUNC(ir
)) {
794 handler
.b
= ieee754sp_add
;
797 handler
.b
= ieee754sp_sub
;
800 handler
.b
= ieee754sp_mul
;
803 handler
.b
= ieee754sp_div
;
807 #if __mips >= 2 || defined(__mips64)
809 handler
.u
= ieee754sp_sqrt
;
812 #if __mips >= 4 && __mips != 32
814 handler
.u
= fpemu_sp_rsqrt
;
817 handler
.u
= fpemu_sp_recip
;
822 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
823 if (((ctx
->fcr31
& cond
) != 0) !=
824 ((MIPSInst_FT(ir
) & 1) != 0))
826 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
829 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
831 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
834 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
836 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
840 handler
.u
= ieee754sp_abs
;
843 handler
.u
= ieee754sp_neg
;
847 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
850 /* binary op on handler */
855 SPFROMREG(fs
, MIPSInst_FS(ir
));
856 SPFROMREG(ft
, MIPSInst_FT(ir
));
858 rv
.s
= (*handler
.b
) (fs
, ft
);
865 SPFROMREG(fs
, MIPSInst_FS(ir
));
866 rv
.s
= (*handler
.u
) (fs
);
870 if (ieee754_cxtest(IEEE754_INEXACT
))
871 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
872 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
873 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
874 if (ieee754_cxtest(IEEE754_OVERFLOW
))
875 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
876 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
))
877 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
878 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
879 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
884 return SIGILL
; /* not defined */
888 SPFROMREG(fs
, MIPSInst_FS(ir
));
889 rv
.d
= ieee754dp_fsp(fs
);
896 SPFROMREG(fs
, MIPSInst_FS(ir
));
897 rv
.w
= ieee754sp_tint(fs
);
902 #if __mips >= 2 || defined(__mips64)
907 unsigned int oldrm
= ieee754_csr
.rm
;
910 SPFROMREG(fs
, MIPSInst_FS(ir
));
911 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
912 rv
.w
= ieee754sp_tint(fs
);
913 ieee754_csr
.rm
= oldrm
;
917 #endif /* __mips >= 2 */
919 #if defined(__mips64)
923 SPFROMREG(fs
, MIPSInst_FS(ir
));
924 rv
.l
= ieee754sp_tlong(fs
);
933 unsigned int oldrm
= ieee754_csr
.rm
;
936 SPFROMREG(fs
, MIPSInst_FS(ir
));
937 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
938 rv
.l
= ieee754sp_tlong(fs
);
939 ieee754_csr
.rm
= oldrm
;
943 #endif /* defined(__mips64) */
946 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
947 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
950 SPFROMREG(fs
, MIPSInst_FS(ir
));
951 SPFROMREG(ft
, MIPSInst_FT(ir
));
952 rv
.w
= ieee754sp_cmp(fs
, ft
,
953 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
955 if ((cmpop
& 0x8) && ieee754_cxtest
956 (IEEE754_INVALID_OPERATION
))
957 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
972 ieee754dp(*b
) (ieee754dp
, ieee754dp
);
973 ieee754dp(*u
) (ieee754dp
);
976 switch (MIPSInst_FUNC(ir
)) {
979 handler
.b
= ieee754dp_add
;
982 handler
.b
= ieee754dp_sub
;
985 handler
.b
= ieee754dp_mul
;
988 handler
.b
= ieee754dp_div
;
992 #if __mips >= 2 || defined(__mips64)
994 handler
.u
= ieee754dp_sqrt
;
997 #if __mips >= 4 && __mips != 32
999 handler
.u
= fpemu_dp_rsqrt
;
1002 handler
.u
= fpemu_dp_recip
;
1007 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1008 if (((ctx
->fcr31
& cond
) != 0) !=
1009 ((MIPSInst_FT(ir
) & 1) != 0))
1011 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1014 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1016 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1019 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1021 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1025 handler
.u
= ieee754dp_abs
;
1029 handler
.u
= ieee754dp_neg
;
1034 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1037 /* binary op on handler */
1041 DPFROMREG(fs
, MIPSInst_FS(ir
));
1042 DPFROMREG(ft
, MIPSInst_FT(ir
));
1044 rv
.d
= (*handler
.b
) (fs
, ft
);
1050 DPFROMREG(fs
, MIPSInst_FS(ir
));
1051 rv
.d
= (*handler
.u
) (fs
);
1055 /* unary conv ops */
1059 DPFROMREG(fs
, MIPSInst_FS(ir
));
1060 rv
.s
= ieee754sp_fdp(fs
);
1065 return SIGILL
; /* not defined */
1070 DPFROMREG(fs
, MIPSInst_FS(ir
));
1071 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1076 #if __mips >= 2 || defined(__mips64)
1081 unsigned int oldrm
= ieee754_csr
.rm
;
1084 DPFROMREG(fs
, MIPSInst_FS(ir
));
1085 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1086 rv
.w
= ieee754dp_tint(fs
);
1087 ieee754_csr
.rm
= oldrm
;
1093 #if defined(__mips64)
1097 DPFROMREG(fs
, MIPSInst_FS(ir
));
1098 rv
.l
= ieee754dp_tlong(fs
);
1107 unsigned int oldrm
= ieee754_csr
.rm
;
1110 DPFROMREG(fs
, MIPSInst_FS(ir
));
1111 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1112 rv
.l
= ieee754dp_tlong(fs
);
1113 ieee754_csr
.rm
= oldrm
;
1117 #endif /* __mips >= 3 */
1120 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1121 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1124 DPFROMREG(fs
, MIPSInst_FS(ir
));
1125 DPFROMREG(ft
, MIPSInst_FT(ir
));
1126 rv
.w
= ieee754dp_cmp(fs
, ft
,
1127 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1132 (IEEE754_INVALID_OPERATION
))
1133 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1149 switch (MIPSInst_FUNC(ir
)) {
1151 /* convert word to single precision real */
1152 SPFROMREG(fs
, MIPSInst_FS(ir
));
1153 rv
.s
= ieee754sp_fint(fs
.bits
);
1157 /* convert word to double precision real */
1158 SPFROMREG(fs
, MIPSInst_FS(ir
));
1159 rv
.d
= ieee754dp_fint(fs
.bits
);
1168 #if defined(__mips64)
1170 switch (MIPSInst_FUNC(ir
)) {
1172 /* convert long to single precision real */
1173 rv
.s
= ieee754sp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1177 /* convert long to double precision real */
1178 rv
.d
= ieee754dp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1193 * Update the fpu CSR register for this operation.
1194 * If an exception is required, generate a tidy SIGFPE exception,
1195 * without updating the result register.
1196 * Note: cause exception bits do not accumulate, they are rewritten
1197 * for each op; only the flag/sticky bits accumulate.
1199 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1200 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1201 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1206 * Now we can safely write the result back to the register file.
1211 cond
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
1213 cond
= FPU_CSR_COND
;
1218 ctx
->fcr31
&= ~cond
;
1222 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
1225 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
1228 SITOREG(rv
.w
, MIPSInst_FD(ir
));
1230 #if defined(__mips64)
1232 DITOREG(rv
.l
, MIPSInst_FD(ir
));
1242 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1245 unsigned long oldepc
, prevepc
;
1246 mips_instruction insn
;
1249 oldepc
= xcp
->cp0_epc
;
1251 prevepc
= xcp
->cp0_epc
;
1253 if (get_user(insn
, (mips_instruction __user
*) xcp
->cp0_epc
)) {
1254 MIPS_FPU_EMU_INC_STATS(errors
);
1258 xcp
->cp0_epc
+= 4; /* skip nops */
1261 * The 'ieee754_csr' is an alias of
1262 * ctx->fcr31. No need to copy ctx->fcr31 to
1263 * ieee754_csr. But ieee754_csr.rm is ieee
1264 * library modes. (not mips rounding mode)
1266 /* convert to ieee library modes */
1267 ieee754_csr
.rm
= ieee_rm
[ieee754_csr
.rm
];
1268 sig
= cop1Emulate(xcp
, ctx
);
1269 /* revert to mips rounding mode */
1270 ieee754_csr
.rm
= mips_rm
[ieee754_csr
.rm
];
1279 } while (xcp
->cp0_epc
> prevepc
);
1281 /* SIGILL indicates a non-fpu instruction */
1282 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
1283 /* but if epc has advanced, then ignore it */
1289 #ifdef CONFIG_DEBUG_FS
1291 static int fpuemu_stat_get(void *data
, u64
*val
)
1294 unsigned long sum
= 0;
1295 for_each_online_cpu(cpu
) {
1296 struct mips_fpu_emulator_stats
*ps
;
1298 ps
= &per_cpu(fpuemustats
, cpu
);
1299 pv
= (void *)ps
+ (unsigned long)data
;
1300 sum
+= local_read(pv
);
1305 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat
, fpuemu_stat_get
, NULL
, "%llu\n");
1307 extern struct dentry
*mips_debugfs_dir
;
1308 static int __init
debugfs_fpuemu(void)
1310 struct dentry
*d
, *dir
;
1312 if (!mips_debugfs_dir
)
1314 dir
= debugfs_create_dir("fpuemustats", mips_debugfs_dir
);
1318 #define FPU_STAT_CREATE(M) \
1320 d = debugfs_create_file(#M , S_IRUGO, dir, \
1321 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1322 &fops_fpuemu_stat); \
1327 FPU_STAT_CREATE(emulated
);
1328 FPU_STAT_CREATE(loads
);
1329 FPU_STAT_CREATE(stores
);
1330 FPU_STAT_CREATE(cp1ops
);
1331 FPU_STAT_CREATE(cp1xops
);
1332 FPU_STAT_CREATE(errors
);
1336 __initcall(debugfs_fpuemu
);