2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
49 #include <asm/uaccess.h>
50 #include <asm/branch.h>
54 /* Strap kernel emulator for full MIPS IV emulation */
61 /* Function which emulates a floating point instruction. */
63 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
66 #if __mips >= 4 && __mips != 32
67 static int fpux_emu(struct pt_regs
*,
68 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
71 /* Further private data for which no space exists in mips_fpu_struct */
73 #ifdef CONFIG_DEBUG_FS
74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats
, fpuemustats
);
77 /* Control registers */
79 #define FPCREG_RID 0 /* $0 = revision id */
80 #define FPCREG_CSR 31 /* $31 = csr */
82 /* Determine rounding mode from the RM bits of the FCSR */
83 #define modeindex(v) ((v) & FPU_CSR_RM)
85 /* microMIPS bitfields */
86 #define MM_POOL32A_MINOR_MASK 0x3f
87 #define MM_POOL32A_MINOR_SHIFT 0x6
88 #define MM_MIPS32_COND_FC 0x30
90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
91 static const unsigned char ieee_rm
[4] = {
92 [FPU_CSR_RN
] = IEEE754_RN
,
93 [FPU_CSR_RZ
] = IEEE754_RZ
,
94 [FPU_CSR_RU
] = IEEE754_RU
,
95 [FPU_CSR_RD
] = IEEE754_RD
,
97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
98 static const unsigned char mips_rm
[4] = {
99 [IEEE754_RN
] = FPU_CSR_RN
,
100 [IEEE754_RZ
] = FPU_CSR_RZ
,
101 [IEEE754_RD
] = FPU_CSR_RD
,
102 [IEEE754_RU
] = FPU_CSR_RU
,
106 /* convert condition code register number to csr bit */
107 static const unsigned int fpucondbit
[8] = {
119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
124 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
125 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
126 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
133 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
135 union mips_instruction insn
= *insn_ptr
;
136 union mips_instruction mips32_insn
= insn
;
139 switch (insn
.mm_i_format
.opcode
) {
141 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
142 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
143 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
146 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
147 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
148 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
151 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
152 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
153 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
156 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
157 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
158 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
163 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
164 mips32_insn
.fb_format
.opcode
= cop1_op
;
165 mips32_insn
.fb_format
.bc
= bc_op
;
166 mips32_insn
.fb_format
.flag
=
167 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
172 switch (insn
.mm_fp0_format
.func
) {
181 op
= insn
.mm_fp0_format
.func
;
182 if (op
== mm_32f_01_op
)
184 else if (op
== mm_32f_11_op
)
186 else if (op
== mm_32f_02_op
)
188 else if (op
== mm_32f_12_op
)
190 else if (op
== mm_32f_41_op
)
192 else if (op
== mm_32f_51_op
)
194 else if (op
== mm_32f_42_op
)
198 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
199 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
200 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
201 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
202 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
203 mips32_insn
.fp6_format
.func
= func
;
206 func
= -1; /* Invalid */
207 op
= insn
.mm_fp5_format
.op
& 0x7;
208 if (op
== mm_ldxc1_op
)
210 else if (op
== mm_sdxc1_op
)
212 else if (op
== mm_lwxc1_op
)
214 else if (op
== mm_swxc1_op
)
218 mips32_insn
.r_format
.opcode
= cop1x_op
;
219 mips32_insn
.r_format
.rs
=
220 insn
.mm_fp5_format
.base
;
221 mips32_insn
.r_format
.rt
=
222 insn
.mm_fp5_format
.index
;
223 mips32_insn
.r_format
.rd
= 0;
224 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
225 mips32_insn
.r_format
.func
= func
;
230 op
= -1; /* Invalid */
231 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
233 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
236 mips32_insn
.fp0_format
.opcode
= cop1_op
;
237 mips32_insn
.fp0_format
.fmt
=
238 sdps_format
[insn
.mm_fp2_format
.fmt
];
239 mips32_insn
.fp0_format
.ft
=
240 (insn
.mm_fp2_format
.cc
<<2) + op
;
241 mips32_insn
.fp0_format
.fs
=
242 insn
.mm_fp2_format
.fs
;
243 mips32_insn
.fp0_format
.fd
=
244 insn
.mm_fp2_format
.fd
;
245 mips32_insn
.fp0_format
.func
= fmovc_op
;
250 func
= -1; /* Invalid */
251 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
253 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
255 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
257 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
260 mips32_insn
.fp0_format
.opcode
= cop1_op
;
261 mips32_insn
.fp0_format
.fmt
=
262 sdps_format
[insn
.mm_fp0_format
.fmt
];
263 mips32_insn
.fp0_format
.ft
=
264 insn
.mm_fp0_format
.ft
;
265 mips32_insn
.fp0_format
.fs
=
266 insn
.mm_fp0_format
.fs
;
267 mips32_insn
.fp0_format
.fd
=
268 insn
.mm_fp0_format
.fd
;
269 mips32_insn
.fp0_format
.func
= func
;
274 func
= -1; /* Invalid */
275 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
277 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
280 mips32_insn
.fp0_format
.opcode
= cop1_op
;
281 mips32_insn
.fp0_format
.fmt
=
282 sdps_format
[insn
.mm_fp0_format
.fmt
];
283 mips32_insn
.fp0_format
.ft
=
284 insn
.mm_fp0_format
.ft
;
285 mips32_insn
.fp0_format
.fs
=
286 insn
.mm_fp0_format
.fs
;
287 mips32_insn
.fp0_format
.fd
=
288 insn
.mm_fp0_format
.fd
;
289 mips32_insn
.fp0_format
.func
= func
;
293 case mm_32f_73_op
: /* POOL32FXF */
294 switch (insn
.mm_fp1_format
.op
) {
299 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
304 mips32_insn
.r_format
.opcode
= spec_op
;
305 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
306 mips32_insn
.r_format
.rt
=
307 (insn
.mm_fp4_format
.cc
<< 2) + op
;
308 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
309 mips32_insn
.r_format
.re
= 0;
310 mips32_insn
.r_format
.func
= movc_op
;
316 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
319 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
322 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
324 mips32_insn
.fp0_format
.opcode
= cop1_op
;
325 mips32_insn
.fp0_format
.fmt
= fmt
;
326 mips32_insn
.fp0_format
.ft
= 0;
327 mips32_insn
.fp0_format
.fs
=
328 insn
.mm_fp3_format
.fs
;
329 mips32_insn
.fp0_format
.fd
=
330 insn
.mm_fp3_format
.rt
;
331 mips32_insn
.fp0_format
.func
= func
;
339 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
342 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
347 mips32_insn
.fp0_format
.opcode
= cop1_op
;
348 mips32_insn
.fp0_format
.fmt
=
349 sdps_format
[insn
.mm_fp3_format
.fmt
];
350 mips32_insn
.fp0_format
.ft
= 0;
351 mips32_insn
.fp0_format
.fs
=
352 insn
.mm_fp3_format
.fs
;
353 mips32_insn
.fp0_format
.fd
=
354 insn
.mm_fp3_format
.rt
;
355 mips32_insn
.fp0_format
.func
= func
;
367 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
369 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
371 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
373 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
375 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
377 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
379 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
381 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
383 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
387 mips32_insn
.fp0_format
.opcode
= cop1_op
;
388 mips32_insn
.fp0_format
.fmt
=
389 sd_format
[insn
.mm_fp1_format
.fmt
];
390 mips32_insn
.fp0_format
.ft
= 0;
391 mips32_insn
.fp0_format
.fs
=
392 insn
.mm_fp1_format
.fs
;
393 mips32_insn
.fp0_format
.fd
=
394 insn
.mm_fp1_format
.rt
;
395 mips32_insn
.fp0_format
.func
= func
;
400 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
402 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
406 mips32_insn
.fp0_format
.opcode
= cop1_op
;
407 mips32_insn
.fp0_format
.fmt
=
408 sdps_format
[insn
.mm_fp1_format
.fmt
];
409 mips32_insn
.fp0_format
.ft
= 0;
410 mips32_insn
.fp0_format
.fs
=
411 insn
.mm_fp1_format
.fs
;
412 mips32_insn
.fp0_format
.fd
=
413 insn
.mm_fp1_format
.rt
;
414 mips32_insn
.fp0_format
.func
= func
;
420 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
422 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
424 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
428 mips32_insn
.fp1_format
.opcode
= cop1_op
;
429 mips32_insn
.fp1_format
.op
= op
;
430 mips32_insn
.fp1_format
.rt
=
431 insn
.mm_fp1_format
.rt
;
432 mips32_insn
.fp1_format
.fs
=
433 insn
.mm_fp1_format
.fs
;
434 mips32_insn
.fp1_format
.fd
= 0;
435 mips32_insn
.fp1_format
.func
= 0;
442 case mm_32f_74_op
: /* c.cond.fmt */
443 mips32_insn
.fp0_format
.opcode
= cop1_op
;
444 mips32_insn
.fp0_format
.fmt
=
445 sdps_format
[insn
.mm_fp4_format
.fmt
];
446 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
447 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
448 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
449 mips32_insn
.fp0_format
.func
=
450 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
462 *insn_ptr
= mips32_insn
;
466 int mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
467 unsigned long *contpc
)
469 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
477 switch (insn
.mm_i_format
.opcode
) {
479 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
481 switch (insn
.mm_i_format
.simmediate
>>
482 MM_POOL32A_MINOR_SHIFT
) {
487 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
488 regs
->regs
[insn
.mm_i_format
.rt
] =
491 dec_insn
.next_pc_inc
;
492 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
499 switch (insn
.mm_i_format
.rt
) {
502 regs
->regs
[31] = regs
->cp0_epc
+
504 dec_insn
.next_pc_inc
;
507 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
508 *contpc
= regs
->cp0_epc
+
510 (insn
.mm_i_format
.simmediate
<< 1);
512 *contpc
= regs
->cp0_epc
+
514 dec_insn
.next_pc_inc
;
519 regs
->regs
[31] = regs
->cp0_epc
+
521 dec_insn
.next_pc_inc
;
524 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
525 *contpc
= regs
->cp0_epc
+
527 (insn
.mm_i_format
.simmediate
<< 1);
529 *contpc
= regs
->cp0_epc
+
531 dec_insn
.next_pc_inc
;
535 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
536 *contpc
= regs
->cp0_epc
+
538 (insn
.mm_i_format
.simmediate
<< 1);
540 *contpc
= regs
->cp0_epc
+
542 dec_insn
.next_pc_inc
;
546 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
547 *contpc
= regs
->cp0_epc
+
549 (insn
.mm_i_format
.simmediate
<< 1);
551 *contpc
= regs
->cp0_epc
+
553 dec_insn
.next_pc_inc
;
564 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
566 fcr31
= current
->thread
.fpu
.fcr31
;
572 bit
= (insn
.mm_i_format
.rs
>> 2);
575 if (fcr31
& (1 << bit
))
576 *contpc
= regs
->cp0_epc
+
578 (insn
.mm_i_format
.simmediate
<< 1);
580 *contpc
= regs
->cp0_epc
+
581 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
587 switch (insn
.mm_i_format
.rt
) {
590 regs
->regs
[31] = regs
->cp0_epc
+
591 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
594 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
600 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
601 *contpc
= regs
->cp0_epc
+
603 (insn
.mm_b1_format
.simmediate
<< 1);
605 *contpc
= regs
->cp0_epc
+
606 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
610 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
611 *contpc
= regs
->cp0_epc
+
613 (insn
.mm_b1_format
.simmediate
<< 1);
615 *contpc
= regs
->cp0_epc
+
616 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
620 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
621 (insn
.mm_b0_format
.simmediate
<< 1);
625 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
626 regs
->regs
[insn
.mm_i_format
.rt
])
627 *contpc
= regs
->cp0_epc
+
629 (insn
.mm_i_format
.simmediate
<< 1);
631 *contpc
= regs
->cp0_epc
+
633 dec_insn
.next_pc_inc
;
637 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
638 regs
->regs
[insn
.mm_i_format
.rt
])
639 *contpc
= regs
->cp0_epc
+
641 (insn
.mm_i_format
.simmediate
<< 1);
643 *contpc
= regs
->cp0_epc
+
644 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
648 regs
->regs
[31] = regs
->cp0_epc
+
649 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
650 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
653 *contpc
|= (insn
.j_format
.target
<< 2);
658 regs
->regs
[31] = regs
->cp0_epc
+
659 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
662 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
665 *contpc
|= (insn
.j_format
.target
<< 1);
666 set_isa16_mode(*contpc
);
674 * Redundant with logic already in kernel/branch.c,
675 * embedded in compute_return_epc. At some point,
676 * a single subroutine should be used across both
679 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
680 unsigned long *contpc
)
682 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
684 unsigned int bit
= 0;
686 switch (insn
.i_format
.opcode
) {
688 switch (insn
.r_format
.func
) {
690 regs
->regs
[insn
.r_format
.rd
] =
691 regs
->cp0_epc
+ dec_insn
.pc_inc
+
692 dec_insn
.next_pc_inc
;
695 *contpc
= regs
->regs
[insn
.r_format
.rs
];
701 switch (insn
.i_format
.rt
) {
704 regs
->regs
[31] = regs
->cp0_epc
+
706 dec_insn
.next_pc_inc
;
710 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
711 *contpc
= regs
->cp0_epc
+
713 (insn
.i_format
.simmediate
<< 2);
715 *contpc
= regs
->cp0_epc
+
717 dec_insn
.next_pc_inc
;
722 regs
->regs
[31] = regs
->cp0_epc
+
724 dec_insn
.next_pc_inc
;
728 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
729 *contpc
= regs
->cp0_epc
+
731 (insn
.i_format
.simmediate
<< 2);
733 *contpc
= regs
->cp0_epc
+
735 dec_insn
.next_pc_inc
;
743 regs
->regs
[31] = regs
->cp0_epc
+
745 dec_insn
.next_pc_inc
;
748 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
751 *contpc
|= (insn
.j_format
.target
<< 2);
752 /* Set microMIPS mode bit: XOR for jalx. */
758 if (regs
->regs
[insn
.i_format
.rs
] ==
759 regs
->regs
[insn
.i_format
.rt
])
760 *contpc
= regs
->cp0_epc
+
762 (insn
.i_format
.simmediate
<< 2);
764 *contpc
= regs
->cp0_epc
+
766 dec_insn
.next_pc_inc
;
771 if (regs
->regs
[insn
.i_format
.rs
] !=
772 regs
->regs
[insn
.i_format
.rt
])
773 *contpc
= regs
->cp0_epc
+
775 (insn
.i_format
.simmediate
<< 2);
777 *contpc
= regs
->cp0_epc
+
779 dec_insn
.next_pc_inc
;
784 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
785 *contpc
= regs
->cp0_epc
+
787 (insn
.i_format
.simmediate
<< 2);
789 *contpc
= regs
->cp0_epc
+
791 dec_insn
.next_pc_inc
;
796 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
797 *contpc
= regs
->cp0_epc
+
799 (insn
.i_format
.simmediate
<< 2);
801 *contpc
= regs
->cp0_epc
+
803 dec_insn
.next_pc_inc
;
806 #ifdef CONFIG_CPU_CAVIUM_OCTEON
807 case lwc2_op
: /* This is bbit0 on Octeon */
808 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
)) == 0)
809 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
811 *contpc
= regs
->cp0_epc
+ 8;
813 case ldc2_op
: /* This is bbit032 on Octeon */
814 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32))) == 0)
815 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
817 *contpc
= regs
->cp0_epc
+ 8;
819 case swc2_op
: /* This is bbit1 on Octeon */
820 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
821 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
823 *contpc
= regs
->cp0_epc
+ 8;
825 case sdc2_op
: /* This is bbit132 on Octeon */
826 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32)))
827 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
829 *contpc
= regs
->cp0_epc
+ 8;
836 if (insn
.i_format
.rs
== bc_op
) {
839 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
841 fcr31
= current
->thread
.fpu
.fcr31
;
844 bit
= (insn
.i_format
.rt
>> 2);
847 switch (insn
.i_format
.rt
& 3) {
850 if (~fcr31
& (1 << bit
))
851 *contpc
= regs
->cp0_epc
+
853 (insn
.i_format
.simmediate
<< 2);
855 *contpc
= regs
->cp0_epc
+
857 dec_insn
.next_pc_inc
;
862 if (fcr31
& (1 << bit
))
863 *contpc
= regs
->cp0_epc
+
865 (insn
.i_format
.simmediate
<< 2);
867 *contpc
= regs
->cp0_epc
+
869 dec_insn
.next_pc_inc
;
880 * In the Linux kernel, we support selection of FPR format on the
881 * basis of the Status.FR bit. If an FPU is not present, the FR bit
882 * is hardwired to zero, which would imply a 32-bit FPU even for
883 * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
884 * FPU emu is slow and bulky and optimizing this function offers fairly
885 * sizeable benefits so we try to be clever and make this function return
886 * a constant whenever possible, that is on 64-bit kernels without O32
887 * compatibility enabled and on 32-bit kernels.
889 static inline int cop1_64bit(struct pt_regs
*xcp
)
891 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
893 #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
894 return !test_thread_flag(TIF_32BIT_REGS
);
900 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
901 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
903 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
904 cop1_64bit(xcp) || !(x & 1) ? \
905 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
906 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
908 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
909 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
911 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
912 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
913 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
914 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
917 * Emulate the single floating point instruction pointed at by EPC.
918 * Two instructions if the instruction is in a branch delay slot.
921 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
922 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
925 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
929 /* XXX NEC Vr54xx bug workaround */
930 if (xcp
->cp0_cause
& CAUSEF_BD
) {
931 if (dec_insn
.micro_mips_mode
) {
932 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
933 xcp
->cp0_cause
&= ~CAUSEF_BD
;
935 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
936 xcp
->cp0_cause
&= ~CAUSEF_BD
;
940 if (xcp
->cp0_cause
& CAUSEF_BD
) {
942 * The instruction to be emulated is in a branch delay slot
943 * which means that we have to emulate the branch instruction
944 * BEFORE we do the cop1 instruction.
946 * This branch could be a COP1 branch, but in that case we
947 * would have had a trap for that instruction, and would not
948 * come through this route.
950 * Linux MIPS branch emulator operates on context, updating the
953 ir
= dec_insn
.next_insn
; /* process delay slot instr */
954 pc_inc
= dec_insn
.next_pc_inc
;
956 ir
= dec_insn
.insn
; /* process current instr */
957 pc_inc
= dec_insn
.pc_inc
;
961 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
962 * instructions, we want to convert microMIPS FPU instructions
963 * into MIPS32 instructions so that we could reuse all of the
964 * FPU emulation code.
966 * NOTE: We cannot do this for branch instructions since they
967 * are not a subset. Example: Cannot emulate a 16-bit
968 * aligned target address with a MIPS32 instruction.
970 if (dec_insn
.micro_mips_mode
) {
972 * If next instruction is a 16-bit instruction, then it
973 * it cannot be a FPU instruction. This could happen
974 * since we can be called for non-FPU instructions.
977 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
983 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
984 MIPS_FPU_EMU_INC_STATS(emulated
);
985 switch (MIPSInst_OPCODE(ir
)) {
987 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
991 MIPS_FPU_EMU_INC_STATS(loads
);
993 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
994 MIPS_FPU_EMU_INC_STATS(errors
);
998 if (__get_user(val
, va
)) {
999 MIPS_FPU_EMU_INC_STATS(errors
);
1003 DITOREG(val
, MIPSInst_RT(ir
));
1008 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1012 MIPS_FPU_EMU_INC_STATS(stores
);
1013 DIFROMREG(val
, MIPSInst_RT(ir
));
1014 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1015 MIPS_FPU_EMU_INC_STATS(errors
);
1019 if (__put_user(val
, va
)) {
1020 MIPS_FPU_EMU_INC_STATS(errors
);
1028 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1032 MIPS_FPU_EMU_INC_STATS(loads
);
1033 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1034 MIPS_FPU_EMU_INC_STATS(errors
);
1038 if (__get_user(val
, va
)) {
1039 MIPS_FPU_EMU_INC_STATS(errors
);
1043 SITOREG(val
, MIPSInst_RT(ir
));
1048 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1052 MIPS_FPU_EMU_INC_STATS(stores
);
1053 SIFROMREG(val
, MIPSInst_RT(ir
));
1054 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1055 MIPS_FPU_EMU_INC_STATS(errors
);
1059 if (__put_user(val
, va
)) {
1060 MIPS_FPU_EMU_INC_STATS(errors
);
1068 switch (MIPSInst_RS(ir
)) {
1070 #if defined(__mips64)
1072 /* copregister fs -> gpr[rt] */
1073 if (MIPSInst_RT(ir
) != 0) {
1074 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1080 /* copregister fs <- rt */
1081 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1086 /* copregister rd -> gpr[rt] */
1087 if (MIPSInst_RT(ir
) != 0) {
1088 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1094 /* copregister rd <- rt */
1095 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1099 /* cop control register rd -> gpr[rt] */
1102 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1104 value
= (value
& ~FPU_CSR_RM
) |
1105 mips_rm
[modeindex(value
)];
1107 printk("%p gpr[%d]<-csr=%08x\n",
1108 (void *) (xcp
->cp0_epc
),
1109 MIPSInst_RT(ir
), value
);
1112 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
1116 if (MIPSInst_RT(ir
))
1117 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
1122 /* copregister rd <- rt */
1125 if (MIPSInst_RT(ir
) == 0)
1128 value
= xcp
->regs
[MIPSInst_RT(ir
)];
1130 /* we only have one writable control reg
1132 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1134 printk("%p gpr[%d]->csr=%08x\n",
1135 (void *) (xcp
->cp0_epc
),
1136 MIPSInst_RT(ir
), value
);
1140 * Don't write reserved bits,
1141 * and convert to ieee library modes
1143 ctx
->fcr31
= (value
&
1144 ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
1145 ieee_rm
[modeindex(value
)];
1147 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1156 if (xcp
->cp0_cause
& CAUSEF_BD
)
1160 cond
= ctx
->fcr31
& fpucondbit
[MIPSInst_RT(ir
) >> 2];
1162 cond
= ctx
->fcr31
& FPU_CSR_COND
;
1164 switch (MIPSInst_RT(ir
) & 3) {
1175 /* thats an illegal instruction */
1179 xcp
->cp0_cause
|= CAUSEF_BD
;
1181 /* branch taken: emulate dslot
1184 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1186 contpc
= MIPSInst_SIMM(ir
);
1187 ir
= dec_insn
.next_insn
;
1188 if (dec_insn
.micro_mips_mode
) {
1189 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1191 /* If 16-bit instruction, not FPU. */
1192 if ((dec_insn
.next_pc_inc
== 2) ||
1193 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1196 * Since this instruction will
1197 * be put on the stack with
1198 * 32-bit words, get around
1199 * this problem by putting a
1200 * NOP16 as the second one.
1202 if (dec_insn
.next_pc_inc
== 2)
1203 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1206 * Single step the non-CP1
1207 * instruction in the dslot.
1209 return mips_dsemul(xcp
, ir
, contpc
);
1212 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1214 switch (MIPSInst_OPCODE(ir
)) {
1217 #if (__mips >= 2 || defined(__mips64))
1222 #if __mips >= 4 && __mips != 32
1225 /* its one of ours */
1229 if (MIPSInst_FUNC(ir
) == movc_op
)
1236 * Single step the non-cp1
1237 * instruction in the dslot
1239 return mips_dsemul(xcp
, ir
, contpc
);
1242 /* branch not taken */
1245 * branch likely nullifies
1246 * dslot if not taken
1248 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1249 contpc
+= dec_insn
.pc_inc
;
1251 * else continue & execute
1252 * dslot as normal insn
1260 if (!(MIPSInst_RS(ir
) & 0x10))
1265 /* a real fpu computation instruction */
1266 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1272 #if __mips >= 4 && __mips != 32
1274 int sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1283 if (MIPSInst_FUNC(ir
) != movc_op
)
1285 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1286 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1287 xcp
->regs
[MIPSInst_RD(ir
)] =
1288 xcp
->regs
[MIPSInst_RS(ir
)];
1297 xcp
->cp0_epc
= contpc
;
1298 xcp
->cp0_cause
&= ~CAUSEF_BD
;
1304 * Conversion table from MIPS compare ops 48-63
1305 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1307 static const unsigned char cmptab
[8] = {
1308 0, /* cmp_0 (sig) cmp_sf */
1309 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1310 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1311 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1312 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1313 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1314 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1315 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1319 #if __mips >= 4 && __mips != 32
1322 * Additional MIPS4 instructions
1325 #define DEF3OP(name, p, f1, f2, f3) \
1326 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1329 struct _ieee754_csr ieee754_csr_save; \
1331 ieee754_csr_save = ieee754_csr; \
1333 ieee754_csr_save.cx |= ieee754_csr.cx; \
1334 ieee754_csr_save.sx |= ieee754_csr.sx; \
1336 ieee754_csr.cx |= ieee754_csr_save.cx; \
1337 ieee754_csr.sx |= ieee754_csr_save.sx; \
1341 static ieee754dp
fpemu_dp_recip(ieee754dp d
)
1343 return ieee754dp_div(ieee754dp_one(0), d
);
1346 static ieee754dp
fpemu_dp_rsqrt(ieee754dp d
)
1348 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1351 static ieee754sp
fpemu_sp_recip(ieee754sp s
)
1353 return ieee754sp_div(ieee754sp_one(0), s
);
1356 static ieee754sp
fpemu_sp_rsqrt(ieee754sp s
)
1358 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1361 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1362 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1363 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1364 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1365 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1366 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1367 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1368 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1370 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1371 mips_instruction ir
, void *__user
*fault_addr
)
1373 unsigned rcsr
= 0; /* resulting csr */
1375 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1377 switch (MIPSInst_FMA_FFMT(ir
)) {
1378 case s_fmt
:{ /* 0 */
1380 ieee754sp(*handler
) (ieee754sp
, ieee754sp
, ieee754sp
);
1381 ieee754sp fd
, fr
, fs
, ft
;
1385 switch (MIPSInst_FUNC(ir
)) {
1387 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1388 xcp
->regs
[MIPSInst_FT(ir
)]);
1390 MIPS_FPU_EMU_INC_STATS(loads
);
1391 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1392 MIPS_FPU_EMU_INC_STATS(errors
);
1396 if (__get_user(val
, va
)) {
1397 MIPS_FPU_EMU_INC_STATS(errors
);
1401 SITOREG(val
, MIPSInst_FD(ir
));
1405 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1406 xcp
->regs
[MIPSInst_FT(ir
)]);
1408 MIPS_FPU_EMU_INC_STATS(stores
);
1410 SIFROMREG(val
, MIPSInst_FS(ir
));
1411 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1412 MIPS_FPU_EMU_INC_STATS(errors
);
1416 if (put_user(val
, va
)) {
1417 MIPS_FPU_EMU_INC_STATS(errors
);
1424 handler
= fpemu_sp_madd
;
1427 handler
= fpemu_sp_msub
;
1430 handler
= fpemu_sp_nmadd
;
1433 handler
= fpemu_sp_nmsub
;
1437 SPFROMREG(fr
, MIPSInst_FR(ir
));
1438 SPFROMREG(fs
, MIPSInst_FS(ir
));
1439 SPFROMREG(ft
, MIPSInst_FT(ir
));
1440 fd
= (*handler
) (fr
, fs
, ft
);
1441 SPTOREG(fd
, MIPSInst_FD(ir
));
1444 if (ieee754_cxtest(IEEE754_INEXACT
))
1445 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1446 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1447 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1448 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1449 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1450 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1451 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1453 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1454 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1455 /*printk ("SIGFPE: fpu csr = %08x\n",
1468 case d_fmt
:{ /* 1 */
1469 ieee754dp(*handler
) (ieee754dp
, ieee754dp
, ieee754dp
);
1470 ieee754dp fd
, fr
, fs
, ft
;
1474 switch (MIPSInst_FUNC(ir
)) {
1476 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1477 xcp
->regs
[MIPSInst_FT(ir
)]);
1479 MIPS_FPU_EMU_INC_STATS(loads
);
1480 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1481 MIPS_FPU_EMU_INC_STATS(errors
);
1485 if (__get_user(val
, va
)) {
1486 MIPS_FPU_EMU_INC_STATS(errors
);
1490 DITOREG(val
, MIPSInst_FD(ir
));
1494 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1495 xcp
->regs
[MIPSInst_FT(ir
)]);
1497 MIPS_FPU_EMU_INC_STATS(stores
);
1498 DIFROMREG(val
, MIPSInst_FS(ir
));
1499 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1500 MIPS_FPU_EMU_INC_STATS(errors
);
1504 if (__put_user(val
, va
)) {
1505 MIPS_FPU_EMU_INC_STATS(errors
);
1512 handler
= fpemu_dp_madd
;
1515 handler
= fpemu_dp_msub
;
1518 handler
= fpemu_dp_nmadd
;
1521 handler
= fpemu_dp_nmsub
;
1525 DPFROMREG(fr
, MIPSInst_FR(ir
));
1526 DPFROMREG(fs
, MIPSInst_FS(ir
));
1527 DPFROMREG(ft
, MIPSInst_FT(ir
));
1528 fd
= (*handler
) (fr
, fs
, ft
);
1529 DPTOREG(fd
, MIPSInst_FD(ir
));
1539 if (MIPSInst_FUNC(ir
) != pfetch_op
) {
1542 /* ignore prefx operation */
1556 * Emulate a single COP1 arithmetic instruction.
1558 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1559 mips_instruction ir
)
1561 int rfmt
; /* resulting format */
1562 unsigned rcsr
= 0; /* resulting csr */
1571 } rv
; /* resulting value */
1573 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1574 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1575 case s_fmt
:{ /* 0 */
1577 ieee754sp(*b
) (ieee754sp
, ieee754sp
);
1578 ieee754sp(*u
) (ieee754sp
);
1581 switch (MIPSInst_FUNC(ir
)) {
1584 handler
.b
= ieee754sp_add
;
1587 handler
.b
= ieee754sp_sub
;
1590 handler
.b
= ieee754sp_mul
;
1593 handler
.b
= ieee754sp_div
;
1597 #if __mips >= 2 || defined(__mips64)
1599 handler
.u
= ieee754sp_sqrt
;
1602 #if __mips >= 4 && __mips != 32
1604 handler
.u
= fpemu_sp_rsqrt
;
1607 handler
.u
= fpemu_sp_recip
;
1612 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1613 if (((ctx
->fcr31
& cond
) != 0) !=
1614 ((MIPSInst_FT(ir
) & 1) != 0))
1616 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1619 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1621 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1624 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1626 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1630 handler
.u
= ieee754sp_abs
;
1633 handler
.u
= ieee754sp_neg
;
1637 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1640 /* binary op on handler */
1645 SPFROMREG(fs
, MIPSInst_FS(ir
));
1646 SPFROMREG(ft
, MIPSInst_FT(ir
));
1648 rv
.s
= (*handler
.b
) (fs
, ft
);
1655 SPFROMREG(fs
, MIPSInst_FS(ir
));
1656 rv
.s
= (*handler
.u
) (fs
);
1660 if (ieee754_cxtest(IEEE754_INEXACT
))
1661 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1662 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1663 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1664 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1665 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1666 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
))
1667 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1668 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1669 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1672 /* unary conv ops */
1674 return SIGILL
; /* not defined */
1678 SPFROMREG(fs
, MIPSInst_FS(ir
));
1679 rv
.d
= ieee754dp_fsp(fs
);
1686 SPFROMREG(fs
, MIPSInst_FS(ir
));
1687 rv
.w
= ieee754sp_tint(fs
);
1692 #if __mips >= 2 || defined(__mips64)
1697 unsigned int oldrm
= ieee754_csr
.rm
;
1700 SPFROMREG(fs
, MIPSInst_FS(ir
));
1701 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1702 rv
.w
= ieee754sp_tint(fs
);
1703 ieee754_csr
.rm
= oldrm
;
1707 #endif /* __mips >= 2 */
1709 #if defined(__mips64)
1713 SPFROMREG(fs
, MIPSInst_FS(ir
));
1714 rv
.l
= ieee754sp_tlong(fs
);
1723 unsigned int oldrm
= ieee754_csr
.rm
;
1726 SPFROMREG(fs
, MIPSInst_FS(ir
));
1727 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1728 rv
.l
= ieee754sp_tlong(fs
);
1729 ieee754_csr
.rm
= oldrm
;
1733 #endif /* defined(__mips64) */
1736 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1737 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1740 SPFROMREG(fs
, MIPSInst_FS(ir
));
1741 SPFROMREG(ft
, MIPSInst_FT(ir
));
1742 rv
.w
= ieee754sp_cmp(fs
, ft
,
1743 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1745 if ((cmpop
& 0x8) && ieee754_cxtest
1746 (IEEE754_INVALID_OPERATION
))
1747 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1762 ieee754dp(*b
) (ieee754dp
, ieee754dp
);
1763 ieee754dp(*u
) (ieee754dp
);
1766 switch (MIPSInst_FUNC(ir
)) {
1769 handler
.b
= ieee754dp_add
;
1772 handler
.b
= ieee754dp_sub
;
1775 handler
.b
= ieee754dp_mul
;
1778 handler
.b
= ieee754dp_div
;
1782 #if __mips >= 2 || defined(__mips64)
1784 handler
.u
= ieee754dp_sqrt
;
1787 #if __mips >= 4 && __mips != 32
1789 handler
.u
= fpemu_dp_rsqrt
;
1792 handler
.u
= fpemu_dp_recip
;
1797 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1798 if (((ctx
->fcr31
& cond
) != 0) !=
1799 ((MIPSInst_FT(ir
) & 1) != 0))
1801 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1804 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1806 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1809 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1811 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1815 handler
.u
= ieee754dp_abs
;
1819 handler
.u
= ieee754dp_neg
;
1824 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1827 /* binary op on handler */
1831 DPFROMREG(fs
, MIPSInst_FS(ir
));
1832 DPFROMREG(ft
, MIPSInst_FT(ir
));
1834 rv
.d
= (*handler
.b
) (fs
, ft
);
1840 DPFROMREG(fs
, MIPSInst_FS(ir
));
1841 rv
.d
= (*handler
.u
) (fs
);
1845 /* unary conv ops */
1849 DPFROMREG(fs
, MIPSInst_FS(ir
));
1850 rv
.s
= ieee754sp_fdp(fs
);
1855 return SIGILL
; /* not defined */
1860 DPFROMREG(fs
, MIPSInst_FS(ir
));
1861 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1866 #if __mips >= 2 || defined(__mips64)
1871 unsigned int oldrm
= ieee754_csr
.rm
;
1874 DPFROMREG(fs
, MIPSInst_FS(ir
));
1875 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1876 rv
.w
= ieee754dp_tint(fs
);
1877 ieee754_csr
.rm
= oldrm
;
1883 #if defined(__mips64)
1887 DPFROMREG(fs
, MIPSInst_FS(ir
));
1888 rv
.l
= ieee754dp_tlong(fs
);
1897 unsigned int oldrm
= ieee754_csr
.rm
;
1900 DPFROMREG(fs
, MIPSInst_FS(ir
));
1901 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1902 rv
.l
= ieee754dp_tlong(fs
);
1903 ieee754_csr
.rm
= oldrm
;
1907 #endif /* __mips >= 3 */
1910 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1911 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1914 DPFROMREG(fs
, MIPSInst_FS(ir
));
1915 DPFROMREG(ft
, MIPSInst_FT(ir
));
1916 rv
.w
= ieee754dp_cmp(fs
, ft
,
1917 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1922 (IEEE754_INVALID_OPERATION
))
1923 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1939 switch (MIPSInst_FUNC(ir
)) {
1941 /* convert word to single precision real */
1942 SPFROMREG(fs
, MIPSInst_FS(ir
));
1943 rv
.s
= ieee754sp_fint(fs
.bits
);
1947 /* convert word to double precision real */
1948 SPFROMREG(fs
, MIPSInst_FS(ir
));
1949 rv
.d
= ieee754dp_fint(fs
.bits
);
1958 #if defined(__mips64)
1960 switch (MIPSInst_FUNC(ir
)) {
1962 /* convert long to single precision real */
1963 rv
.s
= ieee754sp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1967 /* convert long to double precision real */
1968 rv
.d
= ieee754dp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1983 * Update the fpu CSR register for this operation.
1984 * If an exception is required, generate a tidy SIGFPE exception,
1985 * without updating the result register.
1986 * Note: cause exception bits do not accumulate, they are rewritten
1987 * for each op; only the flag/sticky bits accumulate.
1989 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1990 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1991 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1996 * Now we can safely write the result back to the register file.
2001 cond
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
2003 cond
= FPU_CSR_COND
;
2008 ctx
->fcr31
&= ~cond
;
2012 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
2015 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
2018 SITOREG(rv
.w
, MIPSInst_FD(ir
));
2020 #if defined(__mips64)
2022 DITOREG(rv
.l
, MIPSInst_FD(ir
));
2032 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2033 int has_fpu
, void *__user
*fault_addr
)
2035 unsigned long oldepc
, prevepc
;
2036 struct mm_decoded_insn dec_insn
;
2041 oldepc
= xcp
->cp0_epc
;
2043 prevepc
= xcp
->cp0_epc
;
2045 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2047 * Get next 2 microMIPS instructions and convert them
2048 * into 32-bit instructions.
2050 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2051 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2052 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2053 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2054 MIPS_FPU_EMU_INC_STATS(errors
);
2059 /* Get first instruction. */
2060 if (mm_insn_16bit(*instr_ptr
)) {
2061 /* Duplicate the half-word. */
2062 dec_insn
.insn
= (*instr_ptr
<< 16) |
2064 /* 16-bit instruction. */
2065 dec_insn
.pc_inc
= 2;
2068 dec_insn
.insn
= (*instr_ptr
<< 16) |
2070 /* 32-bit instruction. */
2071 dec_insn
.pc_inc
= 4;
2074 /* Get second instruction. */
2075 if (mm_insn_16bit(*instr_ptr
)) {
2076 /* Duplicate the half-word. */
2077 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2079 /* 16-bit instruction. */
2080 dec_insn
.next_pc_inc
= 2;
2082 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2084 /* 32-bit instruction. */
2085 dec_insn
.next_pc_inc
= 4;
2087 dec_insn
.micro_mips_mode
= 1;
2089 if ((get_user(dec_insn
.insn
,
2090 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2091 (get_user(dec_insn
.next_insn
,
2092 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2093 MIPS_FPU_EMU_INC_STATS(errors
);
2096 dec_insn
.pc_inc
= 4;
2097 dec_insn
.next_pc_inc
= 4;
2098 dec_insn
.micro_mips_mode
= 0;
2101 if ((dec_insn
.insn
== 0) ||
2102 ((dec_insn
.pc_inc
== 2) &&
2103 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2104 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2107 * The 'ieee754_csr' is an alias of
2108 * ctx->fcr31. No need to copy ctx->fcr31 to
2109 * ieee754_csr. But ieee754_csr.rm is ieee
2110 * library modes. (not mips rounding mode)
2112 /* convert to ieee library modes */
2113 ieee754_csr
.rm
= ieee_rm
[ieee754_csr
.rm
];
2114 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2115 /* revert to mips rounding mode */
2116 ieee754_csr
.rm
= mips_rm
[ieee754_csr
.rm
];
2125 } while (xcp
->cp0_epc
> prevepc
);
2127 /* SIGILL indicates a non-fpu instruction */
2128 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2129 /* but if epc has advanced, then ignore it */
2135 #ifdef CONFIG_DEBUG_FS
2137 static int fpuemu_stat_get(void *data
, u64
*val
)
2140 unsigned long sum
= 0;
2141 for_each_online_cpu(cpu
) {
2142 struct mips_fpu_emulator_stats
*ps
;
2144 ps
= &per_cpu(fpuemustats
, cpu
);
2145 pv
= (void *)ps
+ (unsigned long)data
;
2146 sum
+= local_read(pv
);
2151 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat
, fpuemu_stat_get
, NULL
, "%llu\n");
2153 extern struct dentry
*mips_debugfs_dir
;
2154 static int __init
debugfs_fpuemu(void)
2156 struct dentry
*d
, *dir
;
2158 if (!mips_debugfs_dir
)
2160 dir
= debugfs_create_dir("fpuemustats", mips_debugfs_dir
);
2164 #define FPU_STAT_CREATE(M) \
2166 d = debugfs_create_file(#M , S_IRUGO, dir, \
2167 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2168 &fops_fpuemu_stat); \
2173 FPU_STAT_CREATE(emulated
);
2174 FPU_STAT_CREATE(loads
);
2175 FPU_STAT_CREATE(stores
);
2176 FPU_STAT_CREATE(cp1ops
);
2177 FPU_STAT_CREATE(cp1xops
);
2178 FPU_STAT_CREATE(errors
);
2182 __initcall(debugfs_fpuemu
);