arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/config.h>
  23 #include <linux/init.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/sched.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/time.h>
  29 #include <linux/timex.h>
  30 #include <linux/mc146818rtc.h>
  31
  32 #include <asm/mipsregs.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/hardirq.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44 #include <asm/mips-boards/maltaint.h>
  45 #include <asm/mc146818-time.h>
  46
  47 unsigned long cpu_khz;
  48
  49 #if defined(CONFIG_MIPS_ATLAS)
  50 static char display_string[] = "        LINUX ON ATLAS       ";
  51 #endif
  52 #if defined(CONFIG_MIPS_MALTA)
  53 static char display_string[] = "        LINUX ON MALTA       ";
  54 #endif
  55 #if defined(CONFIG_MIPS_SEAD)
  56 static char display_string[] = "        LINUX ON SEAD       ";
  57 #endif
  58 static unsigned int display_count = 0;
  59 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  60
  61 static unsigned int timer_tick_count=0;
  62 static int mips_cpu_timer_irq;
  63
  64 static void mips_timer_dispatch (struct pt_regs *regs)
  65 {
  66         do_IRQ (mips_cpu_timer_irq, regs);
  67 }
  68
  69 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  70 {
  71         irqreturn_t r;
  72
  73         r = timer_interrupt(irq, dev_id, regs);
  74
  75         if ((timer_tick_count++ % HZ) == 0) {
  76                 mips_display_message(&display_string[display_count++]);
  77                 if (display_count == MAX_DISPLAY_COUNT)
  78                         display_count = 0;
  79         }
  80
  81         return r;
  82 }
  83
  84 /*
  85  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
  86  */
  87 static unsigned int __init estimate_cpu_frequency(void)
  88 {
  89         unsigned int prid = read_c0_prid() & 0xffff00;
  90         unsigned int count;
  91
  92 #ifdef CONFIG_MIPS_SEAD
  93         /*
  94          * The SEAD board doesn't have a real time clock, so we can't
  95          * really calculate the timer frequency
  96          * For now we hardwire the SEAD board frequency to 12MHz.
  97          */
  98
  99         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 100             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 101                 count = 12000000;
 102         else
 103                 count = 6000000;
 104 #endif
 105 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 106         unsigned int flags;
 107
 108         local_irq_save(flags);
 109
 110         /* Start counter exactly on falling edge of update flag */
 111         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 112         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 113
 114         /* Start r4k counter. */
 115         write_c0_count(0);
 116
 117         /* Read counter exactly on falling edge of update flag */
 118         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 119         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 120
 121         count = read_c0_count();
 122
 123         /* restore interrupts */
 124         local_irq_restore(flags);
 125 #endif
 126
 127         mips_hpt_frequency = count;
 128         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 129             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 130                 count *= 2;
 131
 132         count += 5000;    /* round */
 133         count -= count%10000;
 134
 135         return count;
 136 }
 137
 138 unsigned long __init mips_rtc_get_time(void)
 139 {
 140         return mc146818_get_cmos_time();
 141 }
 142
 143 void __init mips_time_init(void)
 144 {
 145         unsigned int est_freq, flags;
 146
 147         local_irq_save(flags);
 148
 149         /* Set Data mode - binary. */
 150         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 151
 152         est_freq = estimate_cpu_frequency ();
 153
 154         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 155                (est_freq%1000000)*100/1000000);
 156
 157         cpu_khz = est_freq / 1000;
 158
 159         local_irq_restore(flags);
 160 }
 161
 162 void __init mips_timer_setup(struct irqaction *irq)
 163 {
 164         if (cpu_has_veic) {
 165                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 166                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 167         }
 168         else {
 169                 if (cpu_has_vint)
 170                         set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 171                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 172         }
 173
 174
 175         /* we are using the cpu counter for timer interrupts */
 176         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 177         setup_irq(mips_cpu_timer_irq, irq);
 178
 179
 180         /* to generate the first timer interrupt */
 181         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 182 }