arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/irq.h>
  35 #include <asm/div64.h>
  36 #include <asm/cpu.h>
  37 #include <asm/time.h>
  38 #include <asm/mc146818-time.h>
  39 #include <asm/msc01_ic.h>
  40
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/prom.h>
  43
  44 #ifdef CONFIG_MIPS_ATLAS
  45 #include <asm/mips-boards/atlasint.h>
  46 #endif
  47 #ifdef CONFIG_MIPS_MALTA
  48 #include <asm/mips-boards/maltaint.h>
  49 #endif
  50
  51 unsigned long cpu_khz;
  52
  53 #if defined(CONFIG_MIPS_ATLAS)
  54 static char display_string[] = "        LINUX ON ATLAS       ";
  55 #endif
  56 #if defined(CONFIG_MIPS_MALTA)
  57 #if defined(CONFIG_MIPS_MT_SMTC)
  58 static char display_string[] = "       SMTC LINUX ON MALTA       ";
  59 #else
  60 static char display_string[] = "        LINUX ON MALTA       ";
  61 #endif /* CONFIG_MIPS_MT_SMTC */
  62 #endif
  63 #if defined(CONFIG_MIPS_SEAD)
  64 static char display_string[] = "        LINUX ON SEAD       ";
  65 #endif
  66 static unsigned int display_count;
  67 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  68
  69 #define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
  70
  71 static unsigned int timer_tick_count;
  72 static int mips_cpu_timer_irq;
  73 extern void smtc_timer_broadcast(int);
  74
  75 static inline void scroll_display_message(void)
  76 {
  77         if ((timer_tick_count++ % HZ) == 0) {
  78                 mips_display_message(&display_string[display_count++]);
  79                 if (display_count == MAX_DISPLAY_COUNT)
  80                         display_count = 0;
  81         }
  82 }
  83
  84 static void mips_timer_dispatch(void)
  85 {
  86         do_IRQ(mips_cpu_timer_irq);
  87 }
  88
  89 /*
  90  * Redeclare until I get around mopping the timer code insanity on MIPS.
  91  */
  92 extern int null_perf_irq(void);
  93
  94 extern int (*perf_irq)(void);
  95
  96 irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
  97 {
  98         int cpu = smp_processor_id();
  99
 100 #ifdef CONFIG_MIPS_MT_SMTC
 101         /*
 102          *  In an SMTC system, one Count/Compare set exists per VPE.
 103          *  Which TC within a VPE gets the interrupt is essentially
 104          *  random - we only know that it shouldn't be one with
 105          *  IXMT set. Whichever TC gets the interrupt needs to
 106          *  send special interprocessor interrupts to the other
 107          *  TCs to make sure that they schedule, etc.
 108          *
 109          *  That code is specific to the SMTC kernel, not to
 110          *  the a particular platform, so it's invoked from
 111          *  the general MIPS timer_interrupt routine.
 112          */
 113
 114         int vpflags;
 115
 116         /*
 117          * We could be here due to timer interrupt,
 118          * perf counter overflow, or both.
 119          */
 120         if (read_c0_cause() & (1 << 26))
 121                 perf_irq();
 122
 123         if (read_c0_cause() & (1 << 30)) {
 124                 /* If timer interrupt, make it de-assert */
 125                 write_c0_compare (read_c0_count() - 1);
 126                 /*
 127                  * DVPE is necessary so long as cross-VPE interrupts
 128                  * are done via read-modify-write of Cause register.
 129                  */
 130                 vpflags = dvpe();
 131                 clear_c0_cause(CPUCTR_IMASKBIT);
 132                 evpe(vpflags);
 133                 /*
 134                  * There are things we only want to do once per tick
 135                  * in an "MP" system.   One TC of each VPE will take
 136                  * the actual timer interrupt.  The others will get
 137                  * timer broadcast IPIs. We use whoever it is that takes
 138                  * the tick on VPE 0 to run the full timer_interrupt().
 139                  */
 140                 if (cpu_data[cpu].vpe_id == 0) {
 141                                 timer_interrupt(irq, NULL);
 142                                 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 143                                 scroll_display_message();
 144                 } else {
 145                         write_c0_compare(read_c0_count() +
 146                                          (mips_hpt_frequency/HZ));
 147                         local_timer_interrupt(irq, dev_id);
 148                         smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 149                 }
 150         }
 151 #else /* CONFIG_MIPS_MT_SMTC */
 152         int r2 = cpu_has_mips_r2;
 153
 154         if (cpu == 0) {
 155                 /*
 156                  * CPU 0 handles the global timer interrupt job and process
 157                  * accounting resets count/compare registers to trigger next
 158                  * timer int.
 159                  */
 160                 if (!r2 || (read_c0_cause() & (1 << 26)))
 161                         if (perf_irq())
 162                                 goto out;
 163
 164                 /* we keep interrupt disabled all the time */
 165                 if (!r2 || (read_c0_cause() & (1 << 30)))
 166                         timer_interrupt(irq, NULL);
 167
 168                 scroll_display_message();
 169         } else {
 170                 /* Everyone else needs to reset the timer int here as
 171                    ll_local_timer_interrupt doesn't */
 172                 /*
 173                  * FIXME: need to cope with counter underflow.
 174                  * More support needs to be added to kernel/time for
 175                  * counter/timer interrupts on multiple CPU's
 176                  */
 177                 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 178
 179                 /*
 180                  * Other CPUs should do profiling and process accounting
 181                  */
 182                 local_timer_interrupt(irq, dev_id);
 183         }
 184 out:
 185 #endif /* CONFIG_MIPS_MT_SMTC */
 186         return IRQ_HANDLED;
 187 }
 188
 189 /*
 190  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
 191  */
 192 static unsigned int __init estimate_cpu_frequency(void)
 193 {
 194         unsigned int prid = read_c0_prid() & 0xffff00;
 195         unsigned int count;
 196
 197 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
 198         /*
 199          * The SEAD board doesn't have a real time clock, so we can't
 200          * really calculate the timer frequency
 201          * For now we hardwire the SEAD board frequency to 12MHz.
 202          */
 203
 204         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 205             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 206                 count = 12000000;
 207         else
 208                 count = 6000000;
 209 #endif
 210 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 211         unsigned int flags;
 212
 213         local_irq_save(flags);
 214
 215         /* Start counter exactly on falling edge of update flag */
 216         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 217         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 218
 219         /* Start r4k counter. */
 220         write_c0_count(0);
 221
 222         /* Read counter exactly on falling edge of update flag */
 223         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 224         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 225
 226         count = read_c0_count();
 227
 228         /* restore interrupts */
 229         local_irq_restore(flags);
 230 #endif
 231
 232         mips_hpt_frequency = count;
 233         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 234             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 235                 count *= 2;
 236
 237         count += 5000;    /* round */
 238         count -= count%10000;
 239
 240         return count;
 241 }
 242
 243 unsigned long __init mips_rtc_get_time(void)
 244 {
 245         return mc146818_get_cmos_time();
 246 }
 247
 248 void __init mips_time_init(void)
 249 {
 250         unsigned int est_freq;
 251
 252         /* Set Data mode - binary. */
 253         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 254
 255         est_freq = estimate_cpu_frequency ();
 256
 257         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 258                (est_freq%1000000)*100/1000000);
 259
 260         cpu_khz = est_freq / 1000;
 261 }
 262
 263 void __init plat_timer_setup(struct irqaction *irq)
 264 {
 265         if (cpu_has_veic) {
 266                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 267                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 268         }
 269         else {
 270                 if (cpu_has_vint)
 271                         set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 272                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 273         }
 274
 275
 276         /* we are using the cpu counter for timer interrupts */
 277         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 278 #ifdef CONFIG_MIPS_MT_SMTC
 279         setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT);
 280 #else
 281         setup_irq(mips_cpu_timer_irq, irq);
 282 #endif /* CONFIG_MIPS_MT_SMTC */
 283
 284 #ifdef CONFIG_SMP
 285         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 286            on seperate cpu's the first one tries to handle the second interrupt.
 287            The effect is that the int remains disabled on the second cpu.
 288            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 289         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 290 #endif
 291
 292         /* to generate the first timer interrupt */
 293         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 294 }