arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/hardirq.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44 #include <asm/mips-boards/maltaint.h>
  45 #include <asm/mc146818-time.h>
  46
  47 unsigned long cpu_khz;
  48
  49 #if defined(CONFIG_MIPS_ATLAS)
  50 static char display_string[] = "        LINUX ON ATLAS       ";
  51 #endif
  52 #if defined(CONFIG_MIPS_MALTA)
  53 #if defined(CONFIG_MIPS_MT_SMTC)
  54 static char display_string[] = "       SMTC LINUX ON MALTA       ";
  55 #else
  56 static char display_string[] = "        LINUX ON MALTA       ";
  57 #endif /* CONFIG_MIPS_MT_SMTC */
  58 #endif
  59 #if defined(CONFIG_MIPS_SEAD)
  60 static char display_string[] = "        LINUX ON SEAD       ";
  61 #endif
  62 static unsigned int display_count;
  63 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  64
  65 #define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
  66
  67 static unsigned int timer_tick_count;
  68 static int mips_cpu_timer_irq;
  69 extern void smtc_timer_broadcast(int);
  70
  71 static inline void scroll_display_message(void)
  72 {
  73         if ((timer_tick_count++ % HZ) == 0) {
  74                 mips_display_message(&display_string[display_count++]);
  75                 if (display_count == MAX_DISPLAY_COUNT)
  76                         display_count = 0;
  77         }
  78 }
  79
  80 static void mips_timer_dispatch (struct pt_regs *regs)
  81 {
  82         do_IRQ (mips_cpu_timer_irq, regs);
  83 }
  84
  85 /*
  86  * Redeclare until I get around mopping the timer code insanity on MIPS.
  87  */
  88 extern int null_perf_irq(struct pt_regs *regs);
  89
  90 extern int (*perf_irq)(struct pt_regs *regs);
  91
  92 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  93 {
  94         int cpu = smp_processor_id();
  95         int r2 = cpu_has_mips_r2;
  96
  97 #ifdef CONFIG_MIPS_MT_SMTC
  98         /*
  99          *  In an SMTC system, one Count/Compare set exists per VPE.
 100          *  Which TC within a VPE gets the interrupt is essentially
 101          *  random - we only know that it shouldn't be one with
 102          *  IXMT set. Whichever TC gets the interrupt needs to
 103          *  send special interprocessor interrupts to the other
 104          *  TCs to make sure that they schedule, etc.
 105          *
 106          *  That code is specific to the SMTC kernel, not to
 107          *  the a particular platform, so it's invoked from
 108          *  the general MIPS timer_interrupt routine.
 109          */
 110
 111         /*
 112          * DVPE is necessary so long as cross-VPE interrupts
 113          * are done via read-modify-write of Cause register.
 114          */
 115         int vpflags = dvpe();
 116         write_c0_compare (read_c0_count() - 1);
 117         clear_c0_cause(CPUCTR_IMASKBIT);
 118         evpe(vpflags);
 119
 120         if (cpu_data[cpu].vpe_id == 0) {
 121                 timer_interrupt(irq, dev_id, regs);
 122                 scroll_display_message();
 123         } else
 124                 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
 125         smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 126
 127         if (cpu != 0)
 128                 /*
 129                  * Other CPUs should do profiling and process accounting
 130                  */
 131                 local_timer_interrupt(irq, dev_id, regs);
 132
 133 #else /* CONFIG_MIPS_MT_SMTC */
 134         if (cpu == 0) {
 135                 /*
 136                  * CPU 0 handles the global timer interrupt job and process
 137                  * accounting resets count/compare registers to trigger next
 138                  * timer int.
 139                  */
 140                 if (!r2 || (read_c0_cause() & (1 << 26)))
 141                         if (perf_irq(regs))
 142                                 goto out;
 143
 144                 /* we keep interrupt disabled all the time */
 145                 if (!r2 || (read_c0_cause() & (1 << 30)))
 146                         timer_interrupt(irq, NULL, regs);
 147
 148                 scroll_display_message();
 149         } else {
 150                 /* Everyone else needs to reset the timer int here as
 151                    ll_local_timer_interrupt doesn't */
 152                 /*
 153                  * FIXME: need to cope with counter underflow.
 154                  * More support needs to be added to kernel/time for
 155                  * counter/timer interrupts on multiple CPU's
 156                  */
 157                 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 158
 159                 /*
 160                  * Other CPUs should do profiling and process accounting
 161                  */
 162                 local_timer_interrupt(irq, dev_id, regs);
 163         }
 164 #endif /* CONFIG_MIPS_MT_SMTC */
 165
 166 out:
 167         return IRQ_HANDLED;
 168 }
 169
 170 /*
 171  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
 172  */
 173 static unsigned int __init estimate_cpu_frequency(void)
 174 {
 175         unsigned int prid = read_c0_prid() & 0xffff00;
 176         unsigned int count;
 177
 178 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
 179         /*
 180          * The SEAD board doesn't have a real time clock, so we can't
 181          * really calculate the timer frequency
 182          * For now we hardwire the SEAD board frequency to 12MHz.
 183          */
 184
 185         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 186             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 187                 count = 12000000;
 188         else
 189                 count = 6000000;
 190 #endif
 191 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 192         unsigned int flags;
 193
 194         local_irq_save(flags);
 195
 196         /* Start counter exactly on falling edge of update flag */
 197         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 198         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 199
 200         /* Start r4k counter. */
 201         write_c0_count(0);
 202
 203         /* Read counter exactly on falling edge of update flag */
 204         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 205         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 206
 207         count = read_c0_count();
 208
 209         /* restore interrupts */
 210         local_irq_restore(flags);
 211 #endif
 212
 213         mips_hpt_frequency = count;
 214         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 215             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 216                 count *= 2;
 217
 218         count += 5000;    /* round */
 219         count -= count%10000;
 220
 221         return count;
 222 }
 223
 224 unsigned long __init mips_rtc_get_time(void)
 225 {
 226         return mc146818_get_cmos_time();
 227 }
 228
 229 void __init mips_time_init(void)
 230 {
 231         unsigned int est_freq, flags;
 232
 233         local_irq_save(flags);
 234
 235         /* Set Data mode - binary. */
 236         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 237
 238         est_freq = estimate_cpu_frequency ();
 239
 240         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 241                (est_freq%1000000)*100/1000000);
 242
 243         cpu_khz = est_freq / 1000;
 244
 245         local_irq_restore(flags);
 246 }
 247
 248 void __init mips_timer_setup(struct irqaction *irq)
 249 {
 250         if (cpu_has_veic) {
 251                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 252                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 253         }
 254         else {
 255                 if (cpu_has_vint)
 256                         set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 257                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 258         }
 259
 260
 261         /* we are using the cpu counter for timer interrupts */
 262         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 263 #ifdef CONFIG_MIPS_MT_SMTC
 264         setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT);
 265 #else
 266         setup_irq(mips_cpu_timer_irq, irq);
 267 #endif /* CONFIG_MIPS_MT_SMTC */
 268
 269 #ifdef CONFIG_SMP
 270         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 271            on seperate cpu's the first one tries to handle the second interrupt.
 272            The effect is that the int remains disabled on the second cpu.
 273            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 274         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 275 #endif
 276
 277         /* to generate the first timer interrupt */
 278         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 279 }