arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/config.h>
  23 #include <linux/init.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/sched.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/time.h>
  29 #include <linux/timex.h>
  30 #include <linux/mc146818rtc.h>
  31
  32 #include <asm/mipsregs.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/hardirq.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44 #include <asm/mips-boards/maltaint.h>
  45 #include <asm/mc146818-time.h>
  46
  47 unsigned long cpu_khz;
  48
  49 #if defined(CONFIG_MIPS_ATLAS)
  50 static char display_string[] = "        LINUX ON ATLAS       ";
  51 #endif
  52 #if defined(CONFIG_MIPS_MALTA)
  53 static char display_string[] = "        LINUX ON MALTA       ";
  54 #endif
  55 #if defined(CONFIG_MIPS_SEAD)
  56 static char display_string[] = "        LINUX ON SEAD       ";
  57 #endif
  58 static unsigned int display_count = 0;
  59 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  60
  61 static unsigned int timer_tick_count=0;
  62 static int mips_cpu_timer_irq;
  63
  64 static inline void scroll_display_message(void)
  65 {
  66         if ((timer_tick_count++ % HZ) == 0) {
  67                 mips_display_message(&display_string[display_count++]);
  68                 if (display_count == MAX_DISPLAY_COUNT)
  69                         display_count = 0;
  70         }
  71 }
  72
  73 static void mips_timer_dispatch (struct pt_regs *regs)
  74 {
  75         do_IRQ (mips_cpu_timer_irq, regs);
  76 }
  77
  78 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  79 {
  80 #ifdef CONFIG_SMP
  81         int cpu = smp_processor_id();
  82
  83         if (cpu == 0) {
  84                 /*
  85                  * CPU 0 handles the global timer interrupt job and process accounting
  86                  * resets count/compare registers to trigger next timer int.
  87                  */
  88                 (void) timer_interrupt(irq, dev_id, regs);
  89                 scroll_display_message();
  90         }
  91         else {
  92                 /* Everyone else needs to reset the timer int here as
  93                    ll_local_timer_interrupt doesn't */
  94                 /*
  95                  * FIXME: need to cope with counter underflow.
  96                  * More support needs to be added to kernel/time for
  97                  * counter/timer interrupts on multiple CPU's
  98                  */
  99                 write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ));
 100                 /*
 101                  * other CPUs should do profiling and process accounting
 102                  */
 103                 local_timer_interrupt (irq, dev_id, regs);
 104         }
 105
 106         return IRQ_HANDLED;
 107 #else
 108         irqreturn_t r;
 109
 110         r = timer_interrupt(irq, dev_id, regs);
 111
 112         scroll_display_message();
 113
 114         return r;
 115 #endif
 116 }
 117
 118 /*
 119  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
 120  */
 121 static unsigned int __init estimate_cpu_frequency(void)
 122 {
 123         unsigned int prid = read_c0_prid() & 0xffff00;
 124         unsigned int count;
 125
 126 #ifdef CONFIG_MIPS_SEAD
 127         /*
 128          * The SEAD board doesn't have a real time clock, so we can't
 129          * really calculate the timer frequency
 130          * For now we hardwire the SEAD board frequency to 12MHz.
 131          */
 132
 133         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 134             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 135                 count = 12000000;
 136         else
 137                 count = 6000000;
 138 #endif
 139 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 140         unsigned int flags;
 141
 142         local_irq_save(flags);
 143
 144         /* Start counter exactly on falling edge of update flag */
 145         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 146         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 147
 148         /* Start r4k counter. */
 149         write_c0_count(0);
 150
 151         /* Read counter exactly on falling edge of update flag */
 152         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 153         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 154
 155         count = read_c0_count();
 156
 157         /* restore interrupts */
 158         local_irq_restore(flags);
 159 #endif
 160
 161         mips_hpt_frequency = count;
 162         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 163             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 164                 count *= 2;
 165
 166         count += 5000;    /* round */
 167         count -= count%10000;
 168
 169         return count;
 170 }
 171
 172 unsigned long __init mips_rtc_get_time(void)
 173 {
 174         return mc146818_get_cmos_time();
 175 }
 176
 177 void __init mips_time_init(void)
 178 {
 179         unsigned int est_freq, flags;
 180
 181         local_irq_save(flags);
 182
 183         /* Set Data mode - binary. */
 184         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 185
 186         est_freq = estimate_cpu_frequency ();
 187
 188         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 189                (est_freq%1000000)*100/1000000);
 190
 191         cpu_khz = est_freq / 1000;
 192
 193         local_irq_restore(flags);
 194 }
 195
 196 void __init mips_timer_setup(struct irqaction *irq)
 197 {
 198         if (cpu_has_veic) {
 199                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 200                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 201         }
 202         else {
 203                 if (cpu_has_vint)
 204                         set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 205                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 206         }
 207
 208
 209         /* we are using the cpu counter for timer interrupts */
 210         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 211         setup_irq(mips_cpu_timer_irq, irq);
 212
 213 #ifdef CONFIG_SMP
 214         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 215            on seperate cpu's the first one tries to handle the second interrupt.
 216            The effect is that the int remains disabled on the second cpu.
 217            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 218         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 219 #endif
 220
 221         /* to generate the first timer interrupt */
 222         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 223 }