arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/hardirq.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44
  45 #ifdef CONFIG_MIPS_ATLAS
  46 #include <asm/mips-boards/atlasint.h>
  47 #endif
  48 #ifdef CONFIG_MIPS_MALTA
  49 #include <asm/mips-boards/maltaint.h>
  50 #endif
  51
  52 unsigned long cpu_khz;
  53
  54 #if defined(CONFIG_MIPS_ATLAS)
  55 static char display_string[] = "        LINUX ON ATLAS       ";
  56 #endif
  57 #if defined(CONFIG_MIPS_MALTA)
  58 #if defined(CONFIG_MIPS_MT_SMTC)
  59 static char display_string[] = "       SMTC LINUX ON MALTA       ";
  60 #else
  61 static char display_string[] = "        LINUX ON MALTA       ";
  62 #endif /* CONFIG_MIPS_MT_SMTC */
  63 #endif
  64 #if defined(CONFIG_MIPS_SEAD)
  65 static char display_string[] = "        LINUX ON SEAD       ";
  66 #endif
  67 static unsigned int display_count;
  68 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  69
  70 #define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
  71
  72 static unsigned int timer_tick_count;
  73 static int mips_cpu_timer_irq;
  74 extern void smtc_timer_broadcast(int);
  75
  76 static inline void scroll_display_message(void)
  77 {
  78         if ((timer_tick_count++ % HZ) == 0) {
  79                 mips_display_message(&display_string[display_count++]);
  80                 if (display_count == MAX_DISPLAY_COUNT)
  81                         display_count = 0;
  82         }
  83 }
  84
  85 static void mips_timer_dispatch (struct pt_regs *regs)
  86 {
  87         do_IRQ (mips_cpu_timer_irq, regs);
  88 }
  89
  90 /*
  91  * Redeclare until I get around mopping the timer code insanity on MIPS.
  92  */
  93 extern int null_perf_irq(struct pt_regs *regs);
  94
  95 extern int (*perf_irq)(struct pt_regs *regs);
  96
  97 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  98 {
  99         int cpu = smp_processor_id();
 100
 101 #ifdef CONFIG_MIPS_MT_SMTC
 102         /*
 103          *  In an SMTC system, one Count/Compare set exists per VPE.
 104          *  Which TC within a VPE gets the interrupt is essentially
 105          *  random - we only know that it shouldn't be one with
 106          *  IXMT set. Whichever TC gets the interrupt needs to
 107          *  send special interprocessor interrupts to the other
 108          *  TCs to make sure that they schedule, etc.
 109          *
 110          *  That code is specific to the SMTC kernel, not to
 111          *  the a particular platform, so it's invoked from
 112          *  the general MIPS timer_interrupt routine.
 113          */
 114
 115         int vpflags;
 116
 117         /*
 118          * We could be here due to timer interrupt,
 119          * perf counter overflow, or both.
 120          */
 121         if (read_c0_cause() & (1 << 26))
 122                 perf_irq(regs);
 123
 124         if (read_c0_cause() & (1 << 30)) {
 125                 /* If timer interrupt, make it de-assert */
 126                 write_c0_compare (read_c0_count() - 1);
 127                 /*
 128                  * DVPE is necessary so long as cross-VPE interrupts
 129                  * are done via read-modify-write of Cause register.
 130                  */
 131                 vpflags = dvpe();
 132                 clear_c0_cause(CPUCTR_IMASKBIT);
 133                 evpe(vpflags);
 134                 /*
 135                  * There are things we only want to do once per tick
 136                  * in an "MP" system.   One TC of each VPE will take
 137                  * the actual timer interrupt.  The others will get
 138                  * timer broadcast IPIs. We use whoever it is that takes
 139                  * the tick on VPE 0 to run the full timer_interrupt().
 140                  */
 141                 if (cpu_data[cpu].vpe_id == 0) {
 142                                 timer_interrupt(irq, NULL, regs);
 143                                 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 144                                 scroll_display_message();
 145                 } else {
 146                         write_c0_compare(read_c0_count() +
 147                                          (mips_hpt_frequency/HZ));
 148                         local_timer_interrupt(irq, dev_id, regs);
 149                         smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 150                 }
 151         }
 152 #else /* CONFIG_MIPS_MT_SMTC */
 153         int r2 = cpu_has_mips_r2;
 154
 155         if (cpu == 0) {
 156                 /*
 157                  * CPU 0 handles the global timer interrupt job and process
 158                  * accounting resets count/compare registers to trigger next
 159                  * timer int.
 160                  */
 161                 if (!r2 || (read_c0_cause() & (1 << 26)))
 162                         if (perf_irq(regs))
 163                                 goto out;
 164
 165                 /* we keep interrupt disabled all the time */
 166                 if (!r2 || (read_c0_cause() & (1 << 30)))
 167                         timer_interrupt(irq, NULL, regs);
 168
 169                 scroll_display_message();
 170         } else {
 171                 /* Everyone else needs to reset the timer int here as
 172                    ll_local_timer_interrupt doesn't */
 173                 /*
 174                  * FIXME: need to cope with counter underflow.
 175                  * More support needs to be added to kernel/time for
 176                  * counter/timer interrupts on multiple CPU's
 177                  */
 178                 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 179
 180                 /*
 181                  * Other CPUs should do profiling and process accounting
 182                  */
 183                 local_timer_interrupt(irq, dev_id, regs);
 184         }
 185 out:
 186 #endif /* CONFIG_MIPS_MT_SMTC */
 187         return IRQ_HANDLED;
 188 }
 189
 190 /*
 191  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
 192  */
 193 static unsigned int __init estimate_cpu_frequency(void)
 194 {
 195         unsigned int prid = read_c0_prid() & 0xffff00;
 196         unsigned int count;
 197
 198 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
 199         /*
 200          * The SEAD board doesn't have a real time clock, so we can't
 201          * really calculate the timer frequency
 202          * For now we hardwire the SEAD board frequency to 12MHz.
 203          */
 204
 205         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 206             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 207                 count = 12000000;
 208         else
 209                 count = 6000000;
 210 #endif
 211 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 212         unsigned int flags;
 213
 214         local_irq_save(flags);
 215
 216         /* Start counter exactly on falling edge of update flag */
 217         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 218         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 219
 220         /* Start r4k counter. */
 221         write_c0_count(0);
 222
 223         /* Read counter exactly on falling edge of update flag */
 224         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 225         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 226
 227         count = read_c0_count();
 228
 229         /* restore interrupts */
 230         local_irq_restore(flags);
 231 #endif
 232
 233         mips_hpt_frequency = count;
 234         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 235             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 236                 count *= 2;
 237
 238         count += 5000;    /* round */
 239         count -= count%10000;
 240
 241         return count;
 242 }
 243
 244 unsigned long __init mips_rtc_get_time(void)
 245 {
 246         return mc146818_get_cmos_time();
 247 }
 248
 249 void __init mips_time_init(void)
 250 {
 251         unsigned int est_freq;
 252
 253         /* Set Data mode - binary. */
 254         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 255
 256         est_freq = estimate_cpu_frequency ();
 257
 258         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 259                (est_freq%1000000)*100/1000000);
 260
 261         cpu_khz = est_freq / 1000;
 262 }
 263
 264 void __init plat_timer_setup(struct irqaction *irq)
 265 {
 266         if (cpu_has_veic) {
 267                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 268                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 269         }
 270         else {
 271                 if (cpu_has_vint)
 272                         set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 273                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 274         }
 275
 276
 277         /* we are using the cpu counter for timer interrupts */
 278         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 279 #ifdef CONFIG_MIPS_MT_SMTC
 280         setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT);
 281 #else
 282         setup_irq(mips_cpu_timer_irq, irq);
 283 #endif /* CONFIG_MIPS_MT_SMTC */
 284
 285 #ifdef CONFIG_SMP
 286         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 287            on seperate cpu's the first one tries to handle the second interrupt.
 288            The effect is that the int remains disabled on the second cpu.
 289            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 290         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 291 #endif
 292
 293         /* to generate the first timer interrupt */
 294         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 295 }