arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/config.h>
  23 #include <linux/init.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/sched.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/time.h>
  29 #include <linux/timex.h>
  30 #include <linux/mc146818rtc.h>
  31
  32 #include <asm/mipsregs.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/hardirq.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44 #include <asm/mips-boards/maltaint.h>
  45 #include <asm/mc146818-time.h>
  46
  47 unsigned long cpu_khz;
  48
  49 #if defined(CONFIG_MIPS_ATLAS)
  50 static char display_string[] = "        LINUX ON ATLAS       ";
  51 #endif
  52 #if defined(CONFIG_MIPS_MALTA)
  53 static char display_string[] = "        LINUX ON MALTA       ";
  54 #endif
  55 #if defined(CONFIG_MIPS_SEAD)
  56 static char display_string[] = "        LINUX ON SEAD       ";
  57 #endif
  58 static unsigned int display_count = 0;
  59 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  60
  61 static unsigned int timer_tick_count=0;
  62 static int mips_cpu_timer_irq;
  63
  64 static inline void scroll_display_message(void)
  65 {
  66         if ((timer_tick_count++ % HZ) == 0) {
  67                 mips_display_message(&display_string[display_count++]);
  68                 if (display_count == MAX_DISPLAY_COUNT)
  69                         display_count = 0;
  70         }
  71 }
  72
  73 static void mips_timer_dispatch (struct pt_regs *regs)
  74 {
  75         do_IRQ (mips_cpu_timer_irq, regs);
  76 }
  77
  78 extern int null_perf_irq(struct pt_regs *regs);
  79
  80 extern int (*perf_irq)(struct pt_regs *regs);
  81
  82 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  83 {
  84         int r2 = cpu_has_mips_r2;
  85         int cpu = smp_processor_id();
  86
  87         if (cpu == 0) {
  88                 /*
  89                  * CPU 0 handles the global timer interrupt job and process
  90                  * accounting resets count/compare registers to trigger next
  91                  * timer int.
  92                  */
  93                 if (!r2 || (read_c0_cause() & (1 << 26)))
  94                         if (perf_irq(regs))
  95                                 goto out;
  96
  97                 /* we keep interrupt disabled all the time */
  98                 if (!r2 || (read_c0_cause() & (1 << 30)))
  99                         timer_interrupt(irq, NULL, regs);
 100
 101                 scroll_display_message();
 102         } else {
 103                 /* Everyone else needs to reset the timer int here as
 104                    ll_local_timer_interrupt doesn't */
 105                 /*
 106                  * FIXME: need to cope with counter underflow.
 107                  * More support needs to be added to kernel/time for
 108                  * counter/timer interrupts on multiple CPU's
 109                  */
 110                 write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ));
 111                 /*
 112                  * other CPUs should do profiling and process accounting
 113                  */
 114                 local_timer_interrupt (irq, dev_id, regs);
 115         }
 116
 117 out:
 118         return IRQ_HANDLED;
 119 }
 120
 121 /*
 122  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
 123  */
 124 static unsigned int __init estimate_cpu_frequency(void)
 125 {
 126         unsigned int prid = read_c0_prid() & 0xffff00;
 127         unsigned int count;
 128
 129 #ifdef CONFIG_MIPS_SEAD
 130         /*
 131          * The SEAD board doesn't have a real time clock, so we can't
 132          * really calculate the timer frequency
 133          * For now we hardwire the SEAD board frequency to 12MHz.
 134          */
 135
 136         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 137             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 138                 count = 12000000;
 139         else
 140                 count = 6000000;
 141 #endif
 142 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 143         unsigned int flags;
 144
 145         local_irq_save(flags);
 146
 147         /* Start counter exactly on falling edge of update flag */
 148         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 149         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 150
 151         /* Start r4k counter. */
 152         write_c0_count(0);
 153
 154         /* Read counter exactly on falling edge of update flag */
 155         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 156         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 157
 158         count = read_c0_count();
 159
 160         /* restore interrupts */
 161         local_irq_restore(flags);
 162 #endif
 163
 164         mips_hpt_frequency = count;
 165         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 166             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 167                 count *= 2;
 168
 169         count += 5000;    /* round */
 170         count -= count%10000;
 171
 172         return count;
 173 }
 174
 175 unsigned long __init mips_rtc_get_time(void)
 176 {
 177         return mc146818_get_cmos_time();
 178 }
 179
 180 void __init mips_time_init(void)
 181 {
 182         unsigned int est_freq, flags;
 183
 184         local_irq_save(flags);
 185
 186         /* Set Data mode - binary. */
 187         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 188
 189         est_freq = estimate_cpu_frequency ();
 190
 191         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 192                (est_freq%1000000)*100/1000000);
 193
 194         cpu_khz = est_freq / 1000;
 195
 196         local_irq_restore(flags);
 197 }
 198
 199 void __init mips_timer_setup(struct irqaction *irq)
 200 {
 201         if (cpu_has_veic) {
 202                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 203                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 204         }
 205         else {
 206                 if (cpu_has_vint)
 207                         set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 208                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 209         }
 210
 211
 212         /* we are using the cpu counter for timer interrupts */
 213         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 214         setup_irq(mips_cpu_timer_irq, irq);
 215
 216 #ifdef CONFIG_SMP
 217         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 218            on seperate cpu's the first one tries to handle the second interrupt.
 219            The effect is that the int remains disabled on the second cpu.
 220            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 221         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 222 #endif
 223
 224         /* to generate the first timer interrupt */
 225         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 226 }