arch/mips/mips-boards/malta/malta_int.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
   4  * Copyright (C) 2001 Ralf Baechle
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Routines for generic manipulation of the interrupts found on the MIPS
  20  * Malta board.
  21  * The interrupt controller is located in the South Bridge a PIIX4 device
  22  * with two internal 82C95 interrupt controllers.
  23  */
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/kernel_stat.h>
  30 #include <linux/random.h>
  31
  32 #include <asm/i8259.h>
  33 #include <asm/irq_cpu.h>
  34 #include <asm/io.h>
  35 #include <asm/mips-boards/malta.h>
  36 #include <asm/mips-boards/maltaint.h>
  37 #include <asm/mips-boards/piix4.h>
  38 #include <asm/gt64120.h>
  39 #include <asm/mips-boards/generic.h>
  40 #include <asm/mips-boards/msc01_pci.h>
  41 #include <asm/msc01_ic.h>
  42
  43 extern asmlinkage void mipsIRQ(void);
  44 extern void mips_timer_interrupt(void);
  45
  46 static DEFINE_SPINLOCK(mips_irq_lock);
  47
  48 static inline int mips_pcibios_iack(void)
  49 {
  50         int irq;
  51         u32 dummy;
  52
  53         /*
  54          * Determine highest priority pending interrupt by performing
  55          * a PCI Interrupt Acknowledge cycle.
  56          */
  57         switch(mips_revision_corid) {
  58         case MIPS_REVISION_CORID_CORE_MSC:
  59         case MIPS_REVISION_CORID_CORE_FPGA2:
  60         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
  61                 MSC_READ(MSC01_PCI_IACK, irq);
  62                 irq &= 0xff;
  63                 break;
  64         case MIPS_REVISION_CORID_QED_RM5261:
  65         case MIPS_REVISION_CORID_CORE_LV:
  66         case MIPS_REVISION_CORID_CORE_FPGA:
  67         case MIPS_REVISION_CORID_CORE_FPGAR2:
  68                 irq = GT_READ(GT_PCI0_IACK_OFS);
  69                 irq &= 0xff;
  70                 break;
  71         case MIPS_REVISION_CORID_BONITO64:
  72         case MIPS_REVISION_CORID_CORE_20K:
  73         case MIPS_REVISION_CORID_CORE_EMUL_BON:
  74                 /* The following will generate a PCI IACK cycle on the
  75                  * Bonito controller. It's a little bit kludgy, but it
  76                  * was the easiest way to implement it in hardware at
  77                  * the given time.
  78                  */
  79                 BONITO_PCIMAP_CFG = 0x20000;
  80
  81                 /* Flush Bonito register block */
  82                 dummy = BONITO_PCIMAP_CFG;
  83                 iob();    /* sync */
  84
  85                 irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
  86                 iob();    /* sync */
  87                 irq &= 0xff;
  88                 BONITO_PCIMAP_CFG = 0;
  89                 break;
  90         default:
  91                 printk("Unknown Core card, don't know the system controller.\n");
  92                 return -1;
  93         }
  94         return irq;
  95 }
  96
  97 static inline int get_int(void)
  98 {
  99         unsigned long flags;
 100         int irq;
 101         spin_lock_irqsave(&mips_irq_lock, flags);
 102
 103         irq = mips_pcibios_iack();
 104
 105         /*
 106          * IRQ7 is used to detect spurious interrupts.
 107          * The interrupt acknowledge cycle returns IRQ7, if no
 108          * interrupts is requested.
 109          * We can differentiate between this situation and a
 110          * "Normal" IRQ7 by reading the ISR.
 111          */
 112         if (irq == 7)
 113         {
 114                 outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
 115                      PIIX4_ICTLR1_OCW3);
 116                 if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
 117                         irq = -1; /* Spurious interrupt */
 118                         printk("We got a spurious interrupt from PIIX4.\n");
 119                         atomic_inc(&irq_err_count);
 120                 }
 121         }
 122
 123         spin_unlock_irqrestore(&mips_irq_lock, flags);
 124
 125         return irq;
 126 }
 127
 128 void malta_hw0_irqdispatch(struct pt_regs *regs)
 129 {
 130         int irq;
 131
 132         irq = get_int();
 133         if (irq < 0)
 134                 return;  /* interrupt has already been cleared */
 135
 136         do_IRQ(MALTA_INT_BASE+irq, regs);
 137 }
 138
 139 void corehi_irqdispatch(struct pt_regs *regs)
 140 {
 141         unsigned int intrcause,datalo,datahi;
 142         unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
 143
 144         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
 145         printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
 146 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
 147
 148         /* Read all the registers and then print them as there is a
 149            problem with interspersed printk's upsetting the Bonito controller.
 150            Do it for the others too.
 151         */
 152
 153         switch(mips_revision_corid) {
 154         case MIPS_REVISION_CORID_CORE_MSC:
 155         case MIPS_REVISION_CORID_CORE_FPGA2:
 156         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 157                 ll_msc_irq(regs);
 158                 break;
 159         case MIPS_REVISION_CORID_QED_RM5261:
 160         case MIPS_REVISION_CORID_CORE_LV:
 161         case MIPS_REVISION_CORID_CORE_FPGA:
 162         case MIPS_REVISION_CORID_CORE_FPGAR2:
 163                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
 164                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 165                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 166                 printk("GT_INTRCAUSE = %08x\n", intrcause);
 167                 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
 168                 break;
 169         case MIPS_REVISION_CORID_BONITO64:
 170         case MIPS_REVISION_CORID_CORE_20K:
 171         case MIPS_REVISION_CORID_CORE_EMUL_BON:
 172                 pcibadaddr = BONITO_PCIBADADDR;
 173                 pcimstat = BONITO_PCIMSTAT;
 174                 intisr = BONITO_INTISR;
 175                 inten = BONITO_INTEN;
 176                 intpol = BONITO_INTPOL;
 177                 intedge = BONITO_INTEDGE;
 178                 intsteer = BONITO_INTSTEER;
 179                 pcicmd = BONITO_PCICMD;
 180                 printk("BONITO_INTISR = %08x\n", intisr);
 181                 printk("BONITO_INTEN = %08x\n", inten);
 182                 printk("BONITO_INTPOL = %08x\n", intpol);
 183                 printk("BONITO_INTEDGE = %08x\n", intedge);
 184                 printk("BONITO_INTSTEER = %08x\n", intsteer);
 185                 printk("BONITO_PCICMD = %08x\n", pcicmd);
 186                 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 187                 printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
 188                 break;
 189         }
 190
 191         /* We die here*/
 192         die("CoreHi interrupt", regs);
 193 }
 194
 195 static struct irqaction i8259irq = {
 196         .handler = no_action,
 197         .name = "XT-PIC cascade"
 198 };
 199
 200 static struct irqaction corehi_irqaction = {
 201         .handler = no_action,
 202         .name = "CoreHi"
 203 };
 204
 205 msc_irqmap_t __initdata msc_irqmap[] = {
 206         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 207         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 208 };
 209 int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
 210
 211 msc_irqmap_t __initdata msc_eicirqmap[] = {
 212         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 213         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 214         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
 215         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
 216         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
 217         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
 218         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 219         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 220         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 221         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 222 };
 223 int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
 224
 225 void __init arch_init_irq(void)
 226 {
 227         set_except_vector(0, mipsIRQ);
 228         init_i8259_irqs();
 229
 230         if (!cpu_has_veic)
 231                 mips_cpu_irq_init (MIPSCPU_INT_BASE);
 232
 233         switch(mips_revision_corid) {
 234         case MIPS_REVISION_CORID_CORE_MSC:
 235         case MIPS_REVISION_CORID_CORE_FPGA2:
 236         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 237                 if (cpu_has_veic)
 238                         init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
 239                 else
 240                         init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
 241         }
 242
 243         if (cpu_has_veic) {
 244                 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
 245                 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
 246                 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
 247                 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
 248         }
 249         else if (cpu_has_vint) {
 250                 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
 251                 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
 252
 253                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 254                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 255         }
 256         else {
 257                 set_except_vector(0, mipsIRQ);
 258                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 259                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 260         }
 261 }