2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/preempt.h>
16 #include <linux/sched.h>
17 #include <linux/smp.h>
19 #include <linux/module.h>
20 #include <linux/bitops.h>
22 #include <asm/bcache.h>
23 #include <asm/bootinfo.h>
24 #include <asm/cache.h>
25 #include <asm/cacheops.h>
27 #include <asm/cpu-features.h>
28 #include <asm/cpu-type.h>
31 #include <asm/pgtable.h>
32 #include <asm/r4kcache.h>
33 #include <asm/sections.h>
34 #include <asm/mmu_context.h>
36 #include <asm/cacheflush.h> /* for run_uncached() */
37 #include <asm/traps.h>
38 #include <asm/dma-coherence.h>
41 * Special Variant of smp_call_function for use by cache functions:
44 * o collapses to normal function call on UP kernels
45 * o collapses to normal function call on systems with a single shared
47 * o doesn't disable interrupts on the local CPU
49 static inline void r4k_on_each_cpu(void (*func
) (void *info
), void *info
)
53 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
54 smp_call_function(func
, info
, 1);
60 #if defined(CONFIG_MIPS_CMP)
61 #define cpu_has_safe_index_cacheops 0
63 #define cpu_has_safe_index_cacheops 1
69 static unsigned long icache_size __read_mostly
;
70 static unsigned long dcache_size __read_mostly
;
71 static unsigned long scache_size __read_mostly
;
74 * Dummy cache handling routines for machines without boardcaches
76 static void cache_noop(void) {}
78 static struct bcache_ops no_sc_ops
= {
79 .bc_enable
= (void *)cache_noop
,
80 .bc_disable
= (void *)cache_noop
,
81 .bc_wback_inv
= (void *)cache_noop
,
82 .bc_inv
= (void *)cache_noop
85 struct bcache_ops
*bcops
= &no_sc_ops
;
87 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
88 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
90 #define R4600_HIT_CACHEOP_WAR_IMPL \
92 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
93 *(volatile unsigned long *)CKSEG1; \
94 if (R4600_V1_HIT_CACHEOP_WAR) \
95 __asm__ __volatile__("nop;nop;nop;nop"); \
98 static void (*r4k_blast_dcache_page
)(unsigned long addr
);
100 static inline void r4k_blast_dcache_page_dc32(unsigned long addr
)
102 R4600_HIT_CACHEOP_WAR_IMPL
;
103 blast_dcache32_page(addr
);
106 static inline void r4k_blast_dcache_page_dc64(unsigned long addr
)
108 R4600_HIT_CACHEOP_WAR_IMPL
;
109 blast_dcache64_page(addr
);
112 static void r4k_blast_dcache_page_setup(void)
114 unsigned long dc_lsize
= cpu_dcache_line_size();
117 r4k_blast_dcache_page
= (void *)cache_noop
;
118 else if (dc_lsize
== 16)
119 r4k_blast_dcache_page
= blast_dcache16_page
;
120 else if (dc_lsize
== 32)
121 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc32
;
122 else if (dc_lsize
== 64)
123 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc64
;
126 static void (* r4k_blast_dcache_page_indexed
)(unsigned long addr
);
128 static void r4k_blast_dcache_page_indexed_setup(void)
130 unsigned long dc_lsize
= cpu_dcache_line_size();
133 r4k_blast_dcache_page_indexed
= (void *)cache_noop
;
134 else if (dc_lsize
== 16)
135 r4k_blast_dcache_page_indexed
= blast_dcache16_page_indexed
;
136 else if (dc_lsize
== 32)
137 r4k_blast_dcache_page_indexed
= blast_dcache32_page_indexed
;
138 else if (dc_lsize
== 64)
139 r4k_blast_dcache_page_indexed
= blast_dcache64_page_indexed
;
142 void (* r4k_blast_dcache
)(void);
143 EXPORT_SYMBOL(r4k_blast_dcache
);
145 static void r4k_blast_dcache_setup(void)
147 unsigned long dc_lsize
= cpu_dcache_line_size();
150 r4k_blast_dcache
= (void *)cache_noop
;
151 else if (dc_lsize
== 16)
152 r4k_blast_dcache
= blast_dcache16
;
153 else if (dc_lsize
== 32)
154 r4k_blast_dcache
= blast_dcache32
;
155 else if (dc_lsize
== 64)
156 r4k_blast_dcache
= blast_dcache64
;
159 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
160 #define JUMP_TO_ALIGN(order) \
161 __asm__ __volatile__( \
163 ".align\t" #order "\n\t" \
166 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
167 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
169 static inline void blast_r4600_v1_icache32(void)
173 local_irq_save(flags
);
175 local_irq_restore(flags
);
178 static inline void tx49_blast_icache32(void)
180 unsigned long start
= INDEX_BASE
;
181 unsigned long end
= start
+ current_cpu_data
.icache
.waysize
;
182 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
183 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
184 current_cpu_data
.icache
.waybit
;
185 unsigned long ws
, addr
;
187 CACHE32_UNROLL32_ALIGN2
;
188 /* I'm in even chunk. blast odd chunks */
189 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
190 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
191 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
192 CACHE32_UNROLL32_ALIGN
;
193 /* I'm in odd chunk. blast even chunks */
194 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
195 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
196 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
199 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page
)
203 local_irq_save(flags
);
204 blast_icache32_page_indexed(page
);
205 local_irq_restore(flags
);
208 static inline void tx49_blast_icache32_page_indexed(unsigned long page
)
210 unsigned long indexmask
= current_cpu_data
.icache
.waysize
- 1;
211 unsigned long start
= INDEX_BASE
+ (page
& indexmask
);
212 unsigned long end
= start
+ PAGE_SIZE
;
213 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
214 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
215 current_cpu_data
.icache
.waybit
;
216 unsigned long ws
, addr
;
218 CACHE32_UNROLL32_ALIGN2
;
219 /* I'm in even chunk. blast odd chunks */
220 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
221 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
222 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
223 CACHE32_UNROLL32_ALIGN
;
224 /* I'm in odd chunk. blast even chunks */
225 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
226 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
227 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
230 static void (* r4k_blast_icache_page
)(unsigned long addr
);
232 static void r4k_blast_icache_page_setup(void)
234 unsigned long ic_lsize
= cpu_icache_line_size();
237 r4k_blast_icache_page
= (void *)cache_noop
;
238 else if (ic_lsize
== 16)
239 r4k_blast_icache_page
= blast_icache16_page
;
240 else if (ic_lsize
== 32)
241 r4k_blast_icache_page
= blast_icache32_page
;
242 else if (ic_lsize
== 64)
243 r4k_blast_icache_page
= blast_icache64_page
;
247 static void (* r4k_blast_icache_page_indexed
)(unsigned long addr
);
249 static void r4k_blast_icache_page_indexed_setup(void)
251 unsigned long ic_lsize
= cpu_icache_line_size();
254 r4k_blast_icache_page_indexed
= (void *)cache_noop
;
255 else if (ic_lsize
== 16)
256 r4k_blast_icache_page_indexed
= blast_icache16_page_indexed
;
257 else if (ic_lsize
== 32) {
258 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
259 r4k_blast_icache_page_indexed
=
260 blast_icache32_r4600_v1_page_indexed
;
261 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
262 r4k_blast_icache_page_indexed
=
263 tx49_blast_icache32_page_indexed
;
265 r4k_blast_icache_page_indexed
=
266 blast_icache32_page_indexed
;
267 } else if (ic_lsize
== 64)
268 r4k_blast_icache_page_indexed
= blast_icache64_page_indexed
;
271 void (* r4k_blast_icache
)(void);
272 EXPORT_SYMBOL(r4k_blast_icache
);
274 static void r4k_blast_icache_setup(void)
276 unsigned long ic_lsize
= cpu_icache_line_size();
279 r4k_blast_icache
= (void *)cache_noop
;
280 else if (ic_lsize
== 16)
281 r4k_blast_icache
= blast_icache16
;
282 else if (ic_lsize
== 32) {
283 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
284 r4k_blast_icache
= blast_r4600_v1_icache32
;
285 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
286 r4k_blast_icache
= tx49_blast_icache32
;
288 r4k_blast_icache
= blast_icache32
;
289 } else if (ic_lsize
== 64)
290 r4k_blast_icache
= blast_icache64
;
293 static void (* r4k_blast_scache_page
)(unsigned long addr
);
295 static void r4k_blast_scache_page_setup(void)
297 unsigned long sc_lsize
= cpu_scache_line_size();
299 if (scache_size
== 0)
300 r4k_blast_scache_page
= (void *)cache_noop
;
301 else if (sc_lsize
== 16)
302 r4k_blast_scache_page
= blast_scache16_page
;
303 else if (sc_lsize
== 32)
304 r4k_blast_scache_page
= blast_scache32_page
;
305 else if (sc_lsize
== 64)
306 r4k_blast_scache_page
= blast_scache64_page
;
307 else if (sc_lsize
== 128)
308 r4k_blast_scache_page
= blast_scache128_page
;
311 static void (* r4k_blast_scache_page_indexed
)(unsigned long addr
);
313 static void r4k_blast_scache_page_indexed_setup(void)
315 unsigned long sc_lsize
= cpu_scache_line_size();
317 if (scache_size
== 0)
318 r4k_blast_scache_page_indexed
= (void *)cache_noop
;
319 else if (sc_lsize
== 16)
320 r4k_blast_scache_page_indexed
= blast_scache16_page_indexed
;
321 else if (sc_lsize
== 32)
322 r4k_blast_scache_page_indexed
= blast_scache32_page_indexed
;
323 else if (sc_lsize
== 64)
324 r4k_blast_scache_page_indexed
= blast_scache64_page_indexed
;
325 else if (sc_lsize
== 128)
326 r4k_blast_scache_page_indexed
= blast_scache128_page_indexed
;
329 static void (* r4k_blast_scache
)(void);
331 static void r4k_blast_scache_setup(void)
333 unsigned long sc_lsize
= cpu_scache_line_size();
335 if (scache_size
== 0)
336 r4k_blast_scache
= (void *)cache_noop
;
337 else if (sc_lsize
== 16)
338 r4k_blast_scache
= blast_scache16
;
339 else if (sc_lsize
== 32)
340 r4k_blast_scache
= blast_scache32
;
341 else if (sc_lsize
== 64)
342 r4k_blast_scache
= blast_scache64
;
343 else if (sc_lsize
== 128)
344 r4k_blast_scache
= blast_scache128
;
347 static inline void local_r4k___flush_cache_all(void * args
)
349 switch (current_cpu_type()) {
359 * These caches are inclusive caches, that is, if something
360 * is not cached in the S-cache, we know it also won't be
361 * in one of the primary caches.
373 static void r4k___flush_cache_all(void)
375 r4k_on_each_cpu(local_r4k___flush_cache_all
, NULL
);
378 static inline int has_valid_asid(const struct mm_struct
*mm
)
380 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
383 for_each_online_cpu(i
)
384 if (cpu_context(i
, mm
))
389 return cpu_context(smp_processor_id(), mm
);
393 static void r4k__flush_cache_vmap(void)
398 static void r4k__flush_cache_vunmap(void)
403 static inline void local_r4k_flush_cache_range(void * args
)
405 struct vm_area_struct
*vma
= args
;
406 int exec
= vma
->vm_flags
& VM_EXEC
;
408 if (!(has_valid_asid(vma
->vm_mm
)))
416 static void r4k_flush_cache_range(struct vm_area_struct
*vma
,
417 unsigned long start
, unsigned long end
)
419 int exec
= vma
->vm_flags
& VM_EXEC
;
421 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
))
422 r4k_on_each_cpu(local_r4k_flush_cache_range
, vma
);
425 static inline void local_r4k_flush_cache_mm(void * args
)
427 struct mm_struct
*mm
= args
;
429 if (!has_valid_asid(mm
))
433 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
434 * only flush the primary caches but R10000 and R12000 behave sane ...
435 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
436 * caches, so we can bail out early.
438 if (current_cpu_type() == CPU_R4000SC
||
439 current_cpu_type() == CPU_R4000MC
||
440 current_cpu_type() == CPU_R4400SC
||
441 current_cpu_type() == CPU_R4400MC
) {
449 static void r4k_flush_cache_mm(struct mm_struct
*mm
)
451 if (!cpu_has_dc_aliases
)
454 r4k_on_each_cpu(local_r4k_flush_cache_mm
, mm
);
457 struct flush_cache_page_args
{
458 struct vm_area_struct
*vma
;
463 static inline void local_r4k_flush_cache_page(void *args
)
465 struct flush_cache_page_args
*fcp_args
= args
;
466 struct vm_area_struct
*vma
= fcp_args
->vma
;
467 unsigned long addr
= fcp_args
->addr
;
468 struct page
*page
= pfn_to_page(fcp_args
->pfn
);
469 int exec
= vma
->vm_flags
& VM_EXEC
;
470 struct mm_struct
*mm
= vma
->vm_mm
;
471 int map_coherent
= 0;
479 * If ownes no valid ASID yet, cannot possibly have gotten
480 * this page into the cache.
482 if (!has_valid_asid(mm
))
486 pgdp
= pgd_offset(mm
, addr
);
487 pudp
= pud_offset(pgdp
, addr
);
488 pmdp
= pmd_offset(pudp
, addr
);
489 ptep
= pte_offset(pmdp
, addr
);
492 * If the page isn't marked valid, the page cannot possibly be
495 if (!(pte_present(*ptep
)))
498 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
))
502 * Use kmap_coherent or kmap_atomic to do flushes for
503 * another ASID than the current one.
505 map_coherent
= (cpu_has_dc_aliases
&&
506 page_mapped(page
) && !Page_dcache_dirty(page
));
508 vaddr
= kmap_coherent(page
, addr
);
510 vaddr
= kmap_atomic(page
);
511 addr
= (unsigned long)vaddr
;
514 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
515 r4k_blast_dcache_page(addr
);
516 if (exec
&& !cpu_icache_snoops_remote_store
)
517 r4k_blast_scache_page(addr
);
520 if (vaddr
&& cpu_has_vtag_icache
&& mm
== current
->active_mm
) {
521 int cpu
= smp_processor_id();
523 if (cpu_context(cpu
, mm
) != 0)
524 drop_mmu_context(mm
, cpu
);
526 r4k_blast_icache_page(addr
);
533 kunmap_atomic(vaddr
);
537 static void r4k_flush_cache_page(struct vm_area_struct
*vma
,
538 unsigned long addr
, unsigned long pfn
)
540 struct flush_cache_page_args args
;
546 r4k_on_each_cpu(local_r4k_flush_cache_page
, &args
);
549 static inline void local_r4k_flush_data_cache_page(void * addr
)
551 r4k_blast_dcache_page((unsigned long) addr
);
554 static void r4k_flush_data_cache_page(unsigned long addr
)
557 local_r4k_flush_data_cache_page((void *)addr
);
559 r4k_on_each_cpu(local_r4k_flush_data_cache_page
, (void *) addr
);
562 struct flush_icache_range_args
{
567 static inline void local_r4k_flush_icache_range(unsigned long start
, unsigned long end
)
569 if (!cpu_has_ic_fills_f_dc
) {
570 if (end
- start
>= dcache_size
) {
573 R4600_HIT_CACHEOP_WAR_IMPL
;
574 protected_blast_dcache_range(start
, end
);
578 if (end
- start
> icache_size
)
581 switch (boot_cpu_type()) {
583 protected_blast_icache_range(start
, end
);
587 protected_loongson23_blast_icache_range(start
, end
);
593 static inline void local_r4k_flush_icache_range_ipi(void *args
)
595 struct flush_icache_range_args
*fir_args
= args
;
596 unsigned long start
= fir_args
->start
;
597 unsigned long end
= fir_args
->end
;
599 local_r4k_flush_icache_range(start
, end
);
602 static void r4k_flush_icache_range(unsigned long start
, unsigned long end
)
604 struct flush_icache_range_args args
;
609 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi
, &args
);
610 instruction_hazard();
613 #ifdef CONFIG_DMA_NONCOHERENT
615 static void r4k_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
617 /* Catch bad driver code */
621 if (cpu_has_inclusive_pcaches
) {
622 if (size
>= scache_size
)
625 blast_scache_range(addr
, addr
+ size
);
632 * Either no secondary cache or the available caches don't have the
633 * subset property so we have to flush the primary caches
636 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
) {
639 R4600_HIT_CACHEOP_WAR_IMPL
;
640 blast_dcache_range(addr
, addr
+ size
);
644 bc_wback_inv(addr
, size
);
648 static void r4k_dma_cache_inv(unsigned long addr
, unsigned long size
)
650 /* Catch bad driver code */
654 if (cpu_has_inclusive_pcaches
) {
655 if (size
>= scache_size
)
659 * There is no clearly documented alignment requirement
660 * for the cache instruction on MIPS processors and
661 * some processors, among them the RM5200 and RM7000
662 * QED processors will throw an address error for cache
663 * hit ops with insufficient alignment. Solved by
664 * aligning the address to cache line size.
666 blast_inv_scache_range(addr
, addr
+ size
);
673 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
) {
676 R4600_HIT_CACHEOP_WAR_IMPL
;
677 blast_inv_dcache_range(addr
, addr
+ size
);
684 #endif /* CONFIG_DMA_NONCOHERENT */
687 * While we're protected against bad userland addresses we don't care
688 * very much about what happens in that case. Usually a segmentation
689 * fault will dump the process later on anyway ...
691 static void local_r4k_flush_cache_sigtramp(void * arg
)
693 unsigned long ic_lsize
= cpu_icache_line_size();
694 unsigned long dc_lsize
= cpu_dcache_line_size();
695 unsigned long sc_lsize
= cpu_scache_line_size();
696 unsigned long addr
= (unsigned long) arg
;
698 R4600_HIT_CACHEOP_WAR_IMPL
;
700 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
701 if (!cpu_icache_snoops_remote_store
&& scache_size
)
702 protected_writeback_scache_line(addr
& ~(sc_lsize
- 1));
704 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
705 if (MIPS4K_ICACHE_REFILL_WAR
) {
706 __asm__
__volatile__ (
721 : "i" (Hit_Invalidate_I
));
723 if (MIPS_CACHE_SYNC_WAR
)
724 __asm__
__volatile__ ("sync");
727 static void r4k_flush_cache_sigtramp(unsigned long addr
)
729 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp
, (void *) addr
);
732 static void r4k_flush_icache_all(void)
734 if (cpu_has_vtag_icache
)
738 struct flush_kernel_vmap_range_args
{
743 static inline void local_r4k_flush_kernel_vmap_range(void *args
)
745 struct flush_kernel_vmap_range_args
*vmra
= args
;
746 unsigned long vaddr
= vmra
->vaddr
;
747 int size
= vmra
->size
;
750 * Aliases only affect the primary caches so don't bother with
751 * S-caches or T-caches.
753 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
)
756 R4600_HIT_CACHEOP_WAR_IMPL
;
757 blast_dcache_range(vaddr
, vaddr
+ size
);
761 static void r4k_flush_kernel_vmap_range(unsigned long vaddr
, int size
)
763 struct flush_kernel_vmap_range_args args
;
765 args
.vaddr
= (unsigned long) vaddr
;
768 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range
, &args
);
771 static inline void rm7k_erratum31(void)
773 const unsigned long ic_lsize
= 32;
776 /* RM7000 erratum #31. The icache is screwed at startup. */
780 for (addr
= INDEX_BASE
; addr
<= INDEX_BASE
+ 4096; addr
+= ic_lsize
) {
781 __asm__
__volatile__ (
785 "cache\t%1, 0(%0)\n\t"
786 "cache\t%1, 0x1000(%0)\n\t"
787 "cache\t%1, 0x2000(%0)\n\t"
788 "cache\t%1, 0x3000(%0)\n\t"
789 "cache\t%2, 0(%0)\n\t"
790 "cache\t%2, 0x1000(%0)\n\t"
791 "cache\t%2, 0x2000(%0)\n\t"
792 "cache\t%2, 0x3000(%0)\n\t"
793 "cache\t%1, 0(%0)\n\t"
794 "cache\t%1, 0x1000(%0)\n\t"
795 "cache\t%1, 0x2000(%0)\n\t"
796 "cache\t%1, 0x3000(%0)\n\t"
799 : "r" (addr
), "i" (Index_Store_Tag_I
), "i" (Fill
));
803 static inline void alias_74k_erratum(struct cpuinfo_mips
*c
)
805 unsigned int imp
= c
->processor_id
& PRID_IMP_MASK
;
806 unsigned int rev
= c
->processor_id
& PRID_REV_MASK
;
809 * Early versions of the 74K do not update the cache tags on a
810 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
811 * aliases. In this case it is better to treat the cache as always
816 if (rev
<= PRID_REV_ENCODE_332(2, 4, 0))
817 c
->dcache
.flags
|= MIPS_CACHE_VTAG
;
818 if (rev
== PRID_REV_ENCODE_332(2, 4, 0))
819 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND
);
822 if (rev
<= PRID_REV_ENCODE_332(1, 1, 0)) {
823 c
->dcache
.flags
|= MIPS_CACHE_VTAG
;
824 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND
);
832 static char *way_string
[] = { NULL
, "direct mapped", "2-way",
833 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
836 static void probe_pcache(void)
838 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
839 unsigned int config
= read_c0_config();
840 unsigned int prid
= read_c0_prid();
841 unsigned long config1
;
844 switch (current_cpu_type()) {
845 case CPU_R4600
: /* QED style two way caches? */
849 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
850 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
852 c
->icache
.waybit
= __ffs(icache_size
/2);
854 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
855 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
857 c
->dcache
.waybit
= __ffs(dcache_size
/2);
859 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
864 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
865 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
869 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
870 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
872 c
->dcache
.waybit
= 0;
874 c
->options
|= MIPS_CPU_CACHE_CDEX_P
| MIPS_CPU_PREFETCH
;
878 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
879 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
883 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
884 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
886 c
->dcache
.waybit
= 0;
888 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
889 c
->options
|= MIPS_CPU_PREFETCH
;
899 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
900 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
902 c
->icache
.waybit
= 0; /* doesn't matter */
904 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
905 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
907 c
->dcache
.waybit
= 0; /* does not matter */
909 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
915 icache_size
= 1 << (12 + ((config
& R10K_CONF_IC
) >> 29));
916 c
->icache
.linesz
= 64;
918 c
->icache
.waybit
= 0;
920 dcache_size
= 1 << (12 + ((config
& R10K_CONF_DC
) >> 26));
921 c
->dcache
.linesz
= 32;
923 c
->dcache
.waybit
= 0;
925 c
->options
|= MIPS_CPU_PREFETCH
;
929 write_c0_config(config
& ~VR41_CONF_P4K
);
931 /* Workaround for cache instruction bug of VR4131 */
932 if (c
->processor_id
== 0x0c80U
|| c
->processor_id
== 0x0c81U
||
933 c
->processor_id
== 0x0c82U
) {
934 config
|= 0x00400000U
;
935 if (c
->processor_id
== 0x0c80U
)
936 config
|= VR41_CONF_BP
;
937 write_c0_config(config
);
939 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
941 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
942 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
944 c
->icache
.waybit
= __ffs(icache_size
/2);
946 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
947 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
949 c
->dcache
.waybit
= __ffs(dcache_size
/2);
958 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
959 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
961 c
->icache
.waybit
= 0; /* doesn't matter */
963 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
964 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
966 c
->dcache
.waybit
= 0; /* does not matter */
968 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
974 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
975 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
977 c
->icache
.waybit
= __ffs(icache_size
/ c
->icache
.ways
);
979 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
980 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
982 c
->dcache
.waybit
= __ffs(dcache_size
/ c
->dcache
.ways
);
984 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
985 c
->options
|= MIPS_CPU_PREFETCH
;
989 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
990 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
995 c
->icache
.waybit
= 0;
997 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
998 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
1003 c
->dcache
.waybit
= 0;
1007 if (!(config
& MIPS_CONF_M
))
1008 panic("Don't know how to probe P-caches on this cpu.");
1011 * So we seem to be a MIPS32 or MIPS64 CPU
1012 * So let's probe the I-cache ...
1014 config1
= read_c0_config1();
1016 if ((lsize
= ((config1
>> 19) & 7)))
1017 c
->icache
.linesz
= 2 << lsize
;
1019 c
->icache
.linesz
= lsize
;
1020 c
->icache
.sets
= 32 << (((config1
>> 22) + 1) & 7);
1021 c
->icache
.ways
= 1 + ((config1
>> 16) & 7);
1023 icache_size
= c
->icache
.sets
*
1026 c
->icache
.waybit
= __ffs(icache_size
/c
->icache
.ways
);
1028 if (config
& 0x8) /* VI bit */
1029 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
1032 * Now probe the MIPS32 / MIPS64 data cache.
1034 c
->dcache
.flags
= 0;
1036 if ((lsize
= ((config1
>> 10) & 7)))
1037 c
->dcache
.linesz
= 2 << lsize
;
1039 c
->dcache
.linesz
= lsize
;
1040 c
->dcache
.sets
= 32 << (((config1
>> 13) + 1) & 7);
1041 c
->dcache
.ways
= 1 + ((config1
>> 7) & 7);
1043 dcache_size
= c
->dcache
.sets
*
1046 c
->dcache
.waybit
= __ffs(dcache_size
/c
->dcache
.ways
);
1048 c
->options
|= MIPS_CPU_PREFETCH
;
1053 * Processor configuration sanity check for the R4000SC erratum
1054 * #5. With page sizes larger than 32kB there is no possibility
1055 * to get a VCE exception anymore so we don't care about this
1056 * misconfiguration. The case is rather theoretical anyway;
1057 * presumably no vendor is shipping his hardware in the "bad"
1060 if ((prid
& PRID_IMP_MASK
) == PRID_IMP_R4000
&&
1061 (prid
& PRID_REV_MASK
) < PRID_REV_R4400
&&
1062 !(config
& CONF_SC
) && c
->icache
.linesz
!= 16 &&
1063 PAGE_SIZE
<= 0x8000)
1064 panic("Improper R4000SC processor configuration detected");
1066 /* compute a couple of other cache variables */
1067 c
->icache
.waysize
= icache_size
/ c
->icache
.ways
;
1068 c
->dcache
.waysize
= dcache_size
/ c
->dcache
.ways
;
1070 c
->icache
.sets
= c
->icache
.linesz
?
1071 icache_size
/ (c
->icache
.linesz
* c
->icache
.ways
) : 0;
1072 c
->dcache
.sets
= c
->dcache
.linesz
?
1073 dcache_size
/ (c
->dcache
.linesz
* c
->dcache
.ways
) : 0;
1076 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1077 * 2-way virtually indexed so normally would suffer from aliases. So
1078 * normally they'd suffer from aliases but magic in the hardware deals
1079 * with that for us so we don't need to take care ourselves.
1081 switch (current_cpu_type()) {
1087 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
1101 if (current_cpu_type() == CPU_74K
)
1102 alias_74k_erratum(c
);
1103 if ((read_c0_config7() & (1 << 16))) {
1104 /* effectively physically indexed dcache,
1105 thus no virtual aliases. */
1106 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
1110 if (c
->dcache
.waysize
> PAGE_SIZE
)
1111 c
->dcache
.flags
|= MIPS_CACHE_ALIASES
;
1114 switch (current_cpu_type()) {
1117 * Some older 20Kc chips doesn't have the 'VI' bit in
1118 * the config register.
1120 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
1124 c
->icache
.flags
|= MIPS_CACHE_IC_F_DC
;
1129 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1130 * one op will act on all 4 ways
1135 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1137 c
->icache
.flags
& MIPS_CACHE_VTAG
? "VIVT" : "VIPT",
1138 way_string
[c
->icache
.ways
], c
->icache
.linesz
);
1140 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1141 dcache_size
>> 10, way_string
[c
->dcache
.ways
],
1142 (c
->dcache
.flags
& MIPS_CACHE_PINDEX
) ? "PIPT" : "VIPT",
1143 (c
->dcache
.flags
& MIPS_CACHE_ALIASES
) ?
1144 "cache aliases" : "no aliases",
1149 * If you even _breathe_ on this function, look at the gcc output and make sure
1150 * it does not pop things on and off the stack for the cache sizing loop that
1151 * executes in KSEG1 space or else you will crash and burn badly. You have
1154 static int probe_scache(void)
1156 unsigned long flags
, addr
, begin
, end
, pow2
;
1157 unsigned int config
= read_c0_config();
1158 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1160 if (config
& CONF_SC
)
1163 begin
= (unsigned long) &_stext
;
1164 begin
&= ~((4 * 1024 * 1024) - 1);
1165 end
= begin
+ (4 * 1024 * 1024);
1168 * This is such a bitch, you'd think they would make it easy to do
1169 * this. Away you daemons of stupidity!
1171 local_irq_save(flags
);
1173 /* Fill each size-multiple cache line with a valid tag. */
1175 for (addr
= begin
; addr
< end
; addr
= (begin
+ pow2
)) {
1176 unsigned long *p
= (unsigned long *) addr
;
1177 __asm__
__volatile__("nop" : : "r" (*p
)); /* whee... */
1181 /* Load first line with zero (therefore invalid) tag. */
1184 __asm__
__volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1185 cache_op(Index_Store_Tag_I
, begin
);
1186 cache_op(Index_Store_Tag_D
, begin
);
1187 cache_op(Index_Store_Tag_SD
, begin
);
1189 /* Now search for the wrap around point. */
1190 pow2
= (128 * 1024);
1191 for (addr
= begin
+ (128 * 1024); addr
< end
; addr
= begin
+ pow2
) {
1192 cache_op(Index_Load_Tag_SD
, addr
);
1193 __asm__
__volatile__("nop; nop; nop; nop;"); /* hazard... */
1194 if (!read_c0_taglo())
1198 local_irq_restore(flags
);
1202 c
->scache
.linesz
= 16 << ((config
& R4K_CONF_SB
) >> 22);
1204 c
->dcache
.waybit
= 0; /* does not matter */
1209 static void __init
loongson2_sc_init(void)
1211 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1213 scache_size
= 512*1024;
1214 c
->scache
.linesz
= 32;
1216 c
->scache
.waybit
= 0;
1217 c
->scache
.waysize
= scache_size
/ (c
->scache
.ways
);
1218 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1219 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1220 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1222 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1225 extern int r5k_sc_init(void);
1226 extern int rm7k_sc_init(void);
1227 extern int mips_sc_init(void);
1229 static void setup_scache(void)
1231 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1232 unsigned int config
= read_c0_config();
1236 * Do the probing thing on R4000SC and R4400SC processors. Other
1237 * processors don't have a S-cache that would be relevant to the
1238 * Linux memory management.
1240 switch (current_cpu_type()) {
1245 sc_present
= run_uncached(probe_scache
);
1247 c
->options
|= MIPS_CPU_CACHE_CDEX_S
;
1253 scache_size
= 0x80000 << ((config
& R10K_CONF_SS
) >> 16);
1254 c
->scache
.linesz
= 64 << ((config
>> 13) & 1);
1256 c
->scache
.waybit
= 0;
1262 #ifdef CONFIG_R5000_CPU_SCACHE
1268 #ifdef CONFIG_RM7000_CPU_SCACHE
1274 loongson2_sc_init();
1278 /* don't need to worry about L2, fully coherent */
1282 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M32R2
|
1283 MIPS_CPU_ISA_M64R1
| MIPS_CPU_ISA_M64R2
)) {
1284 #ifdef CONFIG_MIPS_CPU_SCACHE
1285 if (mips_sc_init ()) {
1286 scache_size
= c
->scache
.ways
* c
->scache
.sets
* c
->scache
.linesz
;
1287 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1289 way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1292 if (!(c
->scache
.flags
& MIPS_CACHE_NOT_PRESENT
))
1293 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1303 /* compute a couple of other cache variables */
1304 c
->scache
.waysize
= scache_size
/ c
->scache
.ways
;
1306 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1308 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1309 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1311 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1314 void au1x00_fixup_config_od(void)
1317 * c0_config.od (bit 19) was write only (and read as 0)
1318 * on the early revisions of Alchemy SOCs. It disables the bus
1319 * transaction overlapping and needs to be set to fix various errata.
1321 switch (read_c0_prid()) {
1322 case 0x00030100: /* Au1000 DA */
1323 case 0x00030201: /* Au1000 HA */
1324 case 0x00030202: /* Au1000 HB */
1325 case 0x01030200: /* Au1500 AB */
1327 * Au1100 errata actually keeps silence about this bit, so we set it
1328 * just in case for those revisions that require it to be set according
1329 * to the (now gone) cpu table.
1331 case 0x02030200: /* Au1100 AB */
1332 case 0x02030201: /* Au1100 BA */
1333 case 0x02030202: /* Au1100 BC */
1334 set_c0_config(1 << 19);
1339 /* CP0 hazard avoidance. */
1340 #define NXP_BARRIER() \
1341 __asm__ __volatile__( \
1342 ".set noreorder\n\t" \
1343 "nop; nop; nop; nop; nop; nop;\n\t" \
1346 static void nxp_pr4450_fixup_config(void)
1348 unsigned long config0
;
1350 config0
= read_c0_config();
1352 /* clear all three cache coherency fields */
1353 config0
&= ~(0x7 | (7 << 25) | (7 << 28));
1354 config0
|= (((_page_cachable_default
>> _CACHE_SHIFT
) << 0) |
1355 ((_page_cachable_default
>> _CACHE_SHIFT
) << 25) |
1356 ((_page_cachable_default
>> _CACHE_SHIFT
) << 28));
1357 write_c0_config(config0
);
1361 static int cca
= -1;
1363 static int __init
cca_setup(char *str
)
1365 get_option(&str
, &cca
);
1370 early_param("cca", cca_setup
);
1372 static void coherency_setup(void)
1374 if (cca
< 0 || cca
> 7)
1375 cca
= read_c0_config() & CONF_CM_CMASK
;
1376 _page_cachable_default
= cca
<< _CACHE_SHIFT
;
1378 pr_debug("Using cache attribute %d\n", cca
);
1379 change_c0_config(CONF_CM_CMASK
, cca
);
1382 * c0_status.cu=0 specifies that updates by the sc instruction use
1383 * the coherency mode specified by the TLB; 1 means cachable
1384 * coherent update on write will be used. Not all processors have
1385 * this bit and; some wire it to zero, others like Toshiba had the
1386 * silly idea of putting something else there ...
1388 switch (current_cpu_type()) {
1395 clear_c0_config(CONF_CU
);
1398 * We need to catch the early Alchemy SOCs with
1399 * the write-only co_config.od bit and set it back to one on:
1400 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1403 au1x00_fixup_config_od();
1406 case PRID_IMP_PR4450
:
1407 nxp_pr4450_fixup_config();
1412 static void r4k_cache_error_setup(void)
1414 extern char __weak except_vec2_generic
;
1415 extern char __weak except_vec2_sb1
;
1417 switch (current_cpu_type()) {
1420 set_uncached_handler(0x100, &except_vec2_sb1
, 0x80);
1424 set_uncached_handler(0x100, &except_vec2_generic
, 0x80);
1429 void r4k_cache_init(void)
1431 extern void build_clear_page(void);
1432 extern void build_copy_page(void);
1433 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1438 r4k_blast_dcache_page_setup();
1439 r4k_blast_dcache_page_indexed_setup();
1440 r4k_blast_dcache_setup();
1441 r4k_blast_icache_page_setup();
1442 r4k_blast_icache_page_indexed_setup();
1443 r4k_blast_icache_setup();
1444 r4k_blast_scache_page_setup();
1445 r4k_blast_scache_page_indexed_setup();
1446 r4k_blast_scache_setup();
1449 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1450 * This code supports virtually indexed processors and will be
1451 * unnecessarily inefficient on physically indexed processors.
1453 if (c
->dcache
.linesz
)
1454 shm_align_mask
= max_t( unsigned long,
1455 c
->dcache
.sets
* c
->dcache
.linesz
- 1,
1458 shm_align_mask
= PAGE_SIZE
-1;
1460 __flush_cache_vmap
= r4k__flush_cache_vmap
;
1461 __flush_cache_vunmap
= r4k__flush_cache_vunmap
;
1463 flush_cache_all
= cache_noop
;
1464 __flush_cache_all
= r4k___flush_cache_all
;
1465 flush_cache_mm
= r4k_flush_cache_mm
;
1466 flush_cache_page
= r4k_flush_cache_page
;
1467 flush_cache_range
= r4k_flush_cache_range
;
1469 __flush_kernel_vmap_range
= r4k_flush_kernel_vmap_range
;
1471 flush_cache_sigtramp
= r4k_flush_cache_sigtramp
;
1472 flush_icache_all
= r4k_flush_icache_all
;
1473 local_flush_data_cache_page
= local_r4k_flush_data_cache_page
;
1474 flush_data_cache_page
= r4k_flush_data_cache_page
;
1475 flush_icache_range
= r4k_flush_icache_range
;
1476 local_flush_icache_range
= local_r4k_flush_icache_range
;
1478 #if defined(CONFIG_DMA_NONCOHERENT)
1480 _dma_cache_wback_inv
= (void *)cache_noop
;
1481 _dma_cache_wback
= (void *)cache_noop
;
1482 _dma_cache_inv
= (void *)cache_noop
;
1484 _dma_cache_wback_inv
= r4k_dma_cache_wback_inv
;
1485 _dma_cache_wback
= r4k_dma_cache_wback_inv
;
1486 _dma_cache_inv
= r4k_dma_cache_inv
;
1494 * We want to run CMP kernels on core with and without coherent
1495 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1496 * or not to flush caches.
1498 local_r4k___flush_cache_all(NULL
);
1501 board_cache_error_setup
= r4k_cache_error_setup
;