2 * sc-rm7k.c: RM7000 cache management functions.
4 * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
9 #include <linux/init.h>
10 #include <linux/kernel.h>
13 #include <asm/addrspace.h>
14 #include <asm/bcache.h>
15 #include <asm/cacheops.h>
16 #include <asm/mipsregs.h>
17 #include <asm/processor.h>
18 #include <asm/cacheflush.h> /* for run_uncached() */
20 /* Primary cache parameters. */
22 #define tc_pagesize (32*128)
24 /* Secondary cache parameters. */
25 #define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
27 extern unsigned long icache_way_size
, dcache_way_size
;
29 #include <asm/r4kcache.h>
31 int rm7k_tcache_enabled
;
34 * Writeback and invalidate the primary cache dcache before DMA.
35 * (XXX These need to be fixed ...)
37 static void rm7k_sc_wback_inv(unsigned long addr
, unsigned long size
)
41 pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr
, size
);
43 /* Catch bad driver code */
46 a
= addr
& ~(sc_lsize
- 1);
47 end
= (addr
+ size
- 1) & ~(sc_lsize
- 1);
49 flush_scache_line(a
); /* Hit_Writeback_Inv_SD */
55 if (!rm7k_tcache_enabled
)
58 a
= addr
& ~(tc_pagesize
- 1);
59 end
= (addr
+ size
- 1) & ~(tc_pagesize
- 1);
61 invalidate_tcache_page(a
); /* Page_Invalidate_T */
68 static void rm7k_sc_inv(unsigned long addr
, unsigned long size
)
72 pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr
, size
);
74 /* Catch bad driver code */
77 a
= addr
& ~(sc_lsize
- 1);
78 end
= (addr
+ size
- 1) & ~(sc_lsize
- 1);
80 invalidate_scache_line(a
); /* Hit_Invalidate_SD */
86 if (!rm7k_tcache_enabled
)
89 a
= addr
& ~(tc_pagesize
- 1);
90 end
= (addr
+ size
- 1) & ~(tc_pagesize
- 1);
92 invalidate_tcache_page(a
); /* Page_Invalidate_T */
100 * This function is executed in uncached address space.
102 static __init
void __rm7k_sc_enable(void)
106 set_c0_config(RM7K_CONF_SE
);
111 for (i
= 0; i
< scache_size
; i
+= sc_lsize
) {
112 __asm__
__volatile__ (
119 : "r" (CKSEG0ADDR(i
)), "i" (Index_Store_Tag_SD
));
123 static __init
void rm7k_sc_enable(void)
125 if (read_c0_config() & RM7K_CONF_SE
)
128 printk(KERN_INFO
"Enabling secondary cache...\n");
129 run_uncached(__rm7k_sc_enable
);
132 static void rm7k_sc_disable(void)
134 clear_c0_config(RM7K_CONF_SE
);
137 struct bcache_ops rm7k_sc_ops
= {
138 .bc_enable
= rm7k_sc_enable
,
139 .bc_disable
= rm7k_sc_disable
,
140 .bc_wback_inv
= rm7k_sc_wback_inv
,
141 .bc_inv
= rm7k_sc_inv
144 void __init
rm7k_sc_init(void)
146 unsigned int config
= read_c0_config();
148 if ((config
& RM7K_CONF_SC
))
151 printk(KERN_INFO
"Secondary cache size %dK, linesize %d bytes.\n",
152 (scache_size
>> 10), sc_lsize
);
154 if (!(config
& RM7K_CONF_SE
))
158 * While we're at it let's deal with the tertiary cache.
160 if (!(config
& RM7K_CONF_TC
)) {
163 * We can't enable the L3 cache yet. There may be board-specific
164 * magic necessary to turn it on, and blindly asking the CPU to
165 * start using it would may give cache errors.
167 * Also, board-specific knowledge may allow us to use the
168 * CACHE Flash_Invalidate_T instruction if the tag RAM supports
169 * it, and may specify the size of the L3 cache so we don't have
172 printk(KERN_INFO
"Tertiary cache present, %s enabled\n",
173 (config
& RM7K_CONF_TE
) ? "already" : "not (yet)");
175 if ((config
& RM7K_CONF_TE
))
176 rm7k_tcache_enabled
= 1;
179 bcops
= &rm7k_sc_ops
;
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