2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
15 #include <linux/hugetlb.h>
16 #include <linux/module.h>
19 #include <asm/cpu-type.h>
20 #include <asm/bootinfo.h>
21 #include <asm/mmu_context.h>
22 #include <asm/pgtable.h>
23 #include <asm/tlbmisc.h>
25 extern void build_tlb_refill_handler(void);
28 * Make sure all entries differ. If they're not different
29 * MIPS32 will take revenge ...
31 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
33 /* Atomicity and interruptability */
34 #ifdef CONFIG_MIPS_MT_SMTC
37 #include <asm/mipsmtregs.h>
39 #define ENTER_CRITICAL(flags) \
41 unsigned int mvpflags; \
42 local_irq_save(flags);\
44 #define EXIT_CRITICAL(flags) \
46 local_irq_restore(flags); \
50 #define ENTER_CRITICAL(flags) local_irq_save(flags)
51 #define EXIT_CRITICAL(flags) local_irq_restore(flags)
53 #endif /* CONFIG_MIPS_MT_SMTC */
56 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
57 * unfortrunately, itlb is not totally transparent to software.
59 static inline void flush_itlb(void)
61 switch (current_cpu_type()) {
70 static inline void flush_itlb_vm(struct vm_area_struct
*vma
)
72 if (vma
->vm_flags
& VM_EXEC
)
76 void local_flush_tlb_all(void)
79 unsigned long old_ctx
;
82 ENTER_CRITICAL(flags
);
83 /* Save old context and create impossible VPN2 value */
84 old_ctx
= read_c0_entryhi();
88 entry
= read_c0_wired();
90 /* Blast 'em all away. */
91 while (entry
< current_cpu_data
.tlbsize
) {
92 /* Make sure all entries differ. */
93 write_c0_entryhi(UNIQUE_ENTRYHI(entry
));
94 write_c0_index(entry
);
100 write_c0_entryhi(old_ctx
);
102 EXIT_CRITICAL(flags
);
104 EXPORT_SYMBOL(local_flush_tlb_all
);
106 /* All entries common to a mm share an asid. To effectively flush
107 these entries, we just bump the asid. */
108 void local_flush_tlb_mm(struct mm_struct
*mm
)
114 cpu
= smp_processor_id();
116 if (cpu_context(cpu
, mm
) != 0) {
117 drop_mmu_context(mm
, cpu
);
123 void local_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
126 struct mm_struct
*mm
= vma
->vm_mm
;
127 int cpu
= smp_processor_id();
129 if (cpu_context(cpu
, mm
) != 0) {
130 unsigned long size
, flags
;
132 ENTER_CRITICAL(flags
);
133 start
= round_down(start
, PAGE_SIZE
<< 1);
134 end
= round_up(end
, PAGE_SIZE
<< 1);
135 size
= (end
- start
) >> (PAGE_SHIFT
+ 1);
136 if (size
<= current_cpu_data
.tlbsize
/2) {
137 int oldpid
= read_c0_entryhi();
138 int newpid
= cpu_asid(cpu
, mm
);
140 while (start
< end
) {
143 write_c0_entryhi(start
| newpid
);
144 start
+= (PAGE_SIZE
<< 1);
148 idx
= read_c0_index();
149 write_c0_entrylo0(0);
150 write_c0_entrylo1(0);
153 /* Make sure all entries differ. */
154 write_c0_entryhi(UNIQUE_ENTRYHI(idx
));
159 write_c0_entryhi(oldpid
);
161 drop_mmu_context(mm
, cpu
);
164 EXIT_CRITICAL(flags
);
168 void local_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
170 unsigned long size
, flags
;
172 ENTER_CRITICAL(flags
);
173 size
= (end
- start
+ (PAGE_SIZE
- 1)) >> PAGE_SHIFT
;
174 size
= (size
+ 1) >> 1;
175 if (size
<= current_cpu_data
.tlbsize
/ 2) {
176 int pid
= read_c0_entryhi();
178 start
&= (PAGE_MASK
<< 1);
179 end
+= ((PAGE_SIZE
<< 1) - 1);
180 end
&= (PAGE_MASK
<< 1);
182 while (start
< end
) {
185 write_c0_entryhi(start
);
186 start
+= (PAGE_SIZE
<< 1);
190 idx
= read_c0_index();
191 write_c0_entrylo0(0);
192 write_c0_entrylo1(0);
195 /* Make sure all entries differ. */
196 write_c0_entryhi(UNIQUE_ENTRYHI(idx
));
201 write_c0_entryhi(pid
);
203 local_flush_tlb_all();
206 EXIT_CRITICAL(flags
);
209 void local_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
211 int cpu
= smp_processor_id();
213 if (cpu_context(cpu
, vma
->vm_mm
) != 0) {
215 int oldpid
, newpid
, idx
;
217 newpid
= cpu_asid(cpu
, vma
->vm_mm
);
218 page
&= (PAGE_MASK
<< 1);
219 ENTER_CRITICAL(flags
);
220 oldpid
= read_c0_entryhi();
221 write_c0_entryhi(page
| newpid
);
225 idx
= read_c0_index();
226 write_c0_entrylo0(0);
227 write_c0_entrylo1(0);
230 /* Make sure all entries differ. */
231 write_c0_entryhi(UNIQUE_ENTRYHI(idx
));
237 write_c0_entryhi(oldpid
);
239 EXIT_CRITICAL(flags
);
244 * This one is only used for pages with the global bit set so we don't care
245 * much about the ASID.
247 void local_flush_tlb_one(unsigned long page
)
252 ENTER_CRITICAL(flags
);
253 oldpid
= read_c0_entryhi();
254 page
&= (PAGE_MASK
<< 1);
255 write_c0_entryhi(page
);
259 idx
= read_c0_index();
260 write_c0_entrylo0(0);
261 write_c0_entrylo1(0);
263 /* Make sure all entries differ. */
264 write_c0_entryhi(UNIQUE_ENTRYHI(idx
));
269 write_c0_entryhi(oldpid
);
271 EXIT_CRITICAL(flags
);
275 * We will need multiple versions of update_mmu_cache(), one that just
276 * updates the TLB with the new pte(s), and another which also checks
277 * for the R4k "end of page" hardware bug and does the needy.
279 void __update_tlb(struct vm_area_struct
* vma
, unsigned long address
, pte_t pte
)
289 * Handle debugger faulting in for debugee.
291 if (current
->active_mm
!= vma
->vm_mm
)
294 ENTER_CRITICAL(flags
);
296 pid
= read_c0_entryhi() & ASID_MASK
;
297 address
&= (PAGE_MASK
<< 1);
298 write_c0_entryhi(address
| pid
);
299 pgdp
= pgd_offset(vma
->vm_mm
, address
);
303 pudp
= pud_offset(pgdp
, address
);
304 pmdp
= pmd_offset(pudp
, address
);
305 idx
= read_c0_index();
306 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
307 /* this could be a huge page */
308 if (pmd_huge(*pmdp
)) {
310 write_c0_pagemask(PM_HUGE_MASK
);
311 ptep
= (pte_t
*)pmdp
;
312 lo
= pte_to_entrylo(pte_val(*ptep
));
313 write_c0_entrylo0(lo
);
314 write_c0_entrylo1(lo
+ (HPAGE_SIZE
>> 7));
322 write_c0_pagemask(PM_DEFAULT_MASK
);
326 ptep
= pte_offset_map(pmdp
, address
);
328 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
329 write_c0_entrylo0(ptep
->pte_high
);
331 write_c0_entrylo1(ptep
->pte_high
);
333 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep
++)));
334 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep
)));
344 EXIT_CRITICAL(flags
);
347 void add_wired_entry(unsigned long entrylo0
, unsigned long entrylo1
,
348 unsigned long entryhi
, unsigned long pagemask
)
352 unsigned long old_pagemask
;
353 unsigned long old_ctx
;
355 ENTER_CRITICAL(flags
);
356 /* Save old context and create impossible VPN2 value */
357 old_ctx
= read_c0_entryhi();
358 old_pagemask
= read_c0_pagemask();
359 wired
= read_c0_wired();
360 write_c0_wired(wired
+ 1);
361 write_c0_index(wired
);
362 tlbw_use_hazard(); /* What is the hazard here? */
363 write_c0_pagemask(pagemask
);
364 write_c0_entryhi(entryhi
);
365 write_c0_entrylo0(entrylo0
);
366 write_c0_entrylo1(entrylo1
);
371 write_c0_entryhi(old_ctx
);
372 tlbw_use_hazard(); /* What is the hazard here? */
373 write_c0_pagemask(old_pagemask
);
374 local_flush_tlb_all();
375 EXIT_CRITICAL(flags
);
378 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
380 int __init
has_transparent_hugepage(void)
385 ENTER_CRITICAL(flags
);
386 write_c0_pagemask(PM_HUGE_MASK
);
387 back_to_back_c0_hazard();
388 mask
= read_c0_pagemask();
389 write_c0_pagemask(PM_DEFAULT_MASK
);
391 EXIT_CRITICAL(flags
);
393 return mask
== PM_HUGE_MASK
;
396 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
399 static int __init
set_ntlb(char *str
)
401 get_option(&str
, &ntlb
);
405 __setup("ntlb=", set_ntlb
);
410 * You should never change this register:
411 * - On R4600 1.7 the tlbp never hits for pages smaller than
412 * the value in the c0_pagemask register.
413 * - The entire mm handling assumes the c0_pagemask register to
414 * be set to fixed-size pages.
416 write_c0_pagemask(PM_DEFAULT_MASK
);
418 if (current_cpu_type() == CPU_R10000
||
419 current_cpu_type() == CPU_R12000
||
420 current_cpu_type() == CPU_R14000
)
421 write_c0_framemask(0);
425 * Enable the no read, no exec bits, and enable large virtual
428 u32 pg
= PG_RIE
| PG_XIE
;
432 write_c0_pagegrain(pg
);
435 /* From this point on the ARC firmware is dead. */
436 local_flush_tlb_all();
438 /* Did I tell you that ARC SUCKS? */
441 if (ntlb
> 1 && ntlb
<= current_cpu_data
.tlbsize
) {
442 int wired
= current_cpu_data
.tlbsize
- ntlb
;
443 write_c0_wired(wired
);
444 write_c0_index(wired
-1);
445 printk("Restricting TLB to %d entries\n", ntlb
);
447 printk("Ignoring invalid argument ntlb=%d\n", ntlb
);
450 build_tlb_refill_handler();
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