2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/init.h>
30 #include <linux/cache.h>
32 #include <asm/cacheflush.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
39 * TLB load/store/modify handlers.
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
47 struct work_registers
{
56 } ____cacheline_aligned_in_smp
;
58 static struct tlb_reg_save handler_reg_save
[NR_CPUS
];
60 static inline int r45k_bvahwbug(void)
62 /* XXX: We should probe for the presence of this bug, but we don't. */
66 static inline int r4k_250MHZhwbug(void)
68 /* XXX: We should probe for the presence of this bug, but we don't. */
72 static inline int __maybe_unused
bcm1250_m3_war(void)
74 return BCM1250_M3_WAR
;
77 static inline int __maybe_unused
r10000_llsc_war(void)
79 return R10000_LLSC_WAR
;
82 static int use_bbit_insns(void)
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON
:
86 case CPU_CAVIUM_OCTEON_PLUS
:
87 case CPU_CAVIUM_OCTEON2
:
94 static int use_lwx_insns(void)
96 switch (current_cpu_type()) {
97 case CPU_CAVIUM_OCTEON2
:
103 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
104 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
105 static bool scratchpad_available(void)
109 static int scratchpad_offset(int i
)
112 * CVMSEG starts at address -32768 and extends for
113 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
115 i
+= 1; /* Kernel use starts at the top and works down. */
116 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
* 128 - (8 * i
) - 32768;
119 static bool scratchpad_available(void)
123 static int scratchpad_offset(int i
)
126 /* Really unreachable, but evidently some GCC want this. */
131 * Found by experiment: At least some revisions of the 4kc throw under
132 * some circumstances a machine check exception, triggered by invalid
133 * values in the index register. Delaying the tlbp instruction until
134 * after the next branch, plus adding an additional nop in front of
135 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
136 * why; it's not an issue caused by the core RTL.
139 static int __cpuinit
m4kc_tlbp_war(void)
141 return (current_cpu_data
.processor_id
& 0xffff00) ==
142 (PRID_COMP_MIPS
| PRID_IMP_4KC
);
145 /* Handle labels (which must be positive integers). */
147 label_second_part
= 1,
152 label_split
= label_tlbw_hazard_0
+ 8,
153 label_tlbl_goaround1
,
154 label_tlbl_goaround2
,
158 label_smp_pgtable_change
,
159 label_r3000_write_probe_fail
,
160 label_large_segbits_fault
,
161 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
162 label_tlb_huge_update
,
166 UASM_L_LA(_second_part
)
169 UASM_L_LA(_vmalloc_done
)
170 /* _tlbw_hazard_x is handled differently. */
172 UASM_L_LA(_tlbl_goaround1
)
173 UASM_L_LA(_tlbl_goaround2
)
174 UASM_L_LA(_nopage_tlbl
)
175 UASM_L_LA(_nopage_tlbs
)
176 UASM_L_LA(_nopage_tlbm
)
177 UASM_L_LA(_smp_pgtable_change
)
178 UASM_L_LA(_r3000_write_probe_fail
)
179 UASM_L_LA(_large_segbits_fault
)
180 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
181 UASM_L_LA(_tlb_huge_update
)
184 static int __cpuinitdata hazard_instance
;
186 static void __cpuinit
uasm_bgezl_hazard(u32
**p
,
187 struct uasm_reloc
**r
,
192 uasm_il_bgezl(p
, r
, 0, label_tlbw_hazard_0
+ instance
);
199 static void __cpuinit
uasm_bgezl_label(struct uasm_label
**l
,
205 uasm_build_label(l
, *p
, label_tlbw_hazard_0
+ instance
);
213 * pgtable bits are assigned dynamically depending on processor feature
214 * and statically based on kernel configuration. This spits out the actual
215 * values the kernel is using. Required to make sense from disassembled
216 * TLB exception handlers.
218 static void output_pgtable_bits_defines(void)
220 #define pr_define(fmt, ...) \
221 pr_debug("#define " fmt, ##__VA_ARGS__)
223 pr_debug("#include <asm/asm.h>\n");
224 pr_debug("#include <asm/regdef.h>\n");
227 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT
);
228 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT
);
229 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT
);
230 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT
);
231 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT
);
232 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
233 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT
);
234 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT
);
237 #ifdef _PAGE_NO_EXEC_SHIFT
238 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT
);
240 #ifdef _PAGE_NO_READ_SHIFT
241 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT
);
244 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT
);
245 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT
);
246 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT
);
247 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT
);
251 static inline void dump_handler(const char *symbol
, const u32
*handler
, int count
)
255 pr_debug("LEAF(%s)\n", symbol
);
257 pr_debug("\t.set push\n");
258 pr_debug("\t.set noreorder\n");
260 for (i
= 0; i
< count
; i
++)
261 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler
[i
], &handler
[i
]);
263 pr_debug("\t.set\tpop\n");
265 pr_debug("\tEND(%s)\n", symbol
);
268 /* The only general purpose registers allowed in TLB handlers. */
272 /* Some CP0 registers */
273 #define C0_INDEX 0, 0
274 #define C0_ENTRYLO0 2, 0
275 #define C0_TCBIND 2, 2
276 #define C0_ENTRYLO1 3, 0
277 #define C0_CONTEXT 4, 0
278 #define C0_PAGEMASK 5, 0
279 #define C0_BADVADDR 8, 0
280 #define C0_ENTRYHI 10, 0
282 #define C0_XCONTEXT 20, 0
285 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
287 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
290 /* The worst case length of the handler is around 18 instructions for
291 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
292 * Maximum space available is 32 instructions for R3000 and 64
293 * instructions for R4000.
295 * We deliberately chose a buffer size of 128, so we won't scribble
296 * over anything important on overflow before we panic.
298 static u32 tlb_handler
[128] __cpuinitdata
;
300 /* simply assume worst case size for labels and relocs */
301 static struct uasm_label labels
[128] __cpuinitdata
;
302 static struct uasm_reloc relocs
[128] __cpuinitdata
;
304 static int check_for_high_segbits __cpuinitdata
;
306 static unsigned int kscratch_used_mask __cpuinitdata
;
308 static inline int __maybe_unused
c0_kscratch(void)
310 switch (current_cpu_type()) {
319 static int __cpuinit
allocate_kscratch(void)
322 unsigned int a
= cpu_data
[0].kscratch_mask
& ~kscratch_used_mask
;
329 r
--; /* make it zero based */
331 kscratch_used_mask
|= (1 << r
);
336 static int scratch_reg __cpuinitdata
;
337 static int pgd_reg __cpuinitdata
;
338 enum vmalloc64_mode
{not_refill
, refill_scratch
, refill_noscratch
};
340 static struct work_registers __cpuinit
build_get_work_registers(u32
**p
)
342 struct work_registers r
;
344 int smp_processor_id_reg
;
345 int smp_processor_id_sel
;
346 int smp_processor_id_shift
;
348 if (scratch_reg
>= 0) {
349 /* Save in CPU local C0_KScratch? */
350 UASM_i_MTC0(p
, 1, c0_kscratch(), scratch_reg
);
357 if (num_possible_cpus() > 1) {
358 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
359 smp_processor_id_shift
= 51;
360 smp_processor_id_reg
= 20; /* XContext */
361 smp_processor_id_sel
= 0;
364 smp_processor_id_shift
= 25;
365 smp_processor_id_reg
= 4; /* Context */
366 smp_processor_id_sel
= 0;
369 smp_processor_id_shift
= 26;
370 smp_processor_id_reg
= 4; /* Context */
371 smp_processor_id_sel
= 0;
374 /* Get smp_processor_id */
375 UASM_i_MFC0(p
, K0
, smp_processor_id_reg
, smp_processor_id_sel
);
376 UASM_i_SRL_SAFE(p
, K0
, K0
, smp_processor_id_shift
);
378 /* handler_reg_save index in K0 */
379 UASM_i_SLL(p
, K0
, K0
, ilog2(sizeof(struct tlb_reg_save
)));
381 UASM_i_LA(p
, K1
, (long)&handler_reg_save
);
382 UASM_i_ADDU(p
, K0
, K0
, K1
);
384 UASM_i_LA(p
, K0
, (long)&handler_reg_save
);
386 /* K0 now points to save area, save $1 and $2 */
387 UASM_i_SW(p
, 1, offsetof(struct tlb_reg_save
, a
), K0
);
388 UASM_i_SW(p
, 2, offsetof(struct tlb_reg_save
, b
), K0
);
396 static void __cpuinit
build_restore_work_registers(u32
**p
)
398 if (scratch_reg
>= 0) {
399 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
402 /* K0 already points to save area, restore $1 and $2 */
403 UASM_i_LW(p
, 1, offsetof(struct tlb_reg_save
, a
), K0
);
404 UASM_i_LW(p
, 2, offsetof(struct tlb_reg_save
, b
), K0
);
407 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
410 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
411 * we cannot do r3000 under these circumstances.
413 * Declare pgd_current here instead of including mmu_context.h to avoid type
414 * conflicts for tlbmiss_handler_setup_pgd
416 extern unsigned long pgd_current
[];
419 * The R3000 TLB handler is simple.
421 static void __cpuinit
build_r3000_tlb_refill_handler(void)
423 long pgdc
= (long)pgd_current
;
426 memset(tlb_handler
, 0, sizeof(tlb_handler
));
429 uasm_i_mfc0(&p
, K0
, C0_BADVADDR
);
430 uasm_i_lui(&p
, K1
, uasm_rel_hi(pgdc
)); /* cp0 delay */
431 uasm_i_lw(&p
, K1
, uasm_rel_lo(pgdc
), K1
);
432 uasm_i_srl(&p
, K0
, K0
, 22); /* load delay */
433 uasm_i_sll(&p
, K0
, K0
, 2);
434 uasm_i_addu(&p
, K1
, K1
, K0
);
435 uasm_i_mfc0(&p
, K0
, C0_CONTEXT
);
436 uasm_i_lw(&p
, K1
, 0, K1
); /* cp0 delay */
437 uasm_i_andi(&p
, K0
, K0
, 0xffc); /* load delay */
438 uasm_i_addu(&p
, K1
, K1
, K0
);
439 uasm_i_lw(&p
, K0
, 0, K1
);
440 uasm_i_nop(&p
); /* load delay */
441 uasm_i_mtc0(&p
, K0
, C0_ENTRYLO0
);
442 uasm_i_mfc0(&p
, K1
, C0_EPC
); /* cp0 delay */
443 uasm_i_tlbwr(&p
); /* cp0 delay */
445 uasm_i_rfe(&p
); /* branch delay */
447 if (p
> tlb_handler
+ 32)
448 panic("TLB refill handler space exceeded");
450 pr_debug("Wrote TLB refill handler (%u instructions).\n",
451 (unsigned int)(p
- tlb_handler
));
453 memcpy((void *)ebase
, tlb_handler
, 0x80);
455 dump_handler("r3000_tlb_refill", (u32
*)ebase
, 32);
457 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
460 * The R4000 TLB handler is much more complicated. We have two
461 * consecutive handler areas with 32 instructions space each.
462 * Since they aren't used at the same time, we can overflow in the
463 * other one.To keep things simple, we first assume linear space,
464 * then we relocate it to the final handler layout as needed.
466 static u32 final_handler
[64] __cpuinitdata
;
471 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
472 * 2. A timing hazard exists for the TLBP instruction.
474 * stalling_instruction
477 * The JTLB is being read for the TLBP throughout the stall generated by the
478 * previous instruction. This is not really correct as the stalling instruction
479 * can modify the address used to access the JTLB. The failure symptom is that
480 * the TLBP instruction will use an address created for the stalling instruction
481 * and not the address held in C0_ENHI and thus report the wrong results.
483 * The software work-around is to not allow the instruction preceding the TLBP
484 * to stall - make it an NOP or some other instruction guaranteed not to stall.
486 * Errata 2 will not be fixed. This errata is also on the R5000.
488 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
490 static void __cpuinit __maybe_unused
build_tlb_probe_entry(u32
**p
)
492 switch (current_cpu_type()) {
493 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
509 * Write random or indexed TLB entry, and care about the hazards from
510 * the preceding mtc0 and for the following eret.
512 enum tlb_write_entry
{ tlb_random
, tlb_indexed
};
514 static void __cpuinit
build_tlb_write_entry(u32
**p
, struct uasm_label
**l
,
515 struct uasm_reloc
**r
,
516 enum tlb_write_entry wmode
)
518 void(*tlbw
)(u32
**) = NULL
;
521 case tlb_random
: tlbw
= uasm_i_tlbwr
; break;
522 case tlb_indexed
: tlbw
= uasm_i_tlbwi
; break;
525 if (cpu_has_mips_r2
) {
527 * The architecture spec says an ehb is required here,
528 * but a number of cores do not have the hazard and
529 * using an ehb causes an expensive pipeline stall.
531 switch (current_cpu_type()) {
544 switch (current_cpu_type()) {
552 * This branch uses up a mtc0 hazard nop slot and saves
553 * two nops after the tlbw instruction.
555 uasm_bgezl_hazard(p
, r
, hazard_instance
);
557 uasm_bgezl_label(l
, p
, hazard_instance
);
571 uasm_i_nop(p
); /* QED specifies 2 nops hazard */
572 uasm_i_nop(p
); /* QED specifies 2 nops hazard */
644 panic("No TLB refill handler yet (CPU type: %d)",
645 current_cpu_data
.cputype
);
650 static __cpuinit __maybe_unused
void build_convert_pte_to_entrylo(u32
**p
,
654 UASM_i_ROTR(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
656 #ifdef CONFIG_64BIT_PHYS_ADDR
657 uasm_i_dsrl_safe(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
659 UASM_i_SRL(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
664 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
666 static __cpuinit
void build_restore_pagemask(u32
**p
,
667 struct uasm_reloc
**r
,
672 if (restore_scratch
) {
673 /* Reset default page size */
674 if (PM_DEFAULT_MASK
>> 16) {
675 uasm_i_lui(p
, tmp
, PM_DEFAULT_MASK
>> 16);
676 uasm_i_ori(p
, tmp
, tmp
, PM_DEFAULT_MASK
& 0xffff);
677 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
678 uasm_il_b(p
, r
, lid
);
679 } else if (PM_DEFAULT_MASK
) {
680 uasm_i_ori(p
, tmp
, 0, PM_DEFAULT_MASK
);
681 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
682 uasm_il_b(p
, r
, lid
);
684 uasm_i_mtc0(p
, 0, C0_PAGEMASK
);
685 uasm_il_b(p
, r
, lid
);
687 if (scratch_reg
>= 0)
688 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
690 UASM_i_LW(p
, 1, scratchpad_offset(0), 0);
692 /* Reset default page size */
693 if (PM_DEFAULT_MASK
>> 16) {
694 uasm_i_lui(p
, tmp
, PM_DEFAULT_MASK
>> 16);
695 uasm_i_ori(p
, tmp
, tmp
, PM_DEFAULT_MASK
& 0xffff);
696 uasm_il_b(p
, r
, lid
);
697 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
698 } else if (PM_DEFAULT_MASK
) {
699 uasm_i_ori(p
, tmp
, 0, PM_DEFAULT_MASK
);
700 uasm_il_b(p
, r
, lid
);
701 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
703 uasm_il_b(p
, r
, lid
);
704 uasm_i_mtc0(p
, 0, C0_PAGEMASK
);
709 static __cpuinit
void build_huge_tlb_write_entry(u32
**p
,
710 struct uasm_label
**l
,
711 struct uasm_reloc
**r
,
713 enum tlb_write_entry wmode
,
716 /* Set huge page tlb entry size */
717 uasm_i_lui(p
, tmp
, PM_HUGE_MASK
>> 16);
718 uasm_i_ori(p
, tmp
, tmp
, PM_HUGE_MASK
& 0xffff);
719 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
721 build_tlb_write_entry(p
, l
, r
, wmode
);
723 build_restore_pagemask(p
, r
, tmp
, label_leave
, restore_scratch
);
727 * Check if Huge PTE is present, if so then jump to LABEL.
729 static void __cpuinit
730 build_is_huge_pte(u32
**p
, struct uasm_reloc
**r
, unsigned int tmp
,
731 unsigned int pmd
, int lid
)
733 UASM_i_LW(p
, tmp
, 0, pmd
);
734 if (use_bbit_insns()) {
735 uasm_il_bbit1(p
, r
, tmp
, ilog2(_PAGE_HUGE
), lid
);
737 uasm_i_andi(p
, tmp
, tmp
, _PAGE_HUGE
);
738 uasm_il_bnez(p
, r
, tmp
, lid
);
742 static __cpuinit
void build_huge_update_entries(u32
**p
,
749 * A huge PTE describes an area the size of the
750 * configured huge page size. This is twice the
751 * of the large TLB entry size we intend to use.
752 * A TLB entry half the size of the configured
753 * huge page size is configured into entrylo0
754 * and entrylo1 to cover the contiguous huge PTE
757 small_sequence
= (HPAGE_SIZE
>> 7) < 0x10000;
759 /* We can clobber tmp. It isn't used after this.*/
761 uasm_i_lui(p
, tmp
, HPAGE_SIZE
>> (7 + 16));
763 build_convert_pte_to_entrylo(p
, pte
);
764 UASM_i_MTC0(p
, pte
, C0_ENTRYLO0
); /* load it */
765 /* convert to entrylo1 */
767 UASM_i_ADDIU(p
, pte
, pte
, HPAGE_SIZE
>> 7);
769 UASM_i_ADDU(p
, pte
, pte
, tmp
);
771 UASM_i_MTC0(p
, pte
, C0_ENTRYLO1
); /* load it */
774 static __cpuinit
void build_huge_handler_tail(u32
**p
,
775 struct uasm_reloc
**r
,
776 struct uasm_label
**l
,
781 UASM_i_SC(p
, pte
, 0, ptr
);
782 uasm_il_beqz(p
, r
, pte
, label_tlb_huge_update
);
783 UASM_i_LW(p
, pte
, 0, ptr
); /* Needed because SC killed our PTE */
785 UASM_i_SW(p
, pte
, 0, ptr
);
787 build_huge_update_entries(p
, pte
, ptr
);
788 build_huge_tlb_write_entry(p
, l
, r
, pte
, tlb_indexed
, 0);
790 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
794 * TMP and PTR are scratch.
795 * TMP will be clobbered, PTR will hold the pmd entry.
797 static void __cpuinit
798 build_get_pmde64(u32
**p
, struct uasm_label
**l
, struct uasm_reloc
**r
,
799 unsigned int tmp
, unsigned int ptr
)
801 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
802 long pgdc
= (long)pgd_current
;
805 * The vmalloc handling is not in the hotpath.
807 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
);
809 if (check_for_high_segbits
) {
811 * The kernel currently implicitely assumes that the
812 * MIPS SEGBITS parameter for the processor is
813 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
814 * allocate virtual addresses outside the maximum
815 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
816 * that doesn't prevent user code from accessing the
817 * higher xuseg addresses. Here, we make sure that
818 * everything but the lower xuseg addresses goes down
819 * the module_alloc/vmalloc path.
821 uasm_i_dsrl_safe(p
, ptr
, tmp
, PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
822 uasm_il_bnez(p
, r
, ptr
, label_vmalloc
);
824 uasm_il_bltz(p
, r
, tmp
, label_vmalloc
);
826 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
828 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
830 /* pgd is in pgd_reg */
831 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
834 * &pgd << 11 stored in CONTEXT [23..63].
836 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
838 /* Clear lower 23 bits of context. */
839 uasm_i_dins(p
, ptr
, 0, 0, 23);
841 /* 1 0 1 0 1 << 6 xkphys cached */
842 uasm_i_ori(p
, ptr
, ptr
, 0x540);
843 uasm_i_drotr(p
, ptr
, ptr
, 11);
845 #elif defined(CONFIG_SMP)
846 # ifdef CONFIG_MIPS_MT_SMTC
848 * SMTC uses TCBind value as "CPU" index
850 uasm_i_mfc0(p
, ptr
, C0_TCBIND
);
851 uasm_i_dsrl_safe(p
, ptr
, ptr
, 19);
854 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
857 uasm_i_dmfc0(p
, ptr
, C0_CONTEXT
);
858 uasm_i_dsrl_safe(p
, ptr
, ptr
, 23);
860 UASM_i_LA_mostly(p
, tmp
, pgdc
);
861 uasm_i_daddu(p
, ptr
, ptr
, tmp
);
862 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
);
863 uasm_i_ld(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
865 UASM_i_LA_mostly(p
, ptr
, pgdc
);
866 uasm_i_ld(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
869 uasm_l_vmalloc_done(l
, *p
);
871 /* get pgd offset in bytes */
872 uasm_i_dsrl_safe(p
, tmp
, tmp
, PGDIR_SHIFT
- 3);
874 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PGD
- 1)<<3);
875 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
876 #ifndef __PAGETABLE_PMD_FOLDED
877 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
878 uasm_i_ld(p
, ptr
, 0, ptr
); /* get pmd pointer */
879 uasm_i_dsrl_safe(p
, tmp
, tmp
, PMD_SHIFT
-3); /* get pmd offset in bytes */
880 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PMD
- 1)<<3);
881 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pmd offset */
886 * BVADDR is the faulting address, PTR is scratch.
887 * PTR will hold the pgd for vmalloc.
889 static void __cpuinit
890 build_get_pgd_vmalloc64(u32
**p
, struct uasm_label
**l
, struct uasm_reloc
**r
,
891 unsigned int bvaddr
, unsigned int ptr
,
892 enum vmalloc64_mode mode
)
894 long swpd
= (long)swapper_pg_dir
;
895 int single_insn_swpd
;
896 int did_vmalloc_branch
= 0;
898 single_insn_swpd
= uasm_in_compat_space_p(swpd
) && !uasm_rel_lo(swpd
);
900 uasm_l_vmalloc(l
, *p
);
902 if (mode
!= not_refill
&& check_for_high_segbits
) {
903 if (single_insn_swpd
) {
904 uasm_il_bltz(p
, r
, bvaddr
, label_vmalloc_done
);
905 uasm_i_lui(p
, ptr
, uasm_rel_hi(swpd
));
906 did_vmalloc_branch
= 1;
909 uasm_il_bgez(p
, r
, bvaddr
, label_large_segbits_fault
);
912 if (!did_vmalloc_branch
) {
913 if (uasm_in_compat_space_p(swpd
) && !uasm_rel_lo(swpd
)) {
914 uasm_il_b(p
, r
, label_vmalloc_done
);
915 uasm_i_lui(p
, ptr
, uasm_rel_hi(swpd
));
917 UASM_i_LA_mostly(p
, ptr
, swpd
);
918 uasm_il_b(p
, r
, label_vmalloc_done
);
919 if (uasm_in_compat_space_p(swpd
))
920 uasm_i_addiu(p
, ptr
, ptr
, uasm_rel_lo(swpd
));
922 uasm_i_daddiu(p
, ptr
, ptr
, uasm_rel_lo(swpd
));
925 if (mode
!= not_refill
&& check_for_high_segbits
) {
926 uasm_l_large_segbits_fault(l
, *p
);
928 * We get here if we are an xsseg address, or if we are
929 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
931 * Ignoring xsseg (assume disabled so would generate
932 * (address errors?), the only remaining possibility
933 * is the upper xuseg addresses. On processors with
934 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
935 * addresses would have taken an address error. We try
936 * to mimic that here by taking a load/istream page
939 UASM_i_LA(p
, ptr
, (unsigned long)tlb_do_page_fault_0
);
942 if (mode
== refill_scratch
) {
943 if (scratch_reg
>= 0)
944 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
946 UASM_i_LW(p
, 1, scratchpad_offset(0), 0);
953 #else /* !CONFIG_64BIT */
956 * TMP and PTR are scratch.
957 * TMP will be clobbered, PTR will hold the pgd entry.
959 static void __cpuinit __maybe_unused
960 build_get_pgde32(u32
**p
, unsigned int tmp
, unsigned int ptr
)
962 long pgdc
= (long)pgd_current
;
964 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
966 #ifdef CONFIG_MIPS_MT_SMTC
968 * SMTC uses TCBind value as "CPU" index
970 uasm_i_mfc0(p
, ptr
, C0_TCBIND
);
971 UASM_i_LA_mostly(p
, tmp
, pgdc
);
972 uasm_i_srl(p
, ptr
, ptr
, 19);
975 * smp_processor_id() << 2 is stored in CONTEXT.
977 uasm_i_mfc0(p
, ptr
, C0_CONTEXT
);
978 UASM_i_LA_mostly(p
, tmp
, pgdc
);
979 uasm_i_srl(p
, ptr
, ptr
, 23);
981 uasm_i_addu(p
, ptr
, tmp
, ptr
);
983 UASM_i_LA_mostly(p
, ptr
, pgdc
);
985 uasm_i_mfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
986 uasm_i_lw(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
987 uasm_i_srl(p
, tmp
, tmp
, PGDIR_SHIFT
); /* get pgd only bits */
988 uasm_i_sll(p
, tmp
, tmp
, PGD_T_LOG2
);
989 uasm_i_addu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
992 #endif /* !CONFIG_64BIT */
994 static void __cpuinit
build_adjust_context(u32
**p
, unsigned int ctx
)
996 unsigned int shift
= 4 - (PTE_T_LOG2
+ 1) + PAGE_SHIFT
- 12;
997 unsigned int mask
= (PTRS_PER_PTE
/ 2 - 1) << (PTE_T_LOG2
+ 1);
999 switch (current_cpu_type()) {
1016 UASM_i_SRL(p
, ctx
, ctx
, shift
);
1017 uasm_i_andi(p
, ctx
, ctx
, mask
);
1020 static void __cpuinit
build_get_ptep(u32
**p
, unsigned int tmp
, unsigned int ptr
)
1023 * Bug workaround for the Nevada. It seems as if under certain
1024 * circumstances the move from cp0_context might produce a
1025 * bogus result when the mfc0 instruction and its consumer are
1026 * in a different cacheline or a load instruction, probably any
1027 * memory reference, is between them.
1029 switch (current_cpu_type()) {
1031 UASM_i_LW(p
, ptr
, 0, ptr
);
1032 GET_CONTEXT(p
, tmp
); /* get context reg */
1036 GET_CONTEXT(p
, tmp
); /* get context reg */
1037 UASM_i_LW(p
, ptr
, 0, ptr
);
1041 build_adjust_context(p
, tmp
);
1042 UASM_i_ADDU(p
, ptr
, ptr
, tmp
); /* add in offset */
1045 static void __cpuinit
build_update_entries(u32
**p
, unsigned int tmp
,
1049 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1050 * Kernel is a special case. Only a few CPUs use it.
1052 #ifdef CONFIG_64BIT_PHYS_ADDR
1053 if (cpu_has_64bits
) {
1054 uasm_i_ld(p
, tmp
, 0, ptep
); /* get even pte */
1055 uasm_i_ld(p
, ptep
, sizeof(pte_t
), ptep
); /* get odd pte */
1057 UASM_i_ROTR(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
));
1058 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1059 UASM_i_ROTR(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
));
1061 uasm_i_dsrl_safe(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo0 */
1062 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1063 uasm_i_dsrl_safe(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo1 */
1065 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1067 int pte_off_even
= sizeof(pte_t
) / 2;
1068 int pte_off_odd
= pte_off_even
+ sizeof(pte_t
);
1070 /* The pte entries are pre-shifted */
1071 uasm_i_lw(p
, tmp
, pte_off_even
, ptep
); /* get even pte */
1072 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1073 uasm_i_lw(p
, ptep
, pte_off_odd
, ptep
); /* get odd pte */
1074 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1077 UASM_i_LW(p
, tmp
, 0, ptep
); /* get even pte */
1078 UASM_i_LW(p
, ptep
, sizeof(pte_t
), ptep
); /* get odd pte */
1079 if (r45k_bvahwbug())
1080 build_tlb_probe_entry(p
);
1082 UASM_i_ROTR(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
));
1083 if (r4k_250MHZhwbug())
1084 UASM_i_MTC0(p
, 0, C0_ENTRYLO0
);
1085 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1086 UASM_i_ROTR(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
));
1088 UASM_i_SRL(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo0 */
1089 if (r4k_250MHZhwbug())
1090 UASM_i_MTC0(p
, 0, C0_ENTRYLO0
);
1091 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1092 UASM_i_SRL(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo1 */
1093 if (r45k_bvahwbug())
1094 uasm_i_mfc0(p
, tmp
, C0_INDEX
);
1096 if (r4k_250MHZhwbug())
1097 UASM_i_MTC0(p
, 0, C0_ENTRYLO1
);
1098 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1102 struct mips_huge_tlb_info
{
1104 int restore_scratch
;
1107 static struct mips_huge_tlb_info __cpuinit
1108 build_fast_tlb_refill_handler (u32
**p
, struct uasm_label
**l
,
1109 struct uasm_reloc
**r
, unsigned int tmp
,
1110 unsigned int ptr
, int c0_scratch_reg
)
1112 struct mips_huge_tlb_info rv
;
1113 unsigned int even
, odd
;
1114 int vmalloc_branch_delay_filled
= 0;
1115 const int scratch
= 1; /* Our extra working register */
1117 rv
.huge_pte
= scratch
;
1118 rv
.restore_scratch
= 0;
1120 if (check_for_high_segbits
) {
1121 UASM_i_MFC0(p
, tmp
, C0_BADVADDR
);
1124 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
1126 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
1128 if (c0_scratch_reg
>= 0)
1129 UASM_i_MTC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1131 UASM_i_SW(p
, scratch
, scratchpad_offset(0), 0);
1133 uasm_i_dsrl_safe(p
, scratch
, tmp
,
1134 PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
1135 uasm_il_bnez(p
, r
, scratch
, label_vmalloc
);
1137 if (pgd_reg
== -1) {
1138 vmalloc_branch_delay_filled
= 1;
1139 /* Clear lower 23 bits of context. */
1140 uasm_i_dins(p
, ptr
, 0, 0, 23);
1144 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
1146 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
1148 UASM_i_MFC0(p
, tmp
, C0_BADVADDR
);
1150 if (c0_scratch_reg
>= 0)
1151 UASM_i_MTC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1153 UASM_i_SW(p
, scratch
, scratchpad_offset(0), 0);
1156 /* Clear lower 23 bits of context. */
1157 uasm_i_dins(p
, ptr
, 0, 0, 23);
1159 uasm_il_bltz(p
, r
, tmp
, label_vmalloc
);
1162 if (pgd_reg
== -1) {
1163 vmalloc_branch_delay_filled
= 1;
1164 /* 1 0 1 0 1 << 6 xkphys cached */
1165 uasm_i_ori(p
, ptr
, ptr
, 0x540);
1166 uasm_i_drotr(p
, ptr
, ptr
, 11);
1169 #ifdef __PAGETABLE_PMD_FOLDED
1170 #define LOC_PTEP scratch
1172 #define LOC_PTEP ptr
1175 if (!vmalloc_branch_delay_filled
)
1176 /* get pgd offset in bytes */
1177 uasm_i_dsrl_safe(p
, scratch
, tmp
, PGDIR_SHIFT
- 3);
1179 uasm_l_vmalloc_done(l
, *p
);
1183 * fall-through case = badvaddr *pgd_current
1184 * vmalloc case = badvaddr swapper_pg_dir
1187 if (vmalloc_branch_delay_filled
)
1188 /* get pgd offset in bytes */
1189 uasm_i_dsrl_safe(p
, scratch
, tmp
, PGDIR_SHIFT
- 3);
1191 #ifdef __PAGETABLE_PMD_FOLDED
1192 GET_CONTEXT(p
, tmp
); /* get context reg */
1194 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PGD
- 1) << 3);
1196 if (use_lwx_insns()) {
1197 UASM_i_LWX(p
, LOC_PTEP
, scratch
, ptr
);
1199 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pgd offset */
1200 uasm_i_ld(p
, LOC_PTEP
, 0, ptr
); /* get pmd pointer */
1203 #ifndef __PAGETABLE_PMD_FOLDED
1204 /* get pmd offset in bytes */
1205 uasm_i_dsrl_safe(p
, scratch
, tmp
, PMD_SHIFT
- 3);
1206 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PMD
- 1) << 3);
1207 GET_CONTEXT(p
, tmp
); /* get context reg */
1209 if (use_lwx_insns()) {
1210 UASM_i_LWX(p
, scratch
, scratch
, ptr
);
1212 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pmd offset */
1213 UASM_i_LW(p
, scratch
, 0, ptr
);
1216 /* Adjust the context during the load latency. */
1217 build_adjust_context(p
, tmp
);
1219 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1220 uasm_il_bbit1(p
, r
, scratch
, ilog2(_PAGE_HUGE
), label_tlb_huge_update
);
1222 * The in the LWX case we don't want to do the load in the
1223 * delay slot. It cannot issue in the same cycle and may be
1224 * speculative and unneeded.
1226 if (use_lwx_insns())
1228 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1231 /* build_update_entries */
1232 if (use_lwx_insns()) {
1235 UASM_i_LWX(p
, even
, scratch
, tmp
);
1236 UASM_i_ADDIU(p
, tmp
, tmp
, sizeof(pte_t
));
1237 UASM_i_LWX(p
, odd
, scratch
, tmp
);
1239 UASM_i_ADDU(p
, ptr
, scratch
, tmp
); /* add in offset */
1242 UASM_i_LW(p
, even
, 0, ptr
); /* get even pte */
1243 UASM_i_LW(p
, odd
, sizeof(pte_t
), ptr
); /* get odd pte */
1246 uasm_i_drotr(p
, even
, even
, ilog2(_PAGE_GLOBAL
));
1247 UASM_i_MTC0(p
, even
, C0_ENTRYLO0
); /* load it */
1248 uasm_i_drotr(p
, odd
, odd
, ilog2(_PAGE_GLOBAL
));
1250 uasm_i_dsrl_safe(p
, even
, even
, ilog2(_PAGE_GLOBAL
));
1251 UASM_i_MTC0(p
, even
, C0_ENTRYLO0
); /* load it */
1252 uasm_i_dsrl_safe(p
, odd
, odd
, ilog2(_PAGE_GLOBAL
));
1254 UASM_i_MTC0(p
, odd
, C0_ENTRYLO1
); /* load it */
1256 if (c0_scratch_reg
>= 0) {
1257 UASM_i_MFC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1258 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1259 uasm_l_leave(l
, *p
);
1260 rv
.restore_scratch
= 1;
1261 } else if (PAGE_SHIFT
== 14 || PAGE_SHIFT
== 13) {
1262 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1263 uasm_l_leave(l
, *p
);
1264 UASM_i_LW(p
, scratch
, scratchpad_offset(0), 0);
1266 UASM_i_LW(p
, scratch
, scratchpad_offset(0), 0);
1267 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1268 uasm_l_leave(l
, *p
);
1269 rv
.restore_scratch
= 1;
1272 uasm_i_eret(p
); /* return from trap */
1278 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1279 * because EXL == 0. If we wrap, we can also use the 32 instruction
1280 * slots before the XTLB refill exception handler which belong to the
1281 * unused TLB refill exception.
1283 #define MIPS64_REFILL_INSNS 32
1285 static void __cpuinit
build_r4000_tlb_refill_handler(void)
1287 u32
*p
= tlb_handler
;
1288 struct uasm_label
*l
= labels
;
1289 struct uasm_reloc
*r
= relocs
;
1291 unsigned int final_len
;
1292 struct mips_huge_tlb_info htlb_info __maybe_unused
;
1293 enum vmalloc64_mode vmalloc_mode __maybe_unused
;
1295 memset(tlb_handler
, 0, sizeof(tlb_handler
));
1296 memset(labels
, 0, sizeof(labels
));
1297 memset(relocs
, 0, sizeof(relocs
));
1298 memset(final_handler
, 0, sizeof(final_handler
));
1300 if ((scratch_reg
>= 0 || scratchpad_available()) && use_bbit_insns()) {
1301 htlb_info
= build_fast_tlb_refill_handler(&p
, &l
, &r
, K0
, K1
,
1303 vmalloc_mode
= refill_scratch
;
1305 htlb_info
.huge_pte
= K0
;
1306 htlb_info
.restore_scratch
= 0;
1307 vmalloc_mode
= refill_noscratch
;
1309 * create the plain linear handler
1311 if (bcm1250_m3_war()) {
1312 unsigned int segbits
= 44;
1314 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
1315 uasm_i_dmfc0(&p
, K1
, C0_ENTRYHI
);
1316 uasm_i_xor(&p
, K0
, K0
, K1
);
1317 uasm_i_dsrl_safe(&p
, K1
, K0
, 62);
1318 uasm_i_dsrl_safe(&p
, K0
, K0
, 12 + 1);
1319 uasm_i_dsll_safe(&p
, K0
, K0
, 64 + 12 + 1 - segbits
);
1320 uasm_i_or(&p
, K0
, K0
, K1
);
1321 uasm_il_bnez(&p
, &r
, K0
, label_leave
);
1322 /* No need for uasm_i_nop */
1326 build_get_pmde64(&p
, &l
, &r
, K0
, K1
); /* get pmd in K1 */
1328 build_get_pgde32(&p
, K0
, K1
); /* get pgd in K1 */
1331 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1332 build_is_huge_pte(&p
, &r
, K0
, K1
, label_tlb_huge_update
);
1335 build_get_ptep(&p
, K0
, K1
);
1336 build_update_entries(&p
, K0
, K1
);
1337 build_tlb_write_entry(&p
, &l
, &r
, tlb_random
);
1338 uasm_l_leave(&l
, p
);
1339 uasm_i_eret(&p
); /* return from trap */
1341 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1342 uasm_l_tlb_huge_update(&l
, p
);
1343 build_huge_update_entries(&p
, htlb_info
.huge_pte
, K1
);
1344 build_huge_tlb_write_entry(&p
, &l
, &r
, K0
, tlb_random
,
1345 htlb_info
.restore_scratch
);
1349 build_get_pgd_vmalloc64(&p
, &l
, &r
, K0
, K1
, vmalloc_mode
);
1353 * Overflow check: For the 64bit handler, we need at least one
1354 * free instruction slot for the wrap-around branch. In worst
1355 * case, if the intended insertion point is a delay slot, we
1356 * need three, with the second nop'ed and the third being
1359 /* Loongson2 ebase is different than r4k, we have more space */
1360 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1361 if ((p
- tlb_handler
) > 64)
1362 panic("TLB refill handler space exceeded");
1364 if (((p
- tlb_handler
) > (MIPS64_REFILL_INSNS
* 2) - 1)
1365 || (((p
- tlb_handler
) > (MIPS64_REFILL_INSNS
* 2) - 3)
1366 && uasm_insn_has_bdelay(relocs
,
1367 tlb_handler
+ MIPS64_REFILL_INSNS
- 3)))
1368 panic("TLB refill handler space exceeded");
1372 * Now fold the handler in the TLB refill handler space.
1374 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1376 /* Simplest case, just copy the handler. */
1377 uasm_copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1378 final_len
= p
- tlb_handler
;
1379 #else /* CONFIG_64BIT */
1380 f
= final_handler
+ MIPS64_REFILL_INSNS
;
1381 if ((p
- tlb_handler
) <= MIPS64_REFILL_INSNS
) {
1382 /* Just copy the handler. */
1383 uasm_copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1384 final_len
= p
- tlb_handler
;
1386 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1387 const enum label_id ls
= label_tlb_huge_update
;
1389 const enum label_id ls
= label_vmalloc
;
1395 for (i
= 0; i
< ARRAY_SIZE(labels
) && labels
[i
].lab
!= ls
; i
++)
1397 BUG_ON(i
== ARRAY_SIZE(labels
));
1398 split
= labels
[i
].addr
;
1401 * See if we have overflown one way or the other.
1403 if (split
> tlb_handler
+ MIPS64_REFILL_INSNS
||
1404 split
< p
- MIPS64_REFILL_INSNS
)
1409 * Split two instructions before the end. One
1410 * for the branch and one for the instruction
1411 * in the delay slot.
1413 split
= tlb_handler
+ MIPS64_REFILL_INSNS
- 2;
1416 * If the branch would fall in a delay slot,
1417 * we must back up an additional instruction
1418 * so that it is no longer in a delay slot.
1420 if (uasm_insn_has_bdelay(relocs
, split
- 1))
1423 /* Copy first part of the handler. */
1424 uasm_copy_handler(relocs
, labels
, tlb_handler
, split
, f
);
1425 f
+= split
- tlb_handler
;
1428 /* Insert branch. */
1429 uasm_l_split(&l
, final_handler
);
1430 uasm_il_b(&f
, &r
, label_split
);
1431 if (uasm_insn_has_bdelay(relocs
, split
))
1434 uasm_copy_handler(relocs
, labels
,
1435 split
, split
+ 1, f
);
1436 uasm_move_labels(labels
, f
, f
+ 1, -1);
1442 /* Copy the rest of the handler. */
1443 uasm_copy_handler(relocs
, labels
, split
, p
, final_handler
);
1444 final_len
= (f
- (final_handler
+ MIPS64_REFILL_INSNS
)) +
1447 #endif /* CONFIG_64BIT */
1449 uasm_resolve_relocs(relocs
, labels
);
1450 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1453 memcpy((void *)ebase
, final_handler
, 0x100);
1455 dump_handler("r4000_tlb_refill", (u32
*)ebase
, 64);
1458 extern u32 handle_tlbl
[], handle_tlbl_end
[];
1459 extern u32 handle_tlbs
[], handle_tlbs_end
[];
1460 extern u32 handle_tlbm
[], handle_tlbm_end
[];
1462 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1463 extern u32 tlbmiss_handler_setup_pgd
[], tlbmiss_handler_setup_pgd_end
[];
1465 static void __cpuinit
build_r4000_setup_pgd(void)
1469 u32
*p
= tlbmiss_handler_setup_pgd_array
;
1470 const int tlbmiss_handler_setup_pgd_size
=
1471 tlbmiss_handler_setup_pgd_end
- tlbmiss_handler_setup_pgd
;
1472 struct uasm_label
*l
= labels
;
1473 struct uasm_reloc
*r
= relocs
;
1475 memset(tlbmiss_handler_setup_pgd
, 0, tlbmiss_handler_setup_pgd_size
*
1476 sizeof(tlbmiss_handler_setup_pgd
[0]));
1477 memset(labels
, 0, sizeof(labels
));
1478 memset(relocs
, 0, sizeof(relocs
));
1480 pgd_reg
= allocate_kscratch();
1482 if (pgd_reg
== -1) {
1483 /* PGD << 11 in c0_Context */
1485 * If it is a ckseg0 address, convert to a physical
1486 * address. Shifting right by 29 and adding 4 will
1487 * result in zero for these addresses.
1490 UASM_i_SRA(&p
, a1
, a0
, 29);
1491 UASM_i_ADDIU(&p
, a1
, a1
, 4);
1492 uasm_il_bnez(&p
, &r
, a1
, label_tlbl_goaround1
);
1494 uasm_i_dinsm(&p
, a0
, 0, 29, 64 - 29);
1495 uasm_l_tlbl_goaround1(&l
, p
);
1496 UASM_i_SLL(&p
, a0
, a0
, 11);
1498 UASM_i_MTC0(&p
, a0
, C0_CONTEXT
);
1500 /* PGD in c0_KScratch */
1502 UASM_i_MTC0(&p
, a0
, c0_kscratch(), pgd_reg
);
1504 if (p
>= tlbmiss_handler_setup_pgd_end
)
1505 panic("tlbmiss_handler_setup_pgd space exceeded");
1507 uasm_resolve_relocs(relocs
, labels
);
1508 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1509 (unsigned int)(p
- tlbmiss_handler_setup_pgd
));
1511 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd
,
1512 tlbmiss_handler_setup_pgd_size
);
1516 static void __cpuinit
1517 iPTE_LW(u32
**p
, unsigned int pte
, unsigned int ptr
)
1520 # ifdef CONFIG_64BIT_PHYS_ADDR
1522 uasm_i_lld(p
, pte
, 0, ptr
);
1525 UASM_i_LL(p
, pte
, 0, ptr
);
1527 # ifdef CONFIG_64BIT_PHYS_ADDR
1529 uasm_i_ld(p
, pte
, 0, ptr
);
1532 UASM_i_LW(p
, pte
, 0, ptr
);
1536 static void __cpuinit
1537 iPTE_SW(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
, unsigned int ptr
,
1540 #ifdef CONFIG_64BIT_PHYS_ADDR
1541 unsigned int hwmode
= mode
& (_PAGE_VALID
| _PAGE_DIRTY
);
1544 uasm_i_ori(p
, pte
, pte
, mode
);
1546 # ifdef CONFIG_64BIT_PHYS_ADDR
1548 uasm_i_scd(p
, pte
, 0, ptr
);
1551 UASM_i_SC(p
, pte
, 0, ptr
);
1553 if (r10000_llsc_war())
1554 uasm_il_beqzl(p
, r
, pte
, label_smp_pgtable_change
);
1556 uasm_il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1558 # ifdef CONFIG_64BIT_PHYS_ADDR
1559 if (!cpu_has_64bits
) {
1560 /* no uasm_i_nop needed */
1561 uasm_i_ll(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1562 uasm_i_ori(p
, pte
, pte
, hwmode
);
1563 uasm_i_sc(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1564 uasm_il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1565 /* no uasm_i_nop needed */
1566 uasm_i_lw(p
, pte
, 0, ptr
);
1573 # ifdef CONFIG_64BIT_PHYS_ADDR
1575 uasm_i_sd(p
, pte
, 0, ptr
);
1578 UASM_i_SW(p
, pte
, 0, ptr
);
1580 # ifdef CONFIG_64BIT_PHYS_ADDR
1581 if (!cpu_has_64bits
) {
1582 uasm_i_lw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1583 uasm_i_ori(p
, pte
, pte
, hwmode
);
1584 uasm_i_sw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1585 uasm_i_lw(p
, pte
, 0, ptr
);
1592 * Check if PTE is present, if not then jump to LABEL. PTR points to
1593 * the page table where this PTE is located, PTE will be re-loaded
1594 * with it's original value.
1596 static void __cpuinit
1597 build_pte_present(u32
**p
, struct uasm_reloc
**r
,
1598 int pte
, int ptr
, int scratch
, enum label_id lid
)
1600 int t
= scratch
>= 0 ? scratch
: pte
;
1603 if (use_bbit_insns()) {
1604 uasm_il_bbit0(p
, r
, pte
, ilog2(_PAGE_PRESENT
), lid
);
1607 uasm_i_andi(p
, t
, pte
, _PAGE_PRESENT
);
1608 uasm_il_beqz(p
, r
, t
, lid
);
1610 /* You lose the SMP race :-(*/
1611 iPTE_LW(p
, pte
, ptr
);
1614 uasm_i_andi(p
, t
, pte
, _PAGE_PRESENT
| _PAGE_READ
);
1615 uasm_i_xori(p
, t
, t
, _PAGE_PRESENT
| _PAGE_READ
);
1616 uasm_il_bnez(p
, r
, t
, lid
);
1618 /* You lose the SMP race :-(*/
1619 iPTE_LW(p
, pte
, ptr
);
1623 /* Make PTE valid, store result in PTR. */
1624 static void __cpuinit
1625 build_make_valid(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
,
1628 unsigned int mode
= _PAGE_VALID
| _PAGE_ACCESSED
;
1630 iPTE_SW(p
, r
, pte
, ptr
, mode
);
1634 * Check if PTE can be written to, if not branch to LABEL. Regardless
1635 * restore PTE with value from PTR when done.
1637 static void __cpuinit
1638 build_pte_writable(u32
**p
, struct uasm_reloc
**r
,
1639 unsigned int pte
, unsigned int ptr
, int scratch
,
1642 int t
= scratch
>= 0 ? scratch
: pte
;
1644 uasm_i_andi(p
, t
, pte
, _PAGE_PRESENT
| _PAGE_WRITE
);
1645 uasm_i_xori(p
, t
, t
, _PAGE_PRESENT
| _PAGE_WRITE
);
1646 uasm_il_bnez(p
, r
, t
, lid
);
1648 /* You lose the SMP race :-(*/
1649 iPTE_LW(p
, pte
, ptr
);
1654 /* Make PTE writable, update software status bits as well, then store
1657 static void __cpuinit
1658 build_make_write(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
,
1661 unsigned int mode
= (_PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
1664 iPTE_SW(p
, r
, pte
, ptr
, mode
);
1668 * Check if PTE can be modified, if not branch to LABEL. Regardless
1669 * restore PTE with value from PTR when done.
1671 static void __cpuinit
1672 build_pte_modifiable(u32
**p
, struct uasm_reloc
**r
,
1673 unsigned int pte
, unsigned int ptr
, int scratch
,
1676 if (use_bbit_insns()) {
1677 uasm_il_bbit0(p
, r
, pte
, ilog2(_PAGE_WRITE
), lid
);
1680 int t
= scratch
>= 0 ? scratch
: pte
;
1681 uasm_i_andi(p
, t
, pte
, _PAGE_WRITE
);
1682 uasm_il_beqz(p
, r
, t
, lid
);
1684 /* You lose the SMP race :-(*/
1685 iPTE_LW(p
, pte
, ptr
);
1689 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1693 * R3000 style TLB load/store/modify handlers.
1697 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1700 static void __cpuinit
1701 build_r3000_pte_reload_tlbwi(u32
**p
, unsigned int pte
, unsigned int tmp
)
1703 uasm_i_mtc0(p
, pte
, C0_ENTRYLO0
); /* cp0 delay */
1704 uasm_i_mfc0(p
, tmp
, C0_EPC
); /* cp0 delay */
1707 uasm_i_rfe(p
); /* branch delay */
1711 * This places the pte into ENTRYLO0 and writes it with tlbwi
1712 * or tlbwr as appropriate. This is because the index register
1713 * may have the probe fail bit set as a result of a trap on a
1714 * kseg2 access, i.e. without refill. Then it returns.
1716 static void __cpuinit
1717 build_r3000_tlb_reload_write(u32
**p
, struct uasm_label
**l
,
1718 struct uasm_reloc
**r
, unsigned int pte
,
1721 uasm_i_mfc0(p
, tmp
, C0_INDEX
);
1722 uasm_i_mtc0(p
, pte
, C0_ENTRYLO0
); /* cp0 delay */
1723 uasm_il_bltz(p
, r
, tmp
, label_r3000_write_probe_fail
); /* cp0 delay */
1724 uasm_i_mfc0(p
, tmp
, C0_EPC
); /* branch delay */
1725 uasm_i_tlbwi(p
); /* cp0 delay */
1727 uasm_i_rfe(p
); /* branch delay */
1728 uasm_l_r3000_write_probe_fail(l
, *p
);
1729 uasm_i_tlbwr(p
); /* cp0 delay */
1731 uasm_i_rfe(p
); /* branch delay */
1734 static void __cpuinit
1735 build_r3000_tlbchange_handler_head(u32
**p
, unsigned int pte
,
1738 long pgdc
= (long)pgd_current
;
1740 uasm_i_mfc0(p
, pte
, C0_BADVADDR
);
1741 uasm_i_lui(p
, ptr
, uasm_rel_hi(pgdc
)); /* cp0 delay */
1742 uasm_i_lw(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
1743 uasm_i_srl(p
, pte
, pte
, 22); /* load delay */
1744 uasm_i_sll(p
, pte
, pte
, 2);
1745 uasm_i_addu(p
, ptr
, ptr
, pte
);
1746 uasm_i_mfc0(p
, pte
, C0_CONTEXT
);
1747 uasm_i_lw(p
, ptr
, 0, ptr
); /* cp0 delay */
1748 uasm_i_andi(p
, pte
, pte
, 0xffc); /* load delay */
1749 uasm_i_addu(p
, ptr
, ptr
, pte
);
1750 uasm_i_lw(p
, pte
, 0, ptr
);
1751 uasm_i_tlbp(p
); /* load delay */
1754 static void __cpuinit
build_r3000_tlb_load_handler(void)
1756 u32
*p
= handle_tlbl
;
1757 const int handle_tlbl_size
= handle_tlbl_end
- handle_tlbl
;
1758 struct uasm_label
*l
= labels
;
1759 struct uasm_reloc
*r
= relocs
;
1761 memset(handle_tlbl
, 0, handle_tlbl_size
* sizeof(handle_tlbl
[0]));
1762 memset(labels
, 0, sizeof(labels
));
1763 memset(relocs
, 0, sizeof(relocs
));
1765 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1766 build_pte_present(&p
, &r
, K0
, K1
, -1, label_nopage_tlbl
);
1767 uasm_i_nop(&p
); /* load delay */
1768 build_make_valid(&p
, &r
, K0
, K1
);
1769 build_r3000_tlb_reload_write(&p
, &l
, &r
, K0
, K1
);
1771 uasm_l_nopage_tlbl(&l
, p
);
1772 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
1775 if (p
>= handle_tlbl_end
)
1776 panic("TLB load handler fastpath space exceeded");
1778 uasm_resolve_relocs(relocs
, labels
);
1779 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1780 (unsigned int)(p
- handle_tlbl
));
1782 dump_handler("r3000_tlb_load", handle_tlbl
, handle_tlbl_size
);
1785 static void __cpuinit
build_r3000_tlb_store_handler(void)
1787 u32
*p
= handle_tlbs
;
1788 const int handle_tlbs_size
= handle_tlbs_end
- handle_tlbs
;
1789 struct uasm_label
*l
= labels
;
1790 struct uasm_reloc
*r
= relocs
;
1792 memset(handle_tlbs
, 0, handle_tlbs_size
* sizeof(handle_tlbs
[0]));
1793 memset(labels
, 0, sizeof(labels
));
1794 memset(relocs
, 0, sizeof(relocs
));
1796 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1797 build_pte_writable(&p
, &r
, K0
, K1
, -1, label_nopage_tlbs
);
1798 uasm_i_nop(&p
); /* load delay */
1799 build_make_write(&p
, &r
, K0
, K1
);
1800 build_r3000_tlb_reload_write(&p
, &l
, &r
, K0
, K1
);
1802 uasm_l_nopage_tlbs(&l
, p
);
1803 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1806 if (p
>= handle_tlbs
)
1807 panic("TLB store handler fastpath space exceeded");
1809 uasm_resolve_relocs(relocs
, labels
);
1810 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1811 (unsigned int)(p
- handle_tlbs
));
1813 dump_handler("r3000_tlb_store", handle_tlbs
, handle_tlbs_size
);
1816 static void __cpuinit
build_r3000_tlb_modify_handler(void)
1818 u32
*p
= handle_tlbm
;
1819 const int handle_tlbm_size
= handle_tlbm_end
- handle_tlbm
;
1820 struct uasm_label
*l
= labels
;
1821 struct uasm_reloc
*r
= relocs
;
1823 memset(handle_tlbm
, 0, handle_tlbm_size
* sizeof(handle_tlbm
[0]));
1824 memset(labels
, 0, sizeof(labels
));
1825 memset(relocs
, 0, sizeof(relocs
));
1827 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1828 build_pte_modifiable(&p
, &r
, K0
, K1
, -1, label_nopage_tlbm
);
1829 uasm_i_nop(&p
); /* load delay */
1830 build_make_write(&p
, &r
, K0
, K1
);
1831 build_r3000_pte_reload_tlbwi(&p
, K0
, K1
);
1833 uasm_l_nopage_tlbm(&l
, p
);
1834 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1837 if (p
>= handle_tlbm_end
)
1838 panic("TLB modify handler fastpath space exceeded");
1840 uasm_resolve_relocs(relocs
, labels
);
1841 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1842 (unsigned int)(p
- handle_tlbm
));
1844 dump_handler("r3000_tlb_modify", handle_tlbm
, handle_tlbm_size
);
1846 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1849 * R4000 style TLB load/store/modify handlers.
1851 static struct work_registers __cpuinit
1852 build_r4000_tlbchange_handler_head(u32
**p
, struct uasm_label
**l
,
1853 struct uasm_reloc
**r
)
1855 struct work_registers wr
= build_get_work_registers(p
);
1858 build_get_pmde64(p
, l
, r
, wr
.r1
, wr
.r2
); /* get pmd in ptr */
1860 build_get_pgde32(p
, wr
.r1
, wr
.r2
); /* get pgd in ptr */
1863 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1865 * For huge tlb entries, pmd doesn't contain an address but
1866 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1867 * see if we need to jump to huge tlb processing.
1869 build_is_huge_pte(p
, r
, wr
.r1
, wr
.r2
, label_tlb_huge_update
);
1872 UASM_i_MFC0(p
, wr
.r1
, C0_BADVADDR
);
1873 UASM_i_LW(p
, wr
.r2
, 0, wr
.r2
);
1874 UASM_i_SRL(p
, wr
.r1
, wr
.r1
, PAGE_SHIFT
+ PTE_ORDER
- PTE_T_LOG2
);
1875 uasm_i_andi(p
, wr
.r1
, wr
.r1
, (PTRS_PER_PTE
- 1) << PTE_T_LOG2
);
1876 UASM_i_ADDU(p
, wr
.r2
, wr
.r2
, wr
.r1
);
1879 uasm_l_smp_pgtable_change(l
, *p
);
1881 iPTE_LW(p
, wr
.r1
, wr
.r2
); /* get even pte */
1882 if (!m4kc_tlbp_war())
1883 build_tlb_probe_entry(p
);
1887 static void __cpuinit
1888 build_r4000_tlbchange_handler_tail(u32
**p
, struct uasm_label
**l
,
1889 struct uasm_reloc
**r
, unsigned int tmp
,
1892 uasm_i_ori(p
, ptr
, ptr
, sizeof(pte_t
));
1893 uasm_i_xori(p
, ptr
, ptr
, sizeof(pte_t
));
1894 build_update_entries(p
, tmp
, ptr
);
1895 build_tlb_write_entry(p
, l
, r
, tlb_indexed
);
1896 uasm_l_leave(l
, *p
);
1897 build_restore_work_registers(p
);
1898 uasm_i_eret(p
); /* return from trap */
1901 build_get_pgd_vmalloc64(p
, l
, r
, tmp
, ptr
, not_refill
);
1905 static void __cpuinit
build_r4000_tlb_load_handler(void)
1907 u32
*p
= handle_tlbl
;
1908 const int handle_tlbl_size
= handle_tlbl_end
- handle_tlbl
;
1909 struct uasm_label
*l
= labels
;
1910 struct uasm_reloc
*r
= relocs
;
1911 struct work_registers wr
;
1913 memset(handle_tlbl
, 0, handle_tlbl_size
* sizeof(handle_tlbl
[0]));
1914 memset(labels
, 0, sizeof(labels
));
1915 memset(relocs
, 0, sizeof(relocs
));
1917 if (bcm1250_m3_war()) {
1918 unsigned int segbits
= 44;
1920 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
1921 uasm_i_dmfc0(&p
, K1
, C0_ENTRYHI
);
1922 uasm_i_xor(&p
, K0
, K0
, K1
);
1923 uasm_i_dsrl_safe(&p
, K1
, K0
, 62);
1924 uasm_i_dsrl_safe(&p
, K0
, K0
, 12 + 1);
1925 uasm_i_dsll_safe(&p
, K0
, K0
, 64 + 12 + 1 - segbits
);
1926 uasm_i_or(&p
, K0
, K0
, K1
);
1927 uasm_il_bnez(&p
, &r
, K0
, label_leave
);
1928 /* No need for uasm_i_nop */
1931 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
1932 build_pte_present(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbl
);
1933 if (m4kc_tlbp_war())
1934 build_tlb_probe_entry(&p
);
1938 * If the page is not _PAGE_VALID, RI or XI could not
1939 * have triggered it. Skip the expensive test..
1941 if (use_bbit_insns()) {
1942 uasm_il_bbit0(&p
, &r
, wr
.r1
, ilog2(_PAGE_VALID
),
1943 label_tlbl_goaround1
);
1945 uasm_i_andi(&p
, wr
.r3
, wr
.r1
, _PAGE_VALID
);
1946 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround1
);
1952 switch (current_cpu_type()) {
1954 if (cpu_has_mips_r2
) {
1957 case CPU_CAVIUM_OCTEON
:
1958 case CPU_CAVIUM_OCTEON_PLUS
:
1959 case CPU_CAVIUM_OCTEON2
:
1964 /* Examine entrylo 0 or 1 based on ptr. */
1965 if (use_bbit_insns()) {
1966 uasm_i_bbit0(&p
, wr
.r2
, ilog2(sizeof(pte_t
)), 8);
1968 uasm_i_andi(&p
, wr
.r3
, wr
.r2
, sizeof(pte_t
));
1969 uasm_i_beqz(&p
, wr
.r3
, 8);
1971 /* load it in the delay slot*/
1972 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO0
);
1973 /* load it if ptr is odd */
1974 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO1
);
1976 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1977 * XI must have triggered it.
1979 if (use_bbit_insns()) {
1980 uasm_il_bbit1(&p
, &r
, wr
.r3
, 1, label_nopage_tlbl
);
1982 uasm_l_tlbl_goaround1(&l
, p
);
1984 uasm_i_andi(&p
, wr
.r3
, wr
.r3
, 2);
1985 uasm_il_bnez(&p
, &r
, wr
.r3
, label_nopage_tlbl
);
1988 uasm_l_tlbl_goaround1(&l
, p
);
1990 build_make_valid(&p
, &r
, wr
.r1
, wr
.r2
);
1991 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
1993 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1995 * This is the entry point when build_r4000_tlbchange_handler_head
1996 * spots a huge page.
1998 uasm_l_tlb_huge_update(&l
, p
);
1999 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2000 build_pte_present(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbl
);
2001 build_tlb_probe_entry(&p
);
2005 * If the page is not _PAGE_VALID, RI or XI could not
2006 * have triggered it. Skip the expensive test..
2008 if (use_bbit_insns()) {
2009 uasm_il_bbit0(&p
, &r
, wr
.r1
, ilog2(_PAGE_VALID
),
2010 label_tlbl_goaround2
);
2012 uasm_i_andi(&p
, wr
.r3
, wr
.r1
, _PAGE_VALID
);
2013 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround2
);
2019 switch (current_cpu_type()) {
2021 if (cpu_has_mips_r2
) {
2024 case CPU_CAVIUM_OCTEON
:
2025 case CPU_CAVIUM_OCTEON_PLUS
:
2026 case CPU_CAVIUM_OCTEON2
:
2031 /* Examine entrylo 0 or 1 based on ptr. */
2032 if (use_bbit_insns()) {
2033 uasm_i_bbit0(&p
, wr
.r2
, ilog2(sizeof(pte_t
)), 8);
2035 uasm_i_andi(&p
, wr
.r3
, wr
.r2
, sizeof(pte_t
));
2036 uasm_i_beqz(&p
, wr
.r3
, 8);
2038 /* load it in the delay slot*/
2039 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO0
);
2040 /* load it if ptr is odd */
2041 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO1
);
2043 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2044 * XI must have triggered it.
2046 if (use_bbit_insns()) {
2047 uasm_il_bbit0(&p
, &r
, wr
.r3
, 1, label_tlbl_goaround2
);
2049 uasm_i_andi(&p
, wr
.r3
, wr
.r3
, 2);
2050 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround2
);
2052 if (PM_DEFAULT_MASK
== 0)
2055 * We clobbered C0_PAGEMASK, restore it. On the other branch
2056 * it is restored in build_huge_tlb_write_entry.
2058 build_restore_pagemask(&p
, &r
, wr
.r3
, label_nopage_tlbl
, 0);
2060 uasm_l_tlbl_goaround2(&l
, p
);
2062 uasm_i_ori(&p
, wr
.r1
, wr
.r1
, (_PAGE_ACCESSED
| _PAGE_VALID
));
2063 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
);
2066 uasm_l_nopage_tlbl(&l
, p
);
2067 build_restore_work_registers(&p
);
2068 #ifdef CONFIG_CPU_MICROMIPS
2069 if ((unsigned long)tlb_do_page_fault_0
& 1) {
2070 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_0
));
2071 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_0
));
2075 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
2078 if (p
>= handle_tlbl_end
)
2079 panic("TLB load handler fastpath space exceeded");
2081 uasm_resolve_relocs(relocs
, labels
);
2082 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2083 (unsigned int)(p
- handle_tlbl
));
2085 dump_handler("r4000_tlb_load", handle_tlbl
, handle_tlbl_size
);
2088 static void __cpuinit
build_r4000_tlb_store_handler(void)
2090 u32
*p
= handle_tlbs
;
2091 const int handle_tlbs_size
= handle_tlbs_end
- handle_tlbs
;
2092 struct uasm_label
*l
= labels
;
2093 struct uasm_reloc
*r
= relocs
;
2094 struct work_registers wr
;
2096 memset(handle_tlbs
, 0, handle_tlbs_size
* sizeof(handle_tlbs
[0]));
2097 memset(labels
, 0, sizeof(labels
));
2098 memset(relocs
, 0, sizeof(relocs
));
2100 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2101 build_pte_writable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbs
);
2102 if (m4kc_tlbp_war())
2103 build_tlb_probe_entry(&p
);
2104 build_make_write(&p
, &r
, wr
.r1
, wr
.r2
);
2105 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2107 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2109 * This is the entry point when
2110 * build_r4000_tlbchange_handler_head spots a huge page.
2112 uasm_l_tlb_huge_update(&l
, p
);
2113 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2114 build_pte_writable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbs
);
2115 build_tlb_probe_entry(&p
);
2116 uasm_i_ori(&p
, wr
.r1
, wr
.r1
,
2117 _PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
| _PAGE_DIRTY
);
2118 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
);
2121 uasm_l_nopage_tlbs(&l
, p
);
2122 build_restore_work_registers(&p
);
2123 #ifdef CONFIG_CPU_MICROMIPS
2124 if ((unsigned long)tlb_do_page_fault_1
& 1) {
2125 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_1
));
2126 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_1
));
2130 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2133 if (p
>= handle_tlbs_end
)
2134 panic("TLB store handler fastpath space exceeded");
2136 uasm_resolve_relocs(relocs
, labels
);
2137 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2138 (unsigned int)(p
- handle_tlbs
));
2140 dump_handler("r4000_tlb_store", handle_tlbs
, handle_tlbs_size
);
2143 static void __cpuinit
build_r4000_tlb_modify_handler(void)
2145 u32
*p
= handle_tlbm
;
2146 const int handle_tlbm_size
= handle_tlbm_end
- handle_tlbm
;
2147 struct uasm_label
*l
= labels
;
2148 struct uasm_reloc
*r
= relocs
;
2149 struct work_registers wr
;
2151 memset(handle_tlbm
, 0, handle_tlbm_size
* sizeof(handle_tlbm
[0]));
2152 memset(labels
, 0, sizeof(labels
));
2153 memset(relocs
, 0, sizeof(relocs
));
2155 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2156 build_pte_modifiable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbm
);
2157 if (m4kc_tlbp_war())
2158 build_tlb_probe_entry(&p
);
2159 /* Present and writable bits set, set accessed and dirty bits. */
2160 build_make_write(&p
, &r
, wr
.r1
, wr
.r2
);
2161 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2163 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2165 * This is the entry point when
2166 * build_r4000_tlbchange_handler_head spots a huge page.
2168 uasm_l_tlb_huge_update(&l
, p
);
2169 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2170 build_pte_modifiable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbm
);
2171 build_tlb_probe_entry(&p
);
2172 uasm_i_ori(&p
, wr
.r1
, wr
.r1
,
2173 _PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
| _PAGE_DIRTY
);
2174 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
);
2177 uasm_l_nopage_tlbm(&l
, p
);
2178 build_restore_work_registers(&p
);
2179 #ifdef CONFIG_CPU_MICROMIPS
2180 if ((unsigned long)tlb_do_page_fault_1
& 1) {
2181 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_1
));
2182 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_1
));
2186 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2189 if (p
>= handle_tlbm_end
)
2190 panic("TLB modify handler fastpath space exceeded");
2192 uasm_resolve_relocs(relocs
, labels
);
2193 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2194 (unsigned int)(p
- handle_tlbm
));
2196 dump_handler("r4000_tlb_modify", handle_tlbm
, handle_tlbm_size
);
2199 static void __cpuinit
flush_tlb_handlers(void)
2201 local_flush_icache_range((unsigned long)handle_tlbl
,
2202 (unsigned long)handle_tlbl_end
);
2203 local_flush_icache_range((unsigned long)handle_tlbs
,
2204 (unsigned long)handle_tlbs_end
);
2205 local_flush_icache_range((unsigned long)handle_tlbm
,
2206 (unsigned long)handle_tlbm_end
);
2207 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2208 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd
,
2209 (unsigned long)tlbmiss_handler_setup_pgd_end
);
2213 void __cpuinit
build_tlb_refill_handler(void)
2216 * The refill handler is generated per-CPU, multi-node systems
2217 * may have local storage for it. The other handlers are only
2220 static int run_once
= 0;
2222 output_pgtable_bits_defines();
2225 check_for_high_segbits
= current_cpu_data
.vmbits
> (PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
2228 switch (current_cpu_type()) {
2236 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2237 if (cpu_has_local_ebase
)
2238 build_r3000_tlb_refill_handler();
2240 if (!cpu_has_local_ebase
)
2241 build_r3000_tlb_refill_handler();
2242 build_r3000_tlb_load_handler();
2243 build_r3000_tlb_store_handler();
2244 build_r3000_tlb_modify_handler();
2245 flush_tlb_handlers();
2249 panic("No R3000 TLB refill handler");
2255 panic("No R6000 TLB refill handler yet");
2259 panic("No R8000 TLB refill handler yet");
2264 scratch_reg
= allocate_kscratch();
2265 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2266 build_r4000_setup_pgd();
2268 build_r4000_tlb_load_handler();
2269 build_r4000_tlb_store_handler();
2270 build_r4000_tlb_modify_handler();
2271 if (!cpu_has_local_ebase
)
2272 build_r4000_tlb_refill_handler();
2273 flush_tlb_handlers();
2276 if (cpu_has_local_ebase
)
2277 build_r4000_tlb_refill_handler();