Merge branch 'next/kvm' into mips-for-linux-next
[deliverable/linux.git] / arch / mips / mti-malta / malta-time.c
1 /*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20 #include <linux/types.h>
21 #include <linux/i8253.h>
22 #include <linux/init.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/sched.h>
25 #include <linux/spinlock.h>
26 #include <linux/interrupt.h>
27 #include <linux/timex.h>
28 #include <linux/mc146818rtc.h>
29
30 #include <asm/mipsregs.h>
31 #include <asm/mipsmtregs.h>
32 #include <asm/hardirq.h>
33 #include <asm/irq.h>
34 #include <asm/div64.h>
35 #include <asm/setup.h>
36 #include <asm/time.h>
37 #include <asm/mc146818-time.h>
38 #include <asm/msc01_ic.h>
39 #include <asm/gic.h>
40
41 #include <asm/mips-boards/generic.h>
42 #include <asm/mips-boards/prom.h>
43
44 #include <asm/mips-boards/maltaint.h>
45
46 unsigned long cpu_khz;
47 int gic_frequency;
48
49 static int mips_cpu_timer_irq;
50 static int mips_cpu_perf_irq;
51 extern int cp0_perfcount_irq;
52
53 static void mips_timer_dispatch(void)
54 {
55 do_IRQ(mips_cpu_timer_irq);
56 }
57
58 static void mips_perf_dispatch(void)
59 {
60 do_IRQ(mips_cpu_perf_irq);
61 }
62
63 static unsigned int freqround(unsigned int freq, unsigned int amount)
64 {
65 freq += amount;
66 freq -= freq % (amount*2);
67 return freq;
68 }
69
70 /*
71 * Estimate CPU and GIC frequencies.
72 */
73 static void __init estimate_frequencies(void)
74 {
75 unsigned long flags;
76 unsigned int count, start;
77 unsigned int giccount = 0, gicstart = 0;
78
79 #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
80 unsigned int prid = read_c0_prid() & 0xffff00;
81
82 /*
83 * XXXKYMA: hardwire the CPU frequency to Host Freq/4
84 */
85 count = (CONFIG_KVM_HOST_FREQ * 1000000) >> 3;
86 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
87 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
88 count *= 2;
89
90 mips_hpt_frequency = count;
91 return;
92 #endif
93
94 local_irq_save(flags);
95
96 /* Start counter exactly on falling edge of update flag. */
97 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
98 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
99
100 /* Initialize counters. */
101 start = read_c0_count();
102 if (gic_present)
103 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
104
105 /* Read counter exactly on falling edge of update flag. */
106 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
107 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
108
109 count = read_c0_count();
110 if (gic_present)
111 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
112
113 local_irq_restore(flags);
114
115 count -= start;
116 if (gic_present)
117 giccount -= gicstart;
118
119 mips_hpt_frequency = count;
120 if (gic_present)
121 gic_frequency = giccount;
122 }
123
124 void read_persistent_clock(struct timespec *ts)
125 {
126 ts->tv_sec = mc146818_get_cmos_time();
127 ts->tv_nsec = 0;
128 }
129
130 static void __init plat_perf_setup(void)
131 {
132 #ifdef MSC01E_INT_BASE
133 if (cpu_has_veic) {
134 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
135 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
136 } else
137 #endif
138 if (cp0_perfcount_irq >= 0) {
139 if (cpu_has_vint)
140 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
141 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
142 #ifdef CONFIG_SMP
143 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
144 #endif
145 }
146 }
147
148 unsigned int __cpuinit get_c0_compare_int(void)
149 {
150 #ifdef MSC01E_INT_BASE
151 if (cpu_has_veic) {
152 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
153 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
154 } else
155 #endif
156 {
157 if (cpu_has_vint)
158 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
159 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
160 }
161
162 return mips_cpu_timer_irq;
163 }
164
165 void __init plat_time_init(void)
166 {
167 unsigned int prid = read_c0_prid() & 0xffff00;
168 unsigned int freq;
169
170 estimate_frequencies();
171
172 freq = mips_hpt_frequency;
173 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
174 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
175 freq *= 2;
176 freq = freqround(freq, 5000);
177 pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
178 (freq%1000000)*100/1000000);
179 cpu_khz = freq / 1000;
180
181 if (gic_present) {
182 freq = freqround(gic_frequency, 5000);
183 pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
184 (freq%1000000)*100/1000000);
185 gic_clocksource_init(gic_frequency);
186 } else
187 init_r4k_clocksource();
188
189 #ifdef CONFIG_I8253
190 /* Only Malta has a PIT. */
191 setup_pit_timer();
192 #endif
193
194 mips_scroll_message();
195
196 plat_perf_setup();
197 }
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