3b32c834d14cfa141894df3313fe2f8260a82145
[deliverable/linux.git] / arch / mips / netlogic / common / smp.c
1 /*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/init.h>
38 #include <linux/smp.h>
39 #include <linux/irq.h>
40
41 #include <asm/mmu_context.h>
42
43 #include <asm/netlogic/interrupt.h>
44 #include <asm/netlogic/mips-extns.h>
45 #include <asm/netlogic/haldefs.h>
46 #include <asm/netlogic/common.h>
47
48 #include <asm/netlogic/xlr/iomap.h>
49 #include <asm/netlogic/xlr/pic.h>
50
51 void nlm_send_ipi_single(int logical_cpu, unsigned int action)
52 {
53 int cpu = cpu_logical_map(logical_cpu);
54
55 if (action & SMP_CALL_FUNCTION)
56 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
57 if (action & SMP_RESCHEDULE_YOURSELF)
58 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
59 }
60
61 void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
62 {
63 int cpu;
64
65 for_each_cpu(cpu, mask) {
66 nlm_send_ipi_single(cpu, action);
67 }
68 }
69
70 /* IRQ_IPI_SMP_FUNCTION Handler */
71 void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
72 {
73 smp_call_function_interrupt();
74 write_c0_eirr(1ull << irq);
75 }
76
77 /* IRQ_IPI_SMP_RESCHEDULE handler */
78 void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
79 {
80 scheduler_ipi();
81 write_c0_eirr(1ull << irq);
82 }
83
84 /*
85 * Called before going into mips code, early cpu init
86 */
87 void nlm_early_init_secondary(int cpu)
88 {
89 write_c0_ebase((uint32_t)nlm_common_ebase);
90 #ifdef NLM_XLP
91 if (cpu % 4 == 0)
92 xlp_mmu_init();
93 #endif
94 }
95
96 /*
97 * Code to run on secondary just after probing the CPU
98 */
99 static void __cpuinit nlm_init_secondary(void)
100 {
101 nlm_smp_irq_init();
102 }
103
104 void nlm_smp_finish(void)
105 {
106 #ifdef notyet
107 nlm_common_msgring_cpu_init();
108 #endif
109 local_irq_enable();
110 }
111
112 void nlm_cpus_done(void)
113 {
114 }
115
116 /*
117 * Boot all other cpus in the system, initialize them, and bring them into
118 * the boot function
119 */
120 int nlm_cpu_unblock[NR_CPUS];
121 int nlm_cpu_ready[NR_CPUS];
122 unsigned long nlm_next_gp;
123 unsigned long nlm_next_sp;
124 cpumask_t phys_cpu_present_map;
125
126 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
127 {
128 unsigned long gp = (unsigned long)task_thread_info(idle);
129 unsigned long sp = (unsigned long)__KSTK_TOS(idle);
130 int cpu = cpu_logical_map(logical_cpu);
131
132 nlm_next_sp = sp;
133 nlm_next_gp = gp;
134
135 /* barrier */
136 __sync();
137 nlm_cpu_unblock[cpu] = 1;
138 }
139
140 void __init nlm_smp_setup(void)
141 {
142 unsigned int boot_cpu;
143 int num_cpus, i;
144
145 boot_cpu = hard_smp_processor_id();
146 cpus_clear(phys_cpu_present_map);
147
148 cpu_set(boot_cpu, phys_cpu_present_map);
149 __cpu_number_map[boot_cpu] = 0;
150 __cpu_logical_map[0] = boot_cpu;
151 cpu_set(0, cpu_possible_map);
152
153 num_cpus = 1;
154 for (i = 0; i < NR_CPUS; i++) {
155 /*
156 * nlm_cpu_ready array is not set for the boot_cpu,
157 * it is only set for ASPs (see smpboot.S)
158 */
159 if (nlm_cpu_ready[i]) {
160 cpu_set(i, phys_cpu_present_map);
161 __cpu_number_map[i] = num_cpus;
162 __cpu_logical_map[num_cpus] = i;
163 cpu_set(num_cpus, cpu_possible_map);
164 ++num_cpus;
165 }
166 }
167
168 pr_info("Phys CPU present map: %lx, possible map %lx\n",
169 (unsigned long)phys_cpu_present_map.bits[0],
170 (unsigned long)cpu_possible_map.bits[0]);
171
172 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
173 }
174
175 void nlm_prepare_cpus(unsigned int max_cpus)
176 {
177 }
178
179 struct plat_smp_ops nlm_smp_ops = {
180 .send_ipi_single = nlm_send_ipi_single,
181 .send_ipi_mask = nlm_send_ipi_mask,
182 .init_secondary = nlm_init_secondary,
183 .smp_finish = nlm_smp_finish,
184 .cpus_done = nlm_cpus_done,
185 .boot_secondary = nlm_boot_secondary,
186 .smp_setup = nlm_smp_setup,
187 .prepare_cpus = nlm_prepare_cpus,
188 };
This page took 0.038759 seconds and 4 git commands to generate.