arch/mips/pci/fixup-cobalt.c

   1 /*
   2  * Cobalt Qube/Raq PCI support
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
   9  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
  10  */
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15
  16 #include <asm/pci.h>
  17 #include <asm/io.h>
  18 #include <asm/gt64120.h>
  19
  20 #include <asm/cobalt/cobalt.h>
  21
  22 extern int cobalt_board_id;
  23
  24 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
  25 {
  26         unsigned short cfgword;
  27         unsigned char lt;
  28
  29         /* Enable Bus Mastering and fast back to back. */
  30         pci_read_config_word(dev, PCI_COMMAND, &cfgword);
  31         cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
  32         pci_write_config_word(dev, PCI_COMMAND, cfgword);
  33
  34         /* Enable both ide interfaces. ROM only enables primary one.  */
  35         pci_write_config_byte(dev, 0x40, 0xb);
  36
  37         /* Set latency timer to reasonable value. */
  38         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
  39         if (lt < 64)
  40                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
  41         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
  42 }
  43
  44 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
  45          qube_raq_via_bmIDE_fixup);
  46
  47 static void qube_raq_galileo_fixup(struct pci_dev *dev)
  48 {
  49         unsigned short galileo_id;
  50
  51         /* Fix PCI latency-timer and cache-line-size values in Galileo
  52          * host bridge.
  53          */
  54         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
  55         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
  56
  57         /*
  58          * On all machines prior to Q2, we had the STOP line disconnected
  59          * from Galileo to VIA on PCI.  The new Galileo does not function
  60          * correctly unless we have it connected.
  61          *
  62          * Therefore we must set the disconnect/retry cycle values to
  63          * something sensible when using the new Galileo.
  64          */
  65         pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
  66         galileo_id &= 0xff;     /* mask off class info */
  67         if (galileo_id >= 0x10) {
  68                 /* New Galileo, assumes PCI stop line to VIA is connected. */
  69                 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
  70         } else if (galileo_id == 0x1 || galileo_id == 0x2) {
  71                 signed int timeo;
  72                 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
  73                 timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
  74                 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
  75                 GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
  76         }
  77 }
  78
  79 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID,
  80          qube_raq_galileo_fixup);
  81
  82 static char irq_tab_cobalt[] __initdata = {
  83   [COBALT_PCICONF_CPU]     = 0,
  84   [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
  85   [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
  86   [COBALT_PCICONF_VIA]     = 0,
  87   [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
  88   [COBALT_PCICONF_ETH1]    = COBALT_ETH1_IRQ
  89 };
  90
  91 static char irq_tab_raq2[] __initdata = {
  92   [COBALT_PCICONF_CPU]     = 0,
  93   [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
  94   [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ,
  95   [COBALT_PCICONF_VIA]     = 0,
  96   [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
  97   [COBALT_PCICONF_ETH1]    = COBALT_ETH1_IRQ
  98 };
  99
 100 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 101 {
 102         if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
 103                 return irq_tab_raq2[slot];
 104
 105         return irq_tab_cobalt[slot];
 106 }
 107
 108 /* Do platform specific device initialization at pci_enable_device() time */
 109 int pcibios_plat_dev_init(struct pci_dev *dev)
 110 {
 111         return 0;
 112 }