2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
4 * Based on linux/arch/mips/pci/ops-tx4938.c,
5 * linux/arch/mips/pci/fixup-rbtx4938.c,
6 * linux/arch/mips/txx9/rbtx4938/setup.c,
7 * and RBTX49xx patch from CELF patch archive.
9 * 2003-2005 (c) MontaVista Software, Inc.
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 #include <linux/kernel.h>
19 #include <asm/txx9/tx4927pcic.h>
22 struct pci_controller
*channel
;
23 struct tx4927_pcic_reg __iomem
*pcicptr
;
24 } pcicptrs
[2]; /* TX4938 has 2 pcic */
26 static void __init
set_tx4927_pcicptr(struct pci_controller
*channel
,
27 struct tx4927_pcic_reg __iomem
*pcicptr
)
31 for (i
= 0; i
< ARRAY_SIZE(pcicptrs
); i
++) {
32 if (pcicptrs
[i
].channel
== channel
) {
33 pcicptrs
[i
].pcicptr
= pcicptr
;
37 for (i
= 0; i
< ARRAY_SIZE(pcicptrs
); i
++) {
38 if (!pcicptrs
[i
].channel
) {
39 pcicptrs
[i
].channel
= channel
;
40 pcicptrs
[i
].pcicptr
= pcicptr
;
47 struct tx4927_pcic_reg __iomem
*get_tx4927_pcicptr(
48 struct pci_controller
*channel
)
52 for (i
= 0; i
< ARRAY_SIZE(pcicptrs
); i
++) {
53 if (pcicptrs
[i
].channel
== channel
)
54 return pcicptrs
[i
].pcicptr
;
59 static int mkaddr(struct pci_bus
*bus
, unsigned int devfn
, int where
,
60 struct tx4927_pcic_reg __iomem
*pcicptr
)
62 if (bus
->parent
== NULL
&&
63 devfn
>= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU
, 0))
65 __raw_writel(((bus
->number
& 0xff) << 0x10)
66 | ((devfn
& 0xff) << 0x08) | (where
& 0xfc)
67 | (bus
->parent
? 1 : 0),
68 &pcicptr
->g2pcfgadrs
);
69 /* clear M_ABORT and Disable M_ABORT Int. */
70 __raw_writel((__raw_readl(&pcicptr
->pcistatus
) & 0x0000ffff)
71 | (PCI_STATUS_REC_MASTER_ABORT
<< 16),
76 static int check_abort(struct tx4927_pcic_reg __iomem
*pcicptr
)
78 int code
= PCIBIOS_SUCCESSFUL
;
80 /* wait write cycle completion before checking error status */
81 while (__raw_readl(&pcicptr
->pcicstatus
) & TX4927_PCIC_PCICSTATUS_IWB
)
83 if (__raw_readl(&pcicptr
->pcistatus
)
84 & (PCI_STATUS_REC_MASTER_ABORT
<< 16)) {
85 __raw_writel((__raw_readl(&pcicptr
->pcistatus
) & 0x0000ffff)
86 | (PCI_STATUS_REC_MASTER_ABORT
<< 16),
88 /* flush write buffer */
90 code
= PCIBIOS_DEVICE_NOT_FOUND
;
95 static u8
icd_readb(int offset
, struct tx4927_pcic_reg __iomem
*pcicptr
)
100 return __raw_readb((void __iomem
*)&pcicptr
->g2pcfgdata
+ offset
);
102 static u16
icd_readw(int offset
, struct tx4927_pcic_reg __iomem
*pcicptr
)
107 return __raw_readw((void __iomem
*)&pcicptr
->g2pcfgdata
+ offset
);
109 static u32
icd_readl(struct tx4927_pcic_reg __iomem
*pcicptr
)
111 return __raw_readl(&pcicptr
->g2pcfgdata
);
113 static void icd_writeb(u8 val
, int offset
,
114 struct tx4927_pcic_reg __iomem
*pcicptr
)
119 __raw_writeb(val
, (void __iomem
*)&pcicptr
->g2pcfgdata
+ offset
);
121 static void icd_writew(u16 val
, int offset
,
122 struct tx4927_pcic_reg __iomem
*pcicptr
)
127 __raw_writew(val
, (void __iomem
*)&pcicptr
->g2pcfgdata
+ offset
);
129 static void icd_writel(u32 val
, struct tx4927_pcic_reg __iomem
*pcicptr
)
131 __raw_writel(val
, &pcicptr
->g2pcfgdata
);
134 static struct tx4927_pcic_reg __iomem
*pci_bus_to_pcicptr(struct pci_bus
*bus
)
136 struct pci_controller
*channel
= bus
->sysdata
;
137 return get_tx4927_pcicptr(channel
);
140 static int tx4927_pci_config_read(struct pci_bus
*bus
, unsigned int devfn
,
141 int where
, int size
, u32
*val
)
143 struct tx4927_pcic_reg __iomem
*pcicptr
= pci_bus_to_pcicptr(bus
);
145 if (mkaddr(bus
, devfn
, where
, pcicptr
)) {
151 *val
= icd_readb(where
& 3, pcicptr
);
154 *val
= icd_readw(where
& 3, pcicptr
);
157 *val
= icd_readl(pcicptr
);
159 return check_abort(pcicptr
);
162 static int tx4927_pci_config_write(struct pci_bus
*bus
, unsigned int devfn
,
163 int where
, int size
, u32 val
)
165 struct tx4927_pcic_reg __iomem
*pcicptr
= pci_bus_to_pcicptr(bus
);
167 if (mkaddr(bus
, devfn
, where
, pcicptr
))
171 icd_writeb(val
, where
& 3, pcicptr
);
174 icd_writew(val
, where
& 3, pcicptr
);
177 icd_writel(val
, pcicptr
);
179 return check_abort(pcicptr
);
182 static struct pci_ops tx4927_pci_ops
= {
183 .read
= tx4927_pci_config_read
,
184 .write
= tx4927_pci_config_write
,
191 } tx4927_pci_opts __devinitdata
= {
194 .gbwc
= 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
197 void __init
tx4927_pcic_setup(struct tx4927_pcic_reg __iomem
*pcicptr
,
198 struct pci_controller
*channel
, int extarb
)
203 set_tx4927_pcicptr(channel
, pcicptr
);
205 if (!channel
->pci_ops
)
207 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
208 __raw_readl(&pcicptr
->pciid
) >> 16,
209 __raw_readl(&pcicptr
->pciid
) & 0xffff,
210 __raw_readl(&pcicptr
->pciccrev
) & 0xff,
211 extarb
? "External" : "Internal");
212 channel
->pci_ops
= &tx4927_pci_ops
;
214 local_irq_save(flags
);
216 /* Disable All Initiator Space */
217 __raw_writel(__raw_readl(&pcicptr
->pciccfg
)
218 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
219 | TX4927_PCIC_PCICCFG_G2PMEN(1)
220 | TX4927_PCIC_PCICCFG_G2PMEN(2)
221 | TX4927_PCIC_PCICCFG_G2PIOEN
),
224 /* GB->PCI mappings */
225 __raw_writel((channel
->io_resource
->end
- channel
->io_resource
->start
)
227 &pcicptr
->g2piomask
);
228 ____raw_writeq((channel
->io_resource
->start
+
229 channel
->io_map_base
- IO_BASE
) |
231 TX4927_PCIC_G2PIOGBASE_ECHG
233 TX4927_PCIC_G2PIOGBASE_BSDIS
235 , &pcicptr
->g2piogbase
);
236 ____raw_writeq(channel
->io_resource
->start
- channel
->io_offset
,
237 &pcicptr
->g2piopbase
);
238 for (i
= 0; i
< 3; i
++) {
239 __raw_writel(0, &pcicptr
->g2pmmask
[i
]);
240 ____raw_writeq(0, &pcicptr
->g2pmgbase
[i
]);
241 ____raw_writeq(0, &pcicptr
->g2pmpbase
[i
]);
243 if (channel
->mem_resource
->end
) {
244 __raw_writel((channel
->mem_resource
->end
245 - channel
->mem_resource
->start
) >> 4,
246 &pcicptr
->g2pmmask
[0]);
247 ____raw_writeq(channel
->mem_resource
->start
|
249 TX4927_PCIC_G2PMnGBASE_ECHG
251 TX4927_PCIC_G2PMnGBASE_BSDIS
253 , &pcicptr
->g2pmgbase
[0]);
254 ____raw_writeq(channel
->mem_resource
->start
-
256 &pcicptr
->g2pmpbase
[0]);
258 /* PCI->GB mappings (I/O 256B) */
259 __raw_writel(0, &pcicptr
->p2giopbase
); /* 256B */
260 ____raw_writeq(0, &pcicptr
->p2giogbase
);
261 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
262 __raw_writel(0, &pcicptr
->p2gm0plbase
);
263 __raw_writel(0, &pcicptr
->p2gm0pubase
);
264 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN
|
266 TX4927_PCIC_P2GMnGBASE_TECHG
268 TX4927_PCIC_P2GMnGBASE_TBSDIS
270 , &pcicptr
->p2gmgbase
[0]);
271 /* PCI->GB mappings (MEM 16MB) */
272 __raw_writel(0xffffffff, &pcicptr
->p2gm1plbase
);
273 __raw_writel(0xffffffff, &pcicptr
->p2gm1pubase
);
274 ____raw_writeq(0, &pcicptr
->p2gmgbase
[1]);
275 /* PCI->GB mappings (MEM 1MB) */
276 __raw_writel(0xffffffff, &pcicptr
->p2gm2pbase
); /* 1MB */
277 ____raw_writeq(0, &pcicptr
->p2gmgbase
[2]);
279 /* Clear all (including IRBER) except for GBWC */
280 __raw_writel((tx4927_pci_opts
.gbwc
<< 16)
281 & TX4927_PCIC_PCICCFG_GBWC_MASK
,
283 /* Enable Initiator Memory Space */
284 if (channel
->mem_resource
->end
)
285 __raw_writel(__raw_readl(&pcicptr
->pciccfg
)
286 | TX4927_PCIC_PCICCFG_G2PMEN(0),
288 /* Enable Initiator I/O Space */
289 if (channel
->io_resource
->end
)
290 __raw_writel(__raw_readl(&pcicptr
->pciccfg
)
291 | TX4927_PCIC_PCICCFG_G2PIOEN
,
293 /* Enable Initiator Config */
294 __raw_writel(__raw_readl(&pcicptr
->pciccfg
)
295 | TX4927_PCIC_PCICCFG_ICAEN
| TX4927_PCIC_PCICCFG_TCAR
,
298 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
299 __raw_writel(0, &pcicptr
->pcicfg1
);
301 __raw_writel((__raw_readl(&pcicptr
->g2ptocnt
) & ~0xffff)
302 | (tx4927_pci_opts
.trdyto
& 0xff)
303 | ((tx4927_pci_opts
.retryto
& 0xff) << 8),
306 /* Clear All Local Bus Status */
307 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL
, &pcicptr
->pcicstatus
);
308 /* Enable All Local Bus Interrupts */
309 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL
, &pcicptr
->pcicmask
);
310 /* Clear All Initiator Status */
311 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL
, &pcicptr
->g2pstatus
);
312 /* Enable All Initiator Interrupts */
313 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL
, &pcicptr
->g2pmask
);
314 /* Clear All PCI Status Error */
315 __raw_writel((__raw_readl(&pcicptr
->pcistatus
) & 0x0000ffff)
316 | (TX4927_PCIC_PCISTATUS_ALL
<< 16),
317 &pcicptr
->pcistatus
);
318 /* Enable All PCI Status Error Interrupts */
319 __raw_writel(TX4927_PCIC_PCISTATUS_ALL
, &pcicptr
->pcimask
);
322 /* Reset Bus Arbiter */
323 __raw_writel(TX4927_PCIC_PBACFG_RPBA
, &pcicptr
->pbacfg
);
324 __raw_writel(0, &pcicptr
->pbabm
);
325 /* Enable Bus Arbiter */
326 __raw_writel(TX4927_PCIC_PBACFG_PBAEN
, &pcicptr
->pbacfg
);
329 __raw_writel(PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
330 | PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
,
331 &pcicptr
->pcistatus
);
332 local_irq_restore(flags
);
335 "PCI: COMMAND=%04x,PCIMASK=%04x,"
336 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
337 __raw_readl(&pcicptr
->pcistatus
) & 0xffff,
338 __raw_readl(&pcicptr
->pcimask
) & 0xffff,
339 __raw_readl(&pcicptr
->g2ptocnt
) & 0xff,
340 (__raw_readl(&pcicptr
->g2ptocnt
) & 0xff00) >> 8,
341 (__raw_readl(&pcicptr
->pciccfg
) >> 16) & 0xfff);
344 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem
*pcicptr
)
346 __u16 pcistatus
= (__u16
)(__raw_readl(&pcicptr
->pcistatus
) >> 16);
347 __u32 g2pstatus
= __raw_readl(&pcicptr
->g2pstatus
);
348 __u32 pcicstatus
= __raw_readl(&pcicptr
->pcicstatus
);
353 { PCI_STATUS_DETECTED_PARITY
, "DetectedParityError" },
354 { PCI_STATUS_SIG_SYSTEM_ERROR
, "SignaledSystemError" },
355 { PCI_STATUS_REC_MASTER_ABORT
, "ReceivedMasterAbort" },
356 { PCI_STATUS_REC_TARGET_ABORT
, "ReceivedTargetAbort" },
357 { PCI_STATUS_SIG_TARGET_ABORT
, "SignaledTargetAbort" },
358 { PCI_STATUS_PARITY
, "MasterParityError" },
360 { TX4927_PCIC_G2PSTATUS_TTOE
, "TIOE" },
361 { TX4927_PCIC_G2PSTATUS_RTOE
, "RTOE" },
362 }, pcicstat_tbl
[] = {
363 { TX4927_PCIC_PCICSTATUS_PME
, "PME" },
364 { TX4927_PCIC_PCICSTATUS_TLB
, "TLB" },
365 { TX4927_PCIC_PCICSTATUS_NIB
, "NIB" },
366 { TX4927_PCIC_PCICSTATUS_ZIB
, "ZIB" },
367 { TX4927_PCIC_PCICSTATUS_PERR
, "PERR" },
368 { TX4927_PCIC_PCICSTATUS_SERR
, "SERR" },
369 { TX4927_PCIC_PCICSTATUS_GBE
, "GBE" },
370 { TX4927_PCIC_PCICSTATUS_IWB
, "IWB" },
375 if (pcistatus
& TX4927_PCIC_PCISTATUS_ALL
) {
376 printk(KERN_CONT
"pcistat:%04x(", pcistatus
);
377 for (i
= 0, cont
= 0; i
< ARRAY_SIZE(pcistat_tbl
); i
++)
378 if (pcistatus
& pcistat_tbl
[i
].flag
)
379 printk(KERN_CONT
"%s%s",
380 cont
++ ? " " : "", pcistat_tbl
[i
].str
);
381 printk(KERN_CONT
") ");
383 if (g2pstatus
& TX4927_PCIC_G2PSTATUS_ALL
) {
384 printk(KERN_CONT
"g2pstatus:%08x(", g2pstatus
);
385 for (i
= 0, cont
= 0; i
< ARRAY_SIZE(g2pstat_tbl
); i
++)
386 if (g2pstatus
& g2pstat_tbl
[i
].flag
)
387 printk(KERN_CONT
"%s%s",
388 cont
++ ? " " : "", g2pstat_tbl
[i
].str
);
389 printk(KERN_CONT
") ");
391 if (pcicstatus
& TX4927_PCIC_PCICSTATUS_ALL
) {
392 printk(KERN_CONT
"pcicstatus:%08x(", pcicstatus
);
393 for (i
= 0, cont
= 0; i
< ARRAY_SIZE(pcicstat_tbl
); i
++)
394 if (pcicstatus
& pcicstat_tbl
[i
].flag
)
395 printk(KERN_CONT
"%s%s",
396 cont
++ ? " " : "", pcicstat_tbl
[i
].str
);
397 printk(KERN_CONT
")");
399 printk(KERN_CONT
"\n");
402 void tx4927_report_pcic_status(void)
406 for (i
= 0; i
< ARRAY_SIZE(pcicptrs
); i
++) {
407 if (pcicptrs
[i
].pcicptr
)
408 tx4927_report_pcic_status1(pcicptrs
[i
].pcicptr
);
412 #ifdef CONFIG_TOSHIBA_FPCIB0
413 static void __init
tx4927_quirk_slc90e66_bridge(struct pci_dev
*dev
)
415 struct tx4927_pcic_reg __iomem
*pcicptr
= pci_bus_to_pcicptr(dev
->bus
);
419 if (__raw_readl(&pcicptr
->pbacfg
) & TX4927_PCIC_PBACFG_PBAEN
) {
420 /* Reset Bus Arbiter */
421 __raw_writel(TX4927_PCIC_PBACFG_RPBA
, &pcicptr
->pbacfg
);
423 * swap reqBP and reqXP (raise priority of SLC90E66).
424 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
425 * PCI Backplane board.
427 __raw_writel(0x72543610, &pcicptr
->pbareqport
);
428 __raw_writel(0, &pcicptr
->pbabm
);
429 /* Use Fixed ParkMaster (required by SLC90E66) */
430 __raw_writel(TX4927_PCIC_PBACFG_FIXPA
, &pcicptr
->pbacfg
);
431 /* Enable Bus Arbiter */
432 __raw_writel(TX4927_PCIC_PBACFG_FIXPA
|
433 TX4927_PCIC_PBACFG_PBAEN
,
435 printk(KERN_INFO
"PCI: Use Fixed Park Master (REQPORT %08x)\n",
436 __raw_readl(&pcicptr
->pbareqport
));
439 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_0
,
441 tx4927_quirk_slc90e66_bridge
);