arch/mips/pci/pci-ip27.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
   7  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <asm/sn/arch.h>
  14 #include <asm/pci/bridge.h>
  15 #include <asm/paccess.h>
  16 #include <asm/sn/intr.h>
  17 #include <asm/sn/sn0/hub.h>
  18
  19 /*
  20  * Max #PCI busses we can handle; ie, max #PCI bridges.
  21  */
  22 #define MAX_PCI_BUSSES          40
  23
  24 /*
  25  * Max #PCI devices (like scsi controllers) we handle on a bus.
  26  */
  27 #define MAX_DEVICES_PER_PCIBUS  8
  28
  29 /*
  30  * XXX: No kmalloc available when we do our crosstalk scan,
  31  *      we should try to move it later in the boot process.
  32  */
  33 static struct bridge_controller bridges[MAX_PCI_BUSSES];
  34
  35 /*
  36  * Translate from irq to software PCI bus number and PCI slot.
  37  */
  38 struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
  39 int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
  40
  41 extern struct pci_ops bridge_pci_ops;
  42
  43 int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
  44 {
  45         unsigned long offset = NODE_OFFSET(nasid);
  46         struct bridge_controller *bc;
  47         static int num_bridges = 0;
  48         bridge_t *bridge;
  49         int slot;
  50
  51         pci_probe_only = 1;
  52
  53         printk("a bridge\n");
  54
  55         /* XXX: kludge alert.. */
  56         if (!num_bridges)
  57                 ioport_resource.end = ~0UL;
  58
  59         bc = &bridges[num_bridges];
  60
  61         bc->pc.pci_ops          = &bridge_pci_ops;
  62         bc->pc.mem_resource     = &bc->mem;
  63         bc->pc.io_resource      = &bc->io;
  64
  65         bc->pc.index            = num_bridges;
  66
  67         bc->mem.name            = "Bridge PCI MEM";
  68         bc->pc.mem_offset       = offset;
  69         bc->mem.start           = 0;
  70         bc->mem.end             = ~0UL;
  71         bc->mem.flags           = IORESOURCE_MEM;
  72
  73         bc->io.name             = "Bridge IO MEM";
  74         bc->pc.io_offset        = offset;
  75         bc->io.start            = 0UL;
  76         bc->io.end              = ~0UL;
  77         bc->io.flags            = IORESOURCE_IO;
  78
  79         bc->irq_cpu = smp_processor_id();
  80         bc->widget_id = widget_id;
  81         bc->nasid = nasid;
  82
  83         bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
  84
  85         /*
  86          * point to this bridge
  87          */
  88         bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
  89
  90         /*
  91          * Clear all pending interrupts.
  92          */
  93         bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
  94
  95         /*
  96          * Until otherwise set up, assume all interrupts are from slot 0
  97          */
  98         bridge->b_int_device = 0x0;
  99
 100         /*
 101          * swap pio's to pci mem and io space (big windows)
 102          */
 103         bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
 104                                  BRIDGE_CTRL_MEM_SWAP;
 105 #ifdef CONFIG_PAGE_SIZE_4KB
 106         bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
 107 #else /* 16kB or larger */
 108         bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
 109 #endif
 110
 111         /*
 112          * Hmm...  IRIX sets additional bits in the address which
 113          * are documented as reserved in the bridge docs.
 114          */
 115         bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
 116         bridge->b_wid_int_lower = 0x01800090;   /* PI_INT_PEND_MOD off*/
 117         bridge->b_dir_map = (masterwid << 20);  /* DMA */
 118         bridge->b_int_enable = 0;
 119
 120         for (slot = 0; slot < 8; slot ++) {
 121                 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
 122                 bc->pci_int[slot] = -1;
 123         }
 124         bridge->b_wid_tflush;     /* wait until Bridge PIO complete */
 125
 126         bc->base = bridge;
 127
 128         register_pci_controller(&bc->pc);
 129
 130         num_bridges++;
 131
 132         return 0;
 133 }
 134
 135 /*
 136  * All observed requests have pin == 1. We could have a global here, that
 137  * gets incremented and returned every time - unfortunately, pci_map_irq
 138  * may be called on the same device over and over, and need to return the
 139  * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
 140  *
 141  * A given PCI device, in general, should be able to intr any of the cpus
 142  * on any one of the hubs connected to its xbow.
 143  */
 144 int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 145 {
 146         return 0;
 147 }
 148
 149 /* Most MIPS systems have straight-forward swizzling needs.  */
 150 static inline u8 bridge_swizzle(u8 pin, u8 slot)
 151 {
 152         return (((pin - 1) + slot) % 4) + 1;
 153 }
 154
 155 static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
 156 {
 157         while (dev->bus->parent) {
 158                 /* Move up the chain of bridges. */
 159                 dev = dev->bus->self;
 160         }
 161
 162         return dev;
 163 }
 164
 165 /* Do platform specific device initialization at pci_enable_device() time */
 166 int pcibios_plat_dev_init(struct pci_dev *dev)
 167 {
 168         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 169         struct pci_dev *rdev = bridge_root_dev(dev);
 170         int slot = PCI_SLOT(rdev->devfn);
 171         int irq;
 172
 173         irq = bc->pci_int[slot];
 174         if (irq == -1) {
 175                 irq = request_bridge_irq(bc);
 176                 if (irq < 0)
 177                         return irq;
 178
 179                 bc->pci_int[slot] = irq;
 180         }
 181
 182         irq_to_bridge[irq] = bc;
 183         irq_to_slot[irq] = slot;
 184
 185         dev->irq = irq;
 186
 187         return 0;
 188 }
 189
 190 /*
 191  * Device might live on a subordinate PCI bus.  XXX Walk up the chain of buses
 192  * to find the slot number in sense of the bridge device register.
 193  * XXX This also means multiple devices might rely on conflicting bridge
 194  * settings.
 195  */
 196
 197 static inline void pci_disable_swapping(struct pci_dev *dev)
 198 {
 199         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 200         bridge_t *bridge = bc->base;
 201         int slot = PCI_SLOT(dev->devfn);
 202
 203         /* Turn off byte swapping */
 204         bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
 205         bridge->b_widget.w_tflush;      /* Flush */
 206 }
 207
 208 static inline void pci_enable_swapping(struct pci_dev *dev)
 209 {
 210         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 211         bridge_t *bridge = bc->base;
 212         int slot = PCI_SLOT(dev->devfn);
 213
 214         /* Turn on byte swapping */
 215         bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
 216         bridge->b_widget.w_tflush;      /* Flush */
 217 }
 218
 219 static void __init pci_fixup_ioc3(struct pci_dev *d)
 220 {
 221         pci_disable_swapping(d);
 222 }
 223
 224 int pcibus_to_node(struct pci_bus *bus)
 225 {
 226         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 227
 228         return bc->nasid;
 229 }
 230 EXPORT_SYMBOL(pcibus_to_node);
 231
 232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
 233         pci_fixup_ioc3);