2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
9 #include <linux/kernel.h>
11 #include <linux/bootmem.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
17 * Indicate whether we respect the PCI setup left by the firmware.
19 * Make this long-lived so that we know when shutting down
20 * whether we probed only or not.
24 #define PCI_ASSIGN_ALL_BUSSES 1
26 unsigned int pci_probe
= PCI_ASSIGN_ALL_BUSSES
;
29 * The PCI controller list.
32 struct pci_controller
*hose_head
, **hose_tail
= &hose_head
;
33 struct pci_controller
*pci_isa_hose
;
35 unsigned long PCIBIOS_MIN_IO
= 0x0000;
36 unsigned long PCIBIOS_MIN_MEM
= 0;
39 * We need to avoid collisions with `mirrored' VGA ports
40 * and other strange ISA hardware, so we always want the
41 * addresses to be allocated in the 0x000-0x0ff region
44 * Why? Because some silly external IO cards only decode
45 * the low 10 bits of the IO address. The 0x00-0xff region
46 * is reserved for motherboard devices that decode all 16
47 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
48 * but we want to try to avoid allocating at 0x2900-0x2bff
49 * which might have be mirrored at 0x0100-0x03ff..
52 pcibios_align_resource(void *data
, struct resource
*res
,
53 resource_size_t size
, resource_size_t align
)
55 struct pci_dev
*dev
= data
;
56 struct pci_controller
*hose
= dev
->sysdata
;
57 resource_size_t start
= res
->start
;
59 if (res
->flags
& IORESOURCE_IO
) {
60 /* Make sure we start at our min on all hoses */
61 if (start
< PCIBIOS_MIN_IO
+ hose
->io_resource
->start
)
62 start
= PCIBIOS_MIN_IO
+ hose
->io_resource
->start
;
65 * Put everything into 0x00-0xff region modulo 0x400
68 start
= (start
+ 0x3ff) & ~0x3ff;
69 } else if (res
->flags
& IORESOURCE_MEM
) {
70 /* Make sure we start at our min on all hoses */
71 if (start
< PCIBIOS_MIN_MEM
+ hose
->mem_resource
->start
)
72 start
= PCIBIOS_MIN_MEM
+ hose
->mem_resource
->start
;
78 void __devinit
register_pci_controller(struct pci_controller
*hose
)
80 if (request_resource(&iomem_resource
, hose
->mem_resource
) < 0)
82 if (request_resource(&ioport_resource
, hose
->io_resource
) < 0) {
83 release_resource(hose
->mem_resource
);
88 hose_tail
= &hose
->next
;
91 * Do not panic here but later - this might hapen before console init.
93 if (!hose
->io_map_base
) {
95 "registering PCI controller with io_map_base unset\n");
101 "Skipping PCI bus scan due to resource conflict\n");
104 /* Most MIPS systems have straight-forward swizzling needs. */
106 static inline u8
bridge_swizzle(u8 pin
, u8 slot
)
108 return (((pin
- 1) + slot
) % 4) + 1;
111 static u8 __init
common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
115 while (dev
->bus
->parent
) {
116 pin
= bridge_swizzle(pin
, PCI_SLOT(dev
->devfn
));
117 /* Move up the chain of bridges. */
118 dev
= dev
->bus
->self
;
122 /* The slot is the slot of the last bridge. */
123 return PCI_SLOT(dev
->devfn
);
126 static int __init
pcibios_init(void)
128 struct pci_controller
*hose
;
131 int need_domain_info
= 0;
133 /* Scan all of the recorded PCI controllers. */
134 for (next_busno
= 0, hose
= hose_head
; hose
; hose
= hose
->next
) {
137 PCI_DMA_BUS_IS_PHYS
= 1;
139 if (hose
->get_busno
&& pci_probe_only
)
140 next_busno
= (*hose
->get_busno
)();
142 bus
= pci_scan_bus(next_busno
, hose
->pci_ops
, hose
);
144 need_domain_info
= need_domain_info
|| hose
->index
;
145 hose
->need_domain_info
= need_domain_info
;
147 next_busno
= bus
->subordinate
+ 1;
148 /* Don't allow 8-bit bus number overflow inside the hose -
149 reserve some space for bridges. */
150 if (next_busno
> 224) {
152 need_domain_info
= 1;
158 pci_assign_unassigned_resources();
159 pci_fixup_irqs(common_swizzle
, pcibios_map_irq
);
164 subsys_initcall(pcibios_init
);
166 static int pcibios_enable_resources(struct pci_dev
*dev
, int mask
)
172 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
174 for (idx
=0; idx
< PCI_NUM_RESOURCES
; idx
++) {
175 /* Only set up the requested stuff */
176 if (!(mask
& (1<<idx
)))
179 r
= &dev
->resource
[idx
];
180 if (!(r
->flags
& (IORESOURCE_IO
| IORESOURCE_MEM
)))
182 if ((idx
== PCI_ROM_RESOURCE
) &&
183 (!(r
->flags
& IORESOURCE_ROM_ENABLE
)))
185 if (!r
->start
&& r
->end
) {
186 printk(KERN_ERR
"PCI: Device %s not available "
187 "because of resource collisions\n",
191 if (r
->flags
& IORESOURCE_IO
)
192 cmd
|= PCI_COMMAND_IO
;
193 if (r
->flags
& IORESOURCE_MEM
)
194 cmd
|= PCI_COMMAND_MEMORY
;
196 if (cmd
!= old_cmd
) {
197 printk("PCI: Enabling device %s (%04x -> %04x)\n",
198 pci_name(dev
), old_cmd
, cmd
);
199 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
205 * If we set up a device for bus mastering, we need to check the latency
206 * timer as certain crappy BIOSes forget to set it properly.
208 unsigned int pcibios_max_latency
= 255;
210 void pcibios_set_master(struct pci_dev
*dev
)
213 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
215 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
216 else if (lat
> pcibios_max_latency
)
217 lat
= pcibios_max_latency
;
220 printk(KERN_DEBUG
"PCI: Setting latency timer of device %s to %d\n",
222 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
225 unsigned int pcibios_assign_all_busses(void)
227 return (pci_probe
& PCI_ASSIGN_ALL_BUSSES
) ? 1 : 0;
230 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
234 if ((err
= pcibios_enable_resources(dev
, mask
)) < 0)
237 return pcibios_plat_dev_init(dev
);
240 static void pcibios_fixup_device_resources(struct pci_dev
*dev
,
243 /* Update device resources. */
244 struct pci_controller
*hose
= (struct pci_controller
*)bus
->sysdata
;
245 unsigned long offset
= 0;
248 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
249 if (!dev
->resource
[i
].start
)
251 if (dev
->resource
[i
].flags
& IORESOURCE_PCI_FIXED
)
253 if (dev
->resource
[i
].flags
& IORESOURCE_IO
)
254 offset
= hose
->io_offset
;
255 else if (dev
->resource
[i
].flags
& IORESOURCE_MEM
)
256 offset
= hose
->mem_offset
;
258 dev
->resource
[i
].start
+= offset
;
259 dev
->resource
[i
].end
+= offset
;
263 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
265 /* Propagate hose info into the subordinate devices. */
267 struct pci_controller
*hose
= bus
->sysdata
;
268 struct list_head
*ln
;
269 struct pci_dev
*dev
= bus
->self
;
272 bus
->resource
[0] = hose
->io_resource
;
273 bus
->resource
[1] = hose
->mem_resource
;
274 } else if (pci_probe_only
&&
275 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
276 pci_read_bridge_bases(bus
);
277 pcibios_fixup_device_resources(dev
, bus
);
280 for (ln
= bus
->devices
.next
; ln
!= &bus
->devices
; ln
= ln
->next
) {
283 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
284 pcibios_fixup_device_resources(dev
, bus
);
289 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
291 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
294 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
295 struct resource
*res
)
297 struct pci_controller
*hose
= (struct pci_controller
*)dev
->sysdata
;
298 unsigned long offset
= 0;
300 if (res
->flags
& IORESOURCE_IO
)
301 offset
= hose
->io_offset
;
302 else if (res
->flags
& IORESOURCE_MEM
)
303 offset
= hose
->mem_offset
;
305 region
->start
= res
->start
- offset
;
306 region
->end
= res
->end
- offset
;
310 pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
311 struct pci_bus_region
*region
)
313 struct pci_controller
*hose
= (struct pci_controller
*)dev
->sysdata
;
314 unsigned long offset
= 0;
316 if (res
->flags
& IORESOURCE_IO
)
317 offset
= hose
->io_offset
;
318 else if (res
->flags
& IORESOURCE_MEM
)
319 offset
= hose
->mem_offset
;
321 res
->start
= region
->start
+ offset
;
322 res
->end
= region
->end
+ offset
;
325 #ifdef CONFIG_HOTPLUG
326 EXPORT_SYMBOL(pcibios_resource_to_bus
);
327 EXPORT_SYMBOL(pcibios_bus_to_resource
);
328 EXPORT_SYMBOL(PCIBIOS_MIN_IO
);
329 EXPORT_SYMBOL(PCIBIOS_MIN_MEM
);
332 char *pcibios_setup(char *str
)
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