arch/mips/pci/pci.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
   8  */
   9 #include <linux/kernel.h>
  10 #include <linux/mm.h>
  11 #include <linux/bootmem.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/pci.h>
  15
  16 /*
  17  * Indicate whether we respect the PCI setup left by the firmware.
  18  *
  19  * Make this long-lived  so that we know when shutting down
  20  * whether we probed only or not.
  21  */
  22 int pci_probe_only;
  23
  24 #define PCI_ASSIGN_ALL_BUSSES   1
  25
  26 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
  27
  28 /*
  29  * The PCI controller list.
  30  */
  31
  32 static struct pci_controller *hose_head, **hose_tail = &hose_head;
  33
  34 unsigned long PCIBIOS_MIN_IO    = 0x0000;
  35 unsigned long PCIBIOS_MIN_MEM   = 0;
  36
  37 static int pci_initialized;
  38
  39 /*
  40  * We need to avoid collisions with `mirrored' VGA ports
  41  * and other strange ISA hardware, so we always want the
  42  * addresses to be allocated in the 0x000-0x0ff region
  43  * modulo 0x400.
  44  *
  45  * Why? Because some silly external IO cards only decode
  46  * the low 10 bits of the IO address. The 0x00-0xff region
  47  * is reserved for motherboard devices that decode all 16
  48  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  49  * but we want to try to avoid allocating at 0x2900-0x2bff
  50  * which might have be mirrored at 0x0100-0x03ff..
  51  */
  52 void
  53 pcibios_align_resource(void *data, struct resource *res,
  54                        resource_size_t size, resource_size_t align)
  55 {
  56         struct pci_dev *dev = data;
  57         struct pci_controller *hose = dev->sysdata;
  58         resource_size_t start = res->start;
  59
  60         if (res->flags & IORESOURCE_IO) {
  61                 /* Make sure we start at our min on all hoses */
  62                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  63                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
  64
  65                 /*
  66                  * Put everything into 0x00-0xff region modulo 0x400
  67                  */
  68                 if (start & 0x300)
  69                         start = (start + 0x3ff) & ~0x3ff;
  70         } else if (res->flags & IORESOURCE_MEM) {
  71                 /* Make sure we start at our min on all hoses */
  72                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  73                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  74         }
  75
  76         res->start = start;
  77 }
  78
  79 static void __devinit pcibios_scanbus(struct pci_controller *hose)
  80 {
  81         static int next_busno;
  82         static int need_domain_info;
  83         struct pci_bus *bus;
  84
  85         if (!hose->iommu)
  86                 PCI_DMA_BUS_IS_PHYS = 1;
  87
  88         if (hose->get_busno && pci_probe_only)
  89                 next_busno = (*hose->get_busno)();
  90
  91         bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
  92         hose->bus = bus;
  93
  94         need_domain_info = need_domain_info || hose->index;
  95         hose->need_domain_info = need_domain_info;
  96         if (bus) {
  97                 next_busno = bus->subordinate + 1;
  98                 /* Don't allow 8-bit bus number overflow inside the hose -
  99                    reserve some space for bridges. */
 100                 if (next_busno > 224) {
 101                         next_busno = 0;
 102                         need_domain_info = 1;
 103                 }
 104
 105                 if (!pci_probe_only) {
 106                         pci_bus_size_bridges(bus);
 107                         pci_bus_assign_resources(bus);
 108                         pci_enable_bridges(bus);
 109                 }
 110         }
 111 }
 112
 113 static DEFINE_MUTEX(pci_scan_mutex);
 114
 115 void __devinit register_pci_controller(struct pci_controller *hose)
 116 {
 117         if (request_resource(&iomem_resource, hose->mem_resource) < 0)
 118                 goto out;
 119         if (request_resource(&ioport_resource, hose->io_resource) < 0) {
 120                 release_resource(hose->mem_resource);
 121                 goto out;
 122         }
 123
 124         *hose_tail = hose;
 125         hose_tail = &hose->next;
 126
 127         /*
 128          * Do not panic here but later - this might hapen before console init.
 129          */
 130         if (!hose->io_map_base) {
 131                 printk(KERN_WARNING
 132                        "registering PCI controller with io_map_base unset\n");
 133         }
 134
 135         /*
 136          * Scan the bus if it is register after the PCI subsystem
 137          * initialization.
 138          */
 139         if (pci_initialized) {
 140                 mutex_lock(&pci_scan_mutex);
 141                 pcibios_scanbus(hose);
 142                 mutex_unlock(&pci_scan_mutex);
 143         }
 144
 145         return;
 146
 147 out:
 148         printk(KERN_WARNING
 149                "Skipping PCI bus scan due to resource conflict\n");
 150 }
 151
 152 static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
 153 {
 154         u8 pin = *pinp;
 155
 156         while (dev->bus->parent) {
 157                 pin = pci_swizzle_interrupt_pin(dev, pin);
 158                 /* Move up the chain of bridges. */
 159                 dev = dev->bus->self;
 160         }
 161         *pinp = pin;
 162
 163         /* The slot is the slot of the last bridge. */
 164         return PCI_SLOT(dev->devfn);
 165 }
 166
 167 static int __init pcibios_init(void)
 168 {
 169         struct pci_controller *hose;
 170
 171         /* Scan all of the recorded PCI controllers.  */
 172         for (hose = hose_head; hose; hose = hose->next)
 173                 pcibios_scanbus(hose);
 174
 175         pci_fixup_irqs(common_swizzle, pcibios_map_irq);
 176
 177         pci_initialized = 1;
 178
 179         return 0;
 180 }
 181
 182 subsys_initcall(pcibios_init);
 183
 184 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 185 {
 186         u16 cmd, old_cmd;
 187         int idx;
 188         struct resource *r;
 189
 190         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 191         old_cmd = cmd;
 192         for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
 193                 /* Only set up the requested stuff */
 194                 if (!(mask & (1<<idx)))
 195                         continue;
 196
 197                 r = &dev->resource[idx];
 198                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 199                         continue;
 200                 if ((idx == PCI_ROM_RESOURCE) &&
 201                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 202                         continue;
 203                 if (!r->start && r->end) {
 204                         printk(KERN_ERR "PCI: Device %s not available "
 205                                "because of resource collisions\n",
 206                                pci_name(dev));
 207                         return -EINVAL;
 208                 }
 209                 if (r->flags & IORESOURCE_IO)
 210                         cmd |= PCI_COMMAND_IO;
 211                 if (r->flags & IORESOURCE_MEM)
 212                         cmd |= PCI_COMMAND_MEMORY;
 213         }
 214         if (cmd != old_cmd) {
 215                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 216                        pci_name(dev), old_cmd, cmd);
 217                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 218         }
 219         return 0;
 220 }
 221
 222 /*
 223  *  If we set up a device for bus mastering, we need to check the latency
 224  *  timer as certain crappy BIOSes forget to set it properly.
 225  */
 226 static unsigned int pcibios_max_latency = 255;
 227
 228 void pcibios_set_master(struct pci_dev *dev)
 229 {
 230         u8 lat;
 231         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 232         if (lat < 16)
 233                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 234         else if (lat > pcibios_max_latency)
 235                 lat = pcibios_max_latency;
 236         else
 237                 return;
 238         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
 239                pci_name(dev), lat);
 240         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 241 }
 242
 243 unsigned int pcibios_assign_all_busses(void)
 244 {
 245         return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
 246 }
 247
 248 int pcibios_enable_device(struct pci_dev *dev, int mask)
 249 {
 250         int err;
 251
 252         if ((err = pcibios_enable_resources(dev, mask)) < 0)
 253                 return err;
 254
 255         return pcibios_plat_dev_init(dev);
 256 }
 257
 258 static void pcibios_fixup_device_resources(struct pci_dev *dev,
 259         struct pci_bus *bus)
 260 {
 261         /* Update device resources.  */
 262         struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
 263         unsigned long offset = 0;
 264         int i;
 265
 266         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 267                 if (!dev->resource[i].start)
 268                         continue;
 269                 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
 270                         continue;
 271                 if (dev->resource[i].flags & IORESOURCE_IO)
 272                         offset = hose->io_offset;
 273                 else if (dev->resource[i].flags & IORESOURCE_MEM)
 274                         offset = hose->mem_offset;
 275
 276                 dev->resource[i].start += offset;
 277                 dev->resource[i].end += offset;
 278         }
 279 }
 280
 281 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 282 {
 283         /* Propagate hose info into the subordinate devices.  */
 284
 285         struct pci_controller *hose = bus->sysdata;
 286         struct list_head *ln;
 287         struct pci_dev *dev = bus->self;
 288
 289         if (!dev) {
 290                 bus->resource[0] = hose->io_resource;
 291                 bus->resource[1] = hose->mem_resource;
 292         } else if (pci_probe_only &&
 293                    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 294                 pci_read_bridge_bases(bus);
 295                 pcibios_fixup_device_resources(dev, bus);
 296         }
 297
 298         for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
 299                 dev = pci_dev_b(ln);
 300
 301                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 302                         pcibios_fixup_device_resources(dev, bus);
 303         }
 304 }
 305
 306 void __init
 307 pcibios_update_irq(struct pci_dev *dev, int irq)
 308 {
 309         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 310 }
 311
 312 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 313                          struct resource *res)
 314 {
 315         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 316         unsigned long offset = 0;
 317
 318         if (res->flags & IORESOURCE_IO)
 319                 offset = hose->io_offset;
 320         else if (res->flags & IORESOURCE_MEM)
 321                 offset = hose->mem_offset;
 322
 323         region->start = res->start - offset;
 324         region->end = res->end - offset;
 325 }
 326
 327 void __devinit
 328 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 329                         struct pci_bus_region *region)
 330 {
 331         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 332         unsigned long offset = 0;
 333
 334         if (res->flags & IORESOURCE_IO)
 335                 offset = hose->io_offset;
 336         else if (res->flags & IORESOURCE_MEM)
 337                 offset = hose->mem_offset;
 338
 339         res->start = region->start + offset;
 340         res->end = region->end + offset;
 341 }
 342
 343 #ifdef CONFIG_HOTPLUG
 344 EXPORT_SYMBOL(pcibios_resource_to_bus);
 345 EXPORT_SYMBOL(pcibios_bus_to_resource);
 346 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 347 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 348 #endif
 349
 350 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 351                         enum pci_mmap_state mmap_state, int write_combine)
 352 {
 353         unsigned long prot;
 354
 355         /*
 356          * I/O space can be accessed via normal processor loads and stores on
 357          * this platform but for now we elect not to do this and portable
 358          * drivers should not do this anyway.
 359          */
 360         if (mmap_state == pci_mmap_io)
 361                 return -EINVAL;
 362
 363         /*
 364          * Ignore write-combine; for now only return uncached mappings.
 365          */
 366         prot = pgprot_val(vma->vm_page_prot);
 367         prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
 368         vma->vm_page_prot = __pgprot(prot);
 369
 370         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 371                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 372 }
 373
 374 char * (*pcibios_plat_setup)(char *str) __devinitdata;
 375
 376 char *__devinit pcibios_setup(char *str)
 377 {
 378         if (pcibios_plat_setup)
 379                 return pcibios_plat_setup(str);
 380         return str;
 381 }