arch/mips/pmc-sierra/yosemite/setup.c

   1 /*
   2  *  Copyright (C) 2003 PMC-Sierra Inc.
   3  *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
   4  *
   5  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27 #include <linux/bcd.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/types.h>
  31 #include <linux/mm.h>
  32 #include <linux/bootmem.h>
  33 #include <linux/swap.h>
  34 #include <linux/ioport.h>
  35 #include <linux/sched.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/timex.h>
  38 #include <linux/termios.h>
  39 #include <linux/tty.h>
  40 #include <linux/serial.h>
  41 #include <linux/serial_core.h>
  42 #include <linux/serial_8250.h>
  43
  44 #include <asm/time.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/page.h>
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49 #include <asm/processor.h>
  50 #include <asm/reboot.h>
  51 #include <asm/serial.h>
  52 #include <asm/titan_dep.h>
  53 #include <asm/m48t37.h>
  54
  55 #include "setup.h"
  56
  57 unsigned char titan_ge_mac_addr_base[6] = {
  58         // 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
  59         0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
  60 };
  61
  62 unsigned long cpu_clock_freq;
  63 unsigned long yosemite_base;
  64
  65 static struct m48t37_rtc *m48t37_base;
  66
  67 void __init bus_error_init(void)
  68 {
  69         /* Do nothing */
  70 }
  71
  72
  73 unsigned long m48t37y_get_time(void)
  74 {
  75         unsigned int year, month, day, hour, min, sec;
  76         unsigned long flags;
  77
  78         spin_lock_irqsave(&rtc_lock, flags);
  79         /* Stop the update to the time */
  80         m48t37_base->control = 0x40;
  81
  82         year = BCD2BIN(m48t37_base->year);
  83         year += BCD2BIN(m48t37_base->century) * 100;
  84
  85         month = BCD2BIN(m48t37_base->month);
  86         day = BCD2BIN(m48t37_base->date);
  87         hour = BCD2BIN(m48t37_base->hour);
  88         min = BCD2BIN(m48t37_base->min);
  89         sec = BCD2BIN(m48t37_base->sec);
  90
  91         /* Start the update to the time again */
  92         m48t37_base->control = 0x00;
  93         spin_unlock_irqrestore(&rtc_lock, flags);
  94
  95         return mktime(year, month, day, hour, min, sec);
  96 }
  97
  98 int m48t37y_set_time(unsigned long sec)
  99 {
 100         struct rtc_time tm;
 101         unsigned long flags;
 102
 103         /* convert to a more useful format -- note months count from 0 */
 104         to_tm(sec, &tm);
 105         tm.tm_mon += 1;
 106
 107         spin_lock_irqsave(&rtc_lock, flags);
 108         /* enable writing */
 109         m48t37_base->control = 0x80;
 110
 111         /* year */
 112         m48t37_base->year = BIN2BCD(tm.tm_year % 100);
 113         m48t37_base->century = BIN2BCD(tm.tm_year / 100);
 114
 115         /* month */
 116         m48t37_base->month = BIN2BCD(tm.tm_mon);
 117
 118         /* day */
 119         m48t37_base->date = BIN2BCD(tm.tm_mday);
 120
 121         /* hour/min/sec */
 122         m48t37_base->hour = BIN2BCD(tm.tm_hour);
 123         m48t37_base->min = BIN2BCD(tm.tm_min);
 124         m48t37_base->sec = BIN2BCD(tm.tm_sec);
 125
 126         /* day of week -- not really used, but let's keep it up-to-date */
 127         m48t37_base->day = BIN2BCD(tm.tm_wday + 1);
 128
 129         /* disable writing */
 130         m48t37_base->control = 0x00;
 131         spin_unlock_irqrestore(&rtc_lock, flags);
 132
 133         return 0;
 134 }
 135
 136 void __init plat_timer_setup(struct irqaction *irq)
 137 {
 138         setup_irq(7, irq);
 139 }
 140
 141 void yosemite_time_init(void)
 142 {
 143         mips_hpt_frequency = cpu_clock_freq / 2;
 144 mips_hpt_frequency = 33000000 * 3 * 5;
 145 }
 146
 147 /* No other usable initialization hook than this ...  */
 148 extern void (*late_time_init)(void);
 149
 150 unsigned long ocd_base;
 151
 152 EXPORT_SYMBOL(ocd_base);
 153
 154 /*
 155  * Common setup before any secondaries are started
 156  */
 157
 158 #define TITAN_UART_CLK          3686400
 159 #define TITAN_SERIAL_BASE_BAUD  (TITAN_UART_CLK / 16)
 160 #define TITAN_SERIAL_IRQ        4
 161 #define TITAN_SERIAL_BASE       0xfd000008UL
 162
 163 static void __init py_map_ocd(void)
 164 {
 165         ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
 166         if (!ocd_base)
 167                 panic("Mapping OCD failed - game over.  Your score is 0.");
 168
 169         /* Kludge for PMON bug ... */
 170         OCD_WRITE(0x0710, 0x0ffff029);
 171 }
 172
 173 static void __init py_uart_setup(void)
 174 {
 175 #ifdef CONFIG_SERIAL_8250
 176         struct uart_port up;
 177
 178         /*
 179          * Register to interrupt zero because we share the interrupt with
 180          * the serial driver which we don't properly support yet.
 181          */
 182         memset(&up, 0, sizeof(up));
 183         up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
 184         up.irq          = TITAN_SERIAL_IRQ;
 185         up.uartclk      = TITAN_UART_CLK;
 186         up.regshift     = 0;
 187         up.iotype       = UPIO_MEM;
 188         up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 189         up.line         = 0;
 190
 191         if (early_serial_setup(&up))
 192                 printk(KERN_ERR "Early serial init of port 0 failed\n");
 193 #endif /* CONFIG_SERIAL_8250 */
 194 }
 195
 196 static void __init py_rtc_setup(void)
 197 {
 198         m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
 199         if (!m48t37_base)
 200                 printk(KERN_ERR "Mapping the RTC failed\n");
 201
 202         rtc_mips_get_time = m48t37y_get_time;
 203         rtc_mips_set_time = m48t37y_set_time;
 204
 205         write_seqlock(&xtime_lock);
 206         xtime.tv_sec = m48t37y_get_time();
 207         xtime.tv_nsec = 0;
 208
 209         set_normalized_timespec(&wall_to_monotonic,
 210                                 -xtime.tv_sec, -xtime.tv_nsec);
 211         write_sequnlock(&xtime_lock);
 212 }
 213
 214 /* Not only time init but that's what the hook it's called through is named */
 215 static void __init py_late_time_init(void)
 216 {
 217         py_map_ocd();
 218         py_uart_setup();
 219         py_rtc_setup();
 220 }
 221
 222 void __init plat_mem_setup(void)
 223 {
 224         board_time_init = yosemite_time_init;
 225         late_time_init = py_late_time_init;
 226
 227         /* Add memory regions */
 228         add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
 229
 230 #if 0 /* XXX Crash ...  */
 231         OCD_WRITE(RM9000x2_OCD_HTSC,
 232                   OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
 233
 234         /* Set the BAR. Shifted mode */
 235         OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
 236         OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
 237 #endif
 238 }