arch/mips/pnx833x/common/interrupts.c

   1 /*
   2  *  interrupts.c: Interrupt mappings for PNX833X.
   3  *
   4  *  Copyright 2008 NXP Semiconductors
   5  *        Chris Steel <chris.steel@nxp.com>
   6  *    Daniel Laird <daniel.j.laird@nxp.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/irq.h>
  24 #include <linux/hardirq.h>
  25 #include <linux/interrupt.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/irq_cpu.h>
  28 #include <asm/setup.h>
  29 #include <irq.h>
  30 #include <irq-mapping.h>
  31 #include <gpio.h>
  32
  33 static int mips_cpu_timer_irq;
  34
  35 static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
  36 {
  37     0, /* unused */
  38     4, /* PNX833X_PIC_I2C0_INT                 1 */
  39     4, /* PNX833X_PIC_I2C1_INT                 2 */
  40     1, /* PNX833X_PIC_UART0_INT                3 */
  41     1, /* PNX833X_PIC_UART1_INT                4 */
  42     6, /* PNX833X_PIC_TS_IN0_DV_INT            5 */
  43     6, /* PNX833X_PIC_TS_IN0_DMA_INT           6 */
  44     7, /* PNX833X_PIC_GPIO_INT                 7 */
  45     4, /* PNX833X_PIC_AUDIO_DEC_INT            8 */
  46     5, /* PNX833X_PIC_VIDEO_DEC_INT            9 */
  47     4, /* PNX833X_PIC_CONFIG_INT              10 */
  48     4, /* PNX833X_PIC_AOI_INT                 11 */
  49     9, /* PNX833X_PIC_SYNC_INT                12 */
  50     9, /* PNX8335_PIC_SATA_INT                13 */
  51     4, /* PNX833X_PIC_OSD_INT                 14 */
  52     9, /* PNX833X_PIC_DISP1_INT               15 */
  53     4, /* PNX833X_PIC_DEINTERLACER_INT        16 */
  54     9, /* PNX833X_PIC_DISPLAY2_INT            17 */
  55     4, /* PNX833X_PIC_VC_INT                  18 */
  56     4, /* PNX833X_PIC_SC_INT                  19 */
  57     9, /* PNX833X_PIC_IDE_INT                 20 */
  58     9, /* PNX833X_PIC_IDE_DMA_INT             21 */
  59     6, /* PNX833X_PIC_TS_IN1_DV_INT           22 */
  60     6, /* PNX833X_PIC_TS_IN1_DMA_INT          23 */
  61     4, /* PNX833X_PIC_SGDX_DMA_INT            24 */
  62     4, /* PNX833X_PIC_TS_OUT_INT              25 */
  63     4, /* PNX833X_PIC_IR_INT                  26 */
  64     3, /* PNX833X_PIC_VMSP1_INT               27 */
  65     3, /* PNX833X_PIC_VMSP2_INT               28 */
  66     4, /* PNX833X_PIC_PIBC_INT                29 */
  67     4, /* PNX833X_PIC_TS_IN0_TRD_INT          30 */
  68     4, /* PNX833X_PIC_SGDX_TPD_INT            31 */
  69     5, /* PNX833X_PIC_USB_INT                 32 */
  70     4, /* PNX833X_PIC_TS_IN1_TRD_INT          33 */
  71     4, /* PNX833X_PIC_CLOCK_INT               34 */
  72     4, /* PNX833X_PIC_SGDX_PARSER_INT         35 */
  73     4, /* PNX833X_PIC_VMSP_DMA_INT            36 */
  74 #if defined(CONFIG_SOC_PNX8335)
  75     4, /* PNX8335_PIC_MIU_INT                 37 */
  76     4, /* PNX8335_PIC_AVCHIP_IRQ_INT          38 */
  77     9, /* PNX8335_PIC_SYNC_HD_INT             39 */
  78     9, /* PNX8335_PIC_DISP_HD_INT             40 */
  79     9, /* PNX8335_PIC_DISP_SCALER_INT         41 */
  80     4, /* PNX8335_PIC_OSD_HD1_INT             42 */
  81     4, /* PNX8335_PIC_DTL_WRITER_Y_INT        43 */
  82     4, /* PNX8335_PIC_DTL_WRITER_C_INT        44 */
  83     4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT   45 */
  84     4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT   46 */
  85     4, /* PNX8335_PIC_DENC_TTX_INT            47 */
  86     4, /* PNX8335_PIC_MMI_SIF0_INT            48 */
  87     4, /* PNX8335_PIC_MMI_SIF1_INT            49 */
  88     4, /* PNX8335_PIC_MMI_CDMMU_INT           50 */
  89     4, /* PNX8335_PIC_PIBCS_INT               51 */
  90    12, /* PNX8335_PIC_ETHERNET_INT            52 */
  91     3, /* PNX8335_PIC_VMSP1_0_INT             53 */
  92     3, /* PNX8335_PIC_VMSP1_1_INT             54 */
  93     4, /* PNX8335_PIC_VMSP1_DMA_INT           55 */
  94     4, /* PNX8335_PIC_TDGR_DE_INT             56 */
  95     4, /* PNX8335_PIC_IR1_IRQ_INT             57 */
  96 #endif
  97 };
  98
  99 static void pnx833x_timer_dispatch(void)
 100 {
 101         do_IRQ(mips_cpu_timer_irq);
 102 }
 103
 104 static void pic_dispatch(void)
 105 {
 106         unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
 107
 108         if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
 109                 unsigned long priority = PNX833X_PIC_INT_PRIORITY;
 110                 PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
 111
 112                 if (irq == PNX833X_PIC_GPIO_INT) {
 113                         unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
 114                         int pin;
 115                         while ((pin = ffs(mask & 0xffff))) {
 116                                 pin -= 1;
 117                                 do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
 118                                 mask &= ~(1 << pin);
 119                         }
 120                 } else {
 121                         do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
 122                 }
 123
 124                 PNX833X_PIC_INT_PRIORITY = priority;
 125         } else {
 126                 printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
 127         }
 128 }
 129
 130 asmlinkage void plat_irq_dispatch(void)
 131 {
 132         unsigned int pending = read_c0_status() & read_c0_cause();
 133
 134         if (pending & STATUSF_IP4)
 135                 pic_dispatch();
 136         else if (pending & STATUSF_IP7)
 137                 do_IRQ(PNX833X_TIMER_IRQ);
 138         else
 139                 spurious_interrupt();
 140 }
 141
 142 static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
 143 {
 144         /* Currently we do this by setting IRQ priority to 1.
 145            If priority support is being implemented, 1 should be repalced
 146                 by a better value. */
 147         PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
 148 }
 149
 150 static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
 151 {
 152         /* Disable IRQ by writing setting it's priority to 0 */
 153         PNX833X_PIC_INT_REG(irq) = 0;
 154 }
 155
 156 static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
 157
 158 static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
 159 {
 160         unsigned long flags;
 161         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
 162
 163         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 164         pnx833x_hard_enable_pic_irq(pic_irq);
 165         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
 166         return 0;
 167 }
 168
 169 static void pnx833x_enable_pic_irq(struct irq_data *d)
 170 {
 171         unsigned long flags;
 172         unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
 173
 174         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 175         pnx833x_hard_enable_pic_irq(pic_irq);
 176         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
 177 }
 178
 179 static void pnx833x_disable_pic_irq(struct irq_data *d)
 180 {
 181         unsigned long flags;
 182         unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
 183
 184         raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 185         pnx833x_hard_disable_pic_irq(pic_irq);
 186         raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
 187 }
 188
 189 static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
 190
 191 static void pnx833x_enable_gpio_irq(struct irq_data *d)
 192 {
 193         int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
 194         unsigned long flags;
 195         raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
 196         pnx833x_gpio_enable_irq(pin);
 197         raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
 198 }
 199
 200 static void pnx833x_disable_gpio_irq(struct irq_data *d)
 201 {
 202         int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
 203         unsigned long flags;
 204         raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
 205         pnx833x_gpio_disable_irq(pin);
 206         raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
 207 }
 208
 209 static int pnx833x_set_type_gpio_irq(struct irq_data *d, unsigned int flow_type)
 210 {
 211         int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
 212         int gpio_mode;
 213
 214         switch (flow_type) {
 215         case IRQ_TYPE_EDGE_RISING:
 216                 gpio_mode = GPIO_INT_EDGE_RISING;
 217                 break;
 218         case IRQ_TYPE_EDGE_FALLING:
 219                 gpio_mode = GPIO_INT_EDGE_FALLING;
 220                 break;
 221         case IRQ_TYPE_EDGE_BOTH:
 222                 gpio_mode = GPIO_INT_EDGE_BOTH;
 223                 break;
 224         case IRQ_TYPE_LEVEL_HIGH:
 225                 gpio_mode = GPIO_INT_LEVEL_HIGH;
 226                 break;
 227         case IRQ_TYPE_LEVEL_LOW:
 228                 gpio_mode = GPIO_INT_LEVEL_LOW;
 229                 break;
 230         default:
 231                 gpio_mode = GPIO_INT_NONE;
 232                 break;
 233         }
 234
 235         pnx833x_gpio_setup_irq(gpio_mode, pin);
 236
 237         return 0;
 238 }
 239
 240 static struct irq_chip pnx833x_pic_irq_type = {
 241         .name = "PNX-PIC",
 242         .irq_enable = pnx833x_enable_pic_irq,
 243         .irq_disable = pnx833x_disable_pic_irq,
 244 };
 245
 246 static struct irq_chip pnx833x_gpio_irq_type = {
 247         .name = "PNX-GPIO",
 248         .irq_enable = pnx833x_enable_gpio_irq,
 249         .irq_disable = pnx833x_disable_gpio_irq,
 250         .irq_set_type = pnx833x_set_type_gpio_irq,
 251 };
 252
 253 void __init arch_init_irq(void)
 254 {
 255         unsigned int irq;
 256
 257         /* setup standard internal cpu irqs */
 258         mips_cpu_irq_init();
 259
 260         /* Set IRQ information in irq_desc */
 261         for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
 262                 pnx833x_hard_disable_pic_irq(irq);
 263                 irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
 264                                          handle_simple_irq);
 265         }
 266
 267         for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
 268                 irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
 269                                          handle_simple_irq);
 270
 271         /* Set PIC priority limiter register to 0 */
 272         PNX833X_PIC_INT_PRIORITY = 0;
 273
 274         /* Setup GPIO IRQ dispatching */
 275         pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
 276
 277         /* Enable PIC IRQs (HWIRQ2) */
 278         if (cpu_has_vint)
 279                 set_vi_handler(4, pic_dispatch);
 280
 281         write_c0_status(read_c0_status() | IE_IRQ2);
 282 }
 283
 284 unsigned int __cpuinit get_c0_compare_int(void)
 285 {
 286         if (cpu_has_vint)
 287                 set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
 288
 289         mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 290         return mips_cpu_timer_irq;
 291 }
 292
 293 void __init plat_time_init(void)
 294 {
 295         /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
 296
 297         extern unsigned long mips_hpt_frequency;
 298         unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
 299
 300         if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
 301                 /* Functional clock is disabled so use crystal frequency */
 302                 mips_hpt_frequency = 25;
 303         } else {
 304 #if defined(CONFIG_SOC_PNX8335)
 305                 /* Functional clock is enabled, so get clock multiplier */
 306                 mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
 307 #else
 308                 static const unsigned long int freq[4] = {240, 160, 120, 80};
 309                 mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
 310 #endif
 311         }
 312
 313         printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
 314
 315         mips_hpt_frequency *= 500000;
 316 }