2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
11 #include <linux/init.h>
12 #include <linux/irq.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/timex.h>
20 #include <linux/slab.h>
21 #include <linux/random.h>
22 #include <linux/kernel.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/delay.h>
25 #include <linux/bitops.h>
27 #include <asm/bootinfo.h>
29 #include <asm/mipsregs.h>
30 #include <asm/system.h>
32 #include <asm/processor.h>
33 #include <asm/pci/bridge.h>
34 #include <asm/sn/addrs.h>
35 #include <asm/sn/agent.h>
36 #include <asm/sn/arch.h>
37 #include <asm/sn/hub.h>
38 #include <asm/sn/intr.h>
41 * Linux has a controller-independent x86 interrupt architecture.
42 * every controller has a 'controller-template', that is used
43 * by the main code to do the right thing. Each driver-visible
44 * interrupt source is transparently wired to the apropriate
45 * controller. Thus drivers need not be aware of the
46 * interrupt-controller.
48 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
49 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
50 * (IO-APICs assumed to be messaging to Pentium local-APICs)
52 * the code is designed to be easily extended with new/different
53 * interrupt controllers, without having to do assembly magic.
56 extern asmlinkage
void ip27_irq(void);
58 extern struct bridge_controller
*irq_to_bridge
[];
59 extern int irq_to_slot
[];
62 * use these macros to get the encoded nasid and widget id
65 #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
66 #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
68 static inline int alloc_level(int cpu
, int irq
)
70 struct hub_data
*hub
= hub_data(cpu_to_node(cpu
));
71 struct slice_data
*si
= cpu_data
[cpu
].data
;
74 level
= find_first_zero_bit(hub
->irq_alloc_mask
, LEVELS_PER_SLICE
);
75 if (level
>= LEVELS_PER_SLICE
)
76 panic("Cpu %d flooded with devices\n", cpu
);
78 __set_bit(level
, hub
->irq_alloc_mask
);
79 si
->level_to_irq
[level
] = irq
;
84 static inline int find_level(cpuid_t
*cpunum
, int irq
)
88 for_each_online_cpu(cpu
) {
89 struct slice_data
*si
= cpu_data
[cpu
].data
;
91 for (i
= BASE_PCI_IRQ
; i
< LEVELS_PER_SLICE
; i
++)
92 if (si
->level_to_irq
[i
] == irq
) {
99 panic("Could not identify cpu/level for irq %d\n", irq
);
105 static int ms1bit(unsigned long x
)
109 s
= 16; if (x
>> 16 == 0) s
= 0; b
+= s
; x
>>= s
;
110 s
= 8; if (x
>> 8 == 0) s
= 0; b
+= s
; x
>>= s
;
111 s
= 4; if (x
>> 4 == 0) s
= 0; b
+= s
; x
>>= s
;
112 s
= 2; if (x
>> 2 == 0) s
= 0; b
+= s
; x
>>= s
;
113 s
= 1; if (x
>> 1 == 0) s
= 0; b
+= s
;
119 * This code is unnecessarily complex, because we do IRQF_DISABLED
120 * intr enabling. Basically, once we grab the set of intrs we need
121 * to service, we must mask _all_ these interrupts; firstly, to make
122 * sure the same intr does not intr again, causing recursion that
123 * can lead to stack overflow. Secondly, we can not just mask the
124 * one intr we are do_IRQing, because the non-masked intrs in the
125 * first set might intr again, causing multiple servicings of the
126 * same intr. This effect is mostly seen for intercpu intrs.
130 static void ip27_do_irq_mask0(void)
133 hubreg_t pend0
, mask0
;
134 cpuid_t cpu
= smp_processor_id();
136 (cputoslice(cpu
) == 0) ? PI_INT_MASK0_A
: PI_INT_MASK0_B
;
138 /* copied from Irix intpend0() */
139 pend0
= LOCAL_HUB_L(PI_INT_PEND0
);
140 mask0
= LOCAL_HUB_L(pi_int_mask0
);
142 pend0
&= mask0
; /* Pick intrs we should look at */
146 swlevel
= ms1bit(pend0
);
148 if (pend0
& (1UL << CPU_RESCHED_A_IRQ
)) {
149 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ
);
150 } else if (pend0
& (1UL << CPU_RESCHED_B_IRQ
)) {
151 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ
);
152 } else if (pend0
& (1UL << CPU_CALL_A_IRQ
)) {
153 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ
);
154 smp_call_function_interrupt();
155 } else if (pend0
& (1UL << CPU_CALL_B_IRQ
)) {
156 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ
);
157 smp_call_function_interrupt();
161 /* "map" swlevel to irq */
162 struct slice_data
*si
= cpu_data
[cpu
].data
;
164 irq
= si
->level_to_irq
[swlevel
];
168 LOCAL_HUB_L(PI_INT_PEND0
);
171 static void ip27_do_irq_mask1(void)
174 hubreg_t pend1
, mask1
;
175 cpuid_t cpu
= smp_processor_id();
176 int pi_int_mask1
= (cputoslice(cpu
) == 0) ? PI_INT_MASK1_A
: PI_INT_MASK1_B
;
177 struct slice_data
*si
= cpu_data
[cpu
].data
;
179 /* copied from Irix intpend0() */
180 pend1
= LOCAL_HUB_L(PI_INT_PEND1
);
181 mask1
= LOCAL_HUB_L(pi_int_mask1
);
183 pend1
&= mask1
; /* Pick intrs we should look at */
187 swlevel
= ms1bit(pend1
);
188 /* "map" swlevel to irq */
189 irq
= si
->level_to_irq
[swlevel
];
190 LOCAL_HUB_CLR_INTR(swlevel
);
193 LOCAL_HUB_L(PI_INT_PEND1
);
196 static void ip27_prof_timer(void)
198 panic("CPU %d got a profiling interrupt", smp_processor_id());
201 static void ip27_hub_error(void)
203 panic("CPU %d got a hub error interrupt", smp_processor_id());
206 static int intr_connect_level(int cpu
, int bit
)
208 nasid_t nasid
= COMPACT_TO_NASID_NODEID(cpu_to_node(cpu
));
209 struct slice_data
*si
= cpu_data
[cpu
].data
;
212 set_bit(bit
, si
->irq_enable_mask
);
214 local_irq_save(flags
);
215 if (!cputoslice(cpu
)) {
216 REMOTE_HUB_S(nasid
, PI_INT_MASK0_A
, si
->irq_enable_mask
[0]);
217 REMOTE_HUB_S(nasid
, PI_INT_MASK1_A
, si
->irq_enable_mask
[1]);
219 REMOTE_HUB_S(nasid
, PI_INT_MASK0_B
, si
->irq_enable_mask
[0]);
220 REMOTE_HUB_S(nasid
, PI_INT_MASK1_B
, si
->irq_enable_mask
[1]);
222 local_irq_restore(flags
);
227 static int intr_disconnect_level(int cpu
, int bit
)
229 nasid_t nasid
= COMPACT_TO_NASID_NODEID(cpu_to_node(cpu
));
230 struct slice_data
*si
= cpu_data
[cpu
].data
;
232 clear_bit(bit
, si
->irq_enable_mask
);
234 if (!cputoslice(cpu
)) {
235 REMOTE_HUB_S(nasid
, PI_INT_MASK0_A
, si
->irq_enable_mask
[0]);
236 REMOTE_HUB_S(nasid
, PI_INT_MASK1_A
, si
->irq_enable_mask
[1]);
238 REMOTE_HUB_S(nasid
, PI_INT_MASK0_B
, si
->irq_enable_mask
[0]);
239 REMOTE_HUB_S(nasid
, PI_INT_MASK1_B
, si
->irq_enable_mask
[1]);
245 /* Startup one of the (PCI ...) IRQs routes over a bridge. */
246 static unsigned int startup_bridge_irq(unsigned int irq
)
248 struct bridge_controller
*bc
;
254 pin
= SLOT_FROM_PCI_IRQ(irq
);
255 bc
= IRQ_TO_BRIDGE(irq
);
258 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq
, pin
);
260 * "map" irq to a swlevel greater than 6 since the first 6 bits
261 * of INT_PEND0 are taken
263 swlevel
= find_level(&cpu
, irq
);
264 bridge
->b_int_addr
[pin
].addr
= (0x20000 | swlevel
| (bc
->nasid
<< 8));
265 bridge
->b_int_enable
|= (1 << pin
);
266 bridge
->b_int_enable
|= 0x7ffffe00; /* more stuff in int_enable */
269 * Enable sending of an interrupt clear packt to the hub on a high to
270 * low transition of the interrupt pin.
272 * IRIX sets additional bits in the address which are documented as
273 * reserved in the bridge docs.
275 bridge
->b_int_mode
|= (1UL << pin
);
278 * We assume the bridge to have a 1:1 mapping between devices
279 * (slots) and intr pins.
281 device
= bridge
->b_int_device
;
282 device
&= ~(7 << (pin
*3));
283 device
|= (pin
<< (pin
*3));
284 bridge
->b_int_device
= device
;
286 bridge
->b_wid_tflush
;
288 intr_connect_level(cpu
, swlevel
);
290 return 0; /* Never anything pending. */
293 /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
294 static void shutdown_bridge_irq(unsigned int irq
)
296 struct bridge_controller
*bc
= IRQ_TO_BRIDGE(irq
);
297 bridge_t
*bridge
= bc
->base
;
301 pr_debug("bridge_shutdown: irq 0x%x\n", irq
);
302 pin
= SLOT_FROM_PCI_IRQ(irq
);
305 * map irq to a swlevel greater than 6 since the first 6 bits
306 * of INT_PEND0 are taken
308 swlevel
= find_level(&cpu
, irq
);
309 intr_disconnect_level(cpu
, swlevel
);
311 bridge
->b_int_enable
&= ~(1 << pin
);
312 bridge
->b_wid_tflush
;
315 static inline void enable_bridge_irq(unsigned int irq
)
320 swlevel
= find_level(&cpu
, irq
); /* Criminal offence */
321 intr_connect_level(cpu
, swlevel
);
324 static inline void disable_bridge_irq(unsigned int irq
)
329 swlevel
= find_level(&cpu
, irq
); /* Criminal offence */
330 intr_disconnect_level(cpu
, swlevel
);
333 static struct irq_chip bridge_irq_type
= {
335 .startup
= startup_bridge_irq
,
336 .shutdown
= shutdown_bridge_irq
,
337 .ack
= disable_bridge_irq
,
338 .mask
= disable_bridge_irq
,
339 .mask_ack
= disable_bridge_irq
,
340 .unmask
= enable_bridge_irq
,
343 void __devinit
register_bridge_irq(unsigned int irq
)
345 set_irq_chip_and_handler(irq
, &bridge_irq_type
, handle_level_irq
);
348 int __devinit
request_bridge_irq(struct bridge_controller
*bc
)
350 int irq
= allocate_irqno();
358 * "map" irq to a swlevel greater than 6 since the first 6 bits
359 * of INT_PEND0 are taken
362 swlevel
= alloc_level(cpu
, irq
);
363 if (unlikely(swlevel
< 0)) {
369 /* Make sure it's not already pending when we connect it. */
370 nasid
= COMPACT_TO_NASID_NODEID(cpu_to_node(cpu
));
371 REMOTE_HUB_CLR_INTR(nasid
, swlevel
);
373 intr_connect_level(cpu
, swlevel
);
375 register_bridge_irq(irq
);
380 extern void ip27_rt_timer_interrupt(void);
382 asmlinkage
void plat_irq_dispatch(void)
384 unsigned long pending
= read_c0_cause() & read_c0_status();
386 if (pending
& CAUSEF_IP4
)
387 ip27_rt_timer_interrupt();
388 else if (pending
& CAUSEF_IP2
) /* PI_INT_PEND_0 or CC_PEND_{A|B} */
390 else if (pending
& CAUSEF_IP3
) /* PI_INT_PEND_1 */
392 else if (pending
& CAUSEF_IP5
)
394 else if (pending
& CAUSEF_IP6
)
398 void __init
arch_init_irq(void)
402 void install_ipi(void)
404 int slice
= LOCAL_HUB_L(PI_CPU_NUM
);
405 int cpu
= smp_processor_id();
406 struct slice_data
*si
= cpu_data
[cpu
].data
;
407 struct hub_data
*hub
= hub_data(cpu_to_node(cpu
));
410 resched
= CPU_RESCHED_A_IRQ
+ slice
;
411 __set_bit(resched
, hub
->irq_alloc_mask
);
412 __set_bit(resched
, si
->irq_enable_mask
);
413 LOCAL_HUB_CLR_INTR(resched
);
415 call
= CPU_CALL_A_IRQ
+ slice
;
416 __set_bit(call
, hub
->irq_alloc_mask
);
417 __set_bit(call
, si
->irq_enable_mask
);
418 LOCAL_HUB_CLR_INTR(call
);
421 LOCAL_HUB_S(PI_INT_MASK0_A
, si
->irq_enable_mask
[0]);
422 LOCAL_HUB_S(PI_INT_MASK1_A
, si
->irq_enable_mask
[1]);
424 LOCAL_HUB_S(PI_INT_MASK0_B
, si
->irq_enable_mask
[0]);
425 LOCAL_HUB_S(PI_INT_MASK1_B
, si
->irq_enable_mask
[1]);
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