arch/mips/sibyte/bcm1480/irq.c

   1 /*
   2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mm.h>
  24 #include <linux/slab.h>
  25 #include <linux/kernel_stat.h>
  26
  27 #include <asm/errno.h>
  28 #include <asm/irq_regs.h>
  29 #include <asm/signal.h>
  30 #include <asm/system.h>
  31 #include <asm/io.h>
  32
  33 #include <asm/sibyte/bcm1480_regs.h>
  34 #include <asm/sibyte/bcm1480_int.h>
  35 #include <asm/sibyte/bcm1480_scd.h>
  36
  37 #include <asm/sibyte/sb1250_uart.h>
  38 #include <asm/sibyte/sb1250.h>
  39
  40 /*
  41  * These are the routines that handle all the low level interrupt stuff.
  42  * Actions handled here are: initialization of the interrupt map, requesting of
  43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44  * for interrupt lines
  45  */
  46
  47
  48 static void end_bcm1480_irq(unsigned int irq);
  49 static void enable_bcm1480_irq(unsigned int irq);
  50 static void disable_bcm1480_irq(unsigned int irq);
  51 static void ack_bcm1480_irq(unsigned int irq);
  52 #ifdef CONFIG_SMP
  53 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
  54 #endif
  55
  56 #ifdef CONFIG_PCI
  57 extern unsigned long ht_eoi_space;
  58 #endif
  59
  60 static struct irq_chip bcm1480_irq_type = {
  61         .name = "BCM1480-IMR",
  62         .ack = ack_bcm1480_irq,
  63         .mask = disable_bcm1480_irq,
  64         .mask_ack = ack_bcm1480_irq,
  65         .unmask = enable_bcm1480_irq,
  66         .end = end_bcm1480_irq,
  67 #ifdef CONFIG_SMP
  68         .set_affinity = bcm1480_set_affinity
  69 #endif
  70 };
  71
  72 /* Store the CPU id (not the logical number) */
  73 int bcm1480_irq_owner[BCM1480_NR_IRQS];
  74
  75 DEFINE_SPINLOCK(bcm1480_imr_lock);
  76
  77 void bcm1480_mask_irq(int cpu, int irq)
  78 {
  79         unsigned long flags, hl_spacing;
  80         u64 cur_ints;
  81
  82         spin_lock_irqsave(&bcm1480_imr_lock, flags);
  83         hl_spacing = 0;
  84         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
  85                 hl_spacing = BCM1480_IMR_HL_SPACING;
  86                 irq -= BCM1480_NR_IRQS_HALF;
  87         }
  88         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
  89         cur_ints |= (((u64) 1) << irq);
  90         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
  91         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
  92 }
  93
  94 void bcm1480_unmask_irq(int cpu, int irq)
  95 {
  96         unsigned long flags, hl_spacing;
  97         u64 cur_ints;
  98
  99         spin_lock_irqsave(&bcm1480_imr_lock, flags);
 100         hl_spacing = 0;
 101         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
 102                 hl_spacing = BCM1480_IMR_HL_SPACING;
 103                 irq -= BCM1480_NR_IRQS_HALF;
 104         }
 105         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 106         cur_ints &= ~(((u64) 1) << irq);
 107         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 108         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 109 }
 110
 111 #ifdef CONFIG_SMP
 112 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
 113 {
 114         int i = 0, old_cpu, cpu, int_on, k;
 115         u64 cur_ints;
 116         struct irq_desc *desc = irq_desc + irq;
 117         unsigned long flags;
 118         unsigned int irq_dirty;
 119
 120         if (cpumask_weight(mask) != 1) {
 121                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 122                 return -1;
 123         }
 124         i = cpumask_first(mask);
 125
 126         /* Convert logical CPU to physical CPU */
 127         cpu = cpu_logical_map(i);
 128
 129         /* Protect against other affinity changers and IMR manipulation */
 130         spin_lock_irqsave(&desc->lock, flags);
 131         spin_lock(&bcm1480_imr_lock);
 132
 133         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 134         old_cpu = bcm1480_irq_owner[irq];
 135         irq_dirty = irq;
 136         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 137                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 138         }
 139
 140         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
 141                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 142                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
 143                 if (int_on) {
 144                         /* If it was on, mask it */
 145                         cur_ints |= (((u64) 1) << irq_dirty);
 146                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 147                 }
 148                 bcm1480_irq_owner[irq] = cpu;
 149                 if (int_on) {
 150                         /* unmask for the new CPU */
 151                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 152                         cur_ints &= ~(((u64) 1) << irq_dirty);
 153                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 154                 }
 155         }
 156         spin_unlock(&bcm1480_imr_lock);
 157         spin_unlock_irqrestore(&desc->lock, flags);
 158
 159         return 0;
 160 }
 161 #endif
 162
 163
 164 /*****************************************************************************/
 165
 166 static void disable_bcm1480_irq(unsigned int irq)
 167 {
 168         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 169 }
 170
 171 static void enable_bcm1480_irq(unsigned int irq)
 172 {
 173         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 174 }
 175
 176
 177 static void ack_bcm1480_irq(unsigned int irq)
 178 {
 179         u64 pending;
 180         unsigned int irq_dirty;
 181         int k;
 182
 183         /*
 184          * If the interrupt was an HT interrupt, now is the time to
 185          * clear it.  NOTE: we assume the HT bridge was set up to
 186          * deliver the interrupts to all CPUs (which makes affinity
 187          * changing easier for us)
 188          */
 189         irq_dirty = irq;
 190         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 191                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 192         }
 193         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
 194                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
 195                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
 196                 pending &= ((u64)1 << (irq_dirty));
 197                 if (pending) {
 198 #ifdef CONFIG_SMP
 199                         int i;
 200                         for (i=0; i<NR_CPUS; i++) {
 201                                 /*
 202                                  * Clear for all CPUs so an affinity switch
 203                                  * doesn't find an old status
 204                                  */
 205                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
 206                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 207                         }
 208 #else
 209                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 210 #endif
 211
 212                         /*
 213                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 214                          * Pass 2, the LDT world may be edge-triggered, but
 215                          * this EOI shouldn't hurt.  If they are
 216                          * level-sensitive, the EOI is required.
 217                          */
 218 #ifdef CONFIG_PCI
 219                         if (ht_eoi_space)
 220                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
 221 #endif
 222                 }
 223         }
 224         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 225 }
 226
 227
 228 static void end_bcm1480_irq(unsigned int irq)
 229 {
 230         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 231                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 232         }
 233 }
 234
 235
 236 void __init init_bcm1480_irqs(void)
 237 {
 238         int i;
 239
 240         for (i = 0; i < BCM1480_NR_IRQS; i++) {
 241                 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
 242                 bcm1480_irq_owner[i] = 0;
 243         }
 244 }
 245
 246 /*
 247  *  init_IRQ is called early in the boot sequence from init/main.c.  It
 248  *  is responsible for setting up the interrupt mapper and installing the
 249  *  handler that will be responsible for dispatching interrupts to the
 250  *  "right" place.
 251  */
 252 /*
 253  * For now, map all interrupts to IP[2].  We could save
 254  * some cycles by parceling out system interrupts to different
 255  * IP lines, but keep it simple for bringup.  We'll also direct
 256  * all interrupts to a single CPU; we should probably route
 257  * PCI and LDT to one cpu and everything else to the other
 258  * to balance the load a bit.
 259  *
 260  * On the second cpu, everything is set to IP5, which is
 261  * ignored, EXCEPT the mailbox interrupt.  That one is
 262  * set to IP[2] so it is handled.  This is needed so we
 263  * can do cross-cpu function calls, as requred by SMP
 264  */
 265
 266 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
 267 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
 268 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
 269 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
 270 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
 271
 272 void __init arch_init_irq(void)
 273 {
 274         unsigned int i, cpu;
 275         u64 tmp;
 276         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 277                 STATUSF_IP1 | STATUSF_IP0;
 278
 279         /* Default everything to IP2 */
 280         /* Start with _high registers which has no bit 0 interrupt source */
 281         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
 282                 for (cpu = 0; cpu < 4; cpu++) {
 283                         __raw_writeq(IMR_IP2_VAL,
 284                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 285                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
 286                 }
 287         }
 288
 289         /* Now do _low registers */
 290         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
 291                 for (cpu = 0; cpu < 4; cpu++) {
 292                         __raw_writeq(IMR_IP2_VAL,
 293                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 294                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
 295                 }
 296         }
 297
 298         init_bcm1480_irqs();
 299
 300         /*
 301          * Map the high 16 bits of mailbox_0 registers to IP[3], for
 302          * inter-cpu messages
 303          */
 304         /* Was I1 */
 305         for (cpu = 0; cpu < 4; cpu++) {
 306                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
 307                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
 308         }
 309
 310
 311         /* Clear the mailboxes.  The firmware may leave them dirty */
 312         for (cpu = 0; cpu < 4; cpu++) {
 313                 __raw_writeq(0xffffffffffffffffULL,
 314                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
 315                 __raw_writeq(0xffffffffffffffffULL,
 316                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
 317         }
 318
 319
 320         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
 321         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
 322         for (cpu = 0; cpu < 4; cpu++) {
 323                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
 324         }
 325         tmp = ~((u64) 0);
 326         for (cpu = 0; cpu < 4; cpu++) {
 327                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
 328         }
 329
 330         /*
 331          * Note that the timer interrupts are also mapped, but this is
 332          * done in bcm1480_time_init().  Also, the profiling driver
 333          * does its own management of IP7.
 334          */
 335
 336         /* Enable necessary IPs, disable the rest */
 337         change_c0_status(ST0_IM, imask);
 338 }
 339
 340 extern void bcm1480_mailbox_interrupt(void);
 341
 342 static inline void dispatch_ip2(void)
 343 {
 344         unsigned long long mask_h, mask_l;
 345         unsigned int cpu = smp_processor_id();
 346         unsigned long base;
 347
 348         /*
 349          * Default...we've hit an IP[2] interrupt, which means we've got to
 350          * check the 1480 interrupt registers to figure out what to do.  Need
 351          * to detect which CPU we're on, now that smp_affinity is supported.
 352          */
 353         base = A_BCM1480_IMR_MAPPER(cpu);
 354         mask_h = __raw_readq(
 355                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
 356         mask_l = __raw_readq(
 357                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
 358
 359         if (mask_h) {
 360                 if (mask_h ^ 1)
 361                         do_IRQ(fls64(mask_h) - 1);
 362                 else if (mask_l)
 363                         do_IRQ(63 + fls64(mask_l));
 364         }
 365 }
 366
 367 asmlinkage void plat_irq_dispatch(void)
 368 {
 369         unsigned int cpu = smp_processor_id();
 370         unsigned int pending;
 371
 372 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 373         /* Set compare to count to silence count/compare timer interrupts */
 374         write_c0_compare(read_c0_count());
 375 #endif
 376
 377         pending = read_c0_cause() & read_c0_status();
 378
 379 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 380         if (pending & CAUSEF_IP7)       /* Cpu performance counter interrupt */
 381                 sbprof_cpu_intr();
 382         else
 383 #endif
 384
 385         if (pending & CAUSEF_IP4)
 386                 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
 387 #ifdef CONFIG_SMP
 388         else if (pending & CAUSEF_IP3)
 389                 bcm1480_mailbox_interrupt();
 390 #endif
 391
 392         else if (pending & CAUSEF_IP2)
 393                 dispatch_ip2();
 394 }