arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29                 pci2 = &pci2;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 PowerPC,8548@0 {
  37                         device_type = "cpu";
  38                         reg = <0x0>;
  39                         d-cache-line-size = <32>;       // 32 bytes
  40                         i-cache-line-size = <32>;       // 32 bytes
  41                         d-cache-size = <0x8000>;                // L1, 32K
  42                         i-cache-size = <0x8000>;                // L1, 32K
  43                         timebase-frequency = <0>;       //  33 MHz, from uboot
  44                         bus-frequency = <0>;    // 166 MHz
  45                         clock-frequency = <0>;  // 825 MHz, from uboot
  46                         next-level-cache = <&L2>;
  47                 };
  48         };
  49
  50         memory {
  51                 device_type = "memory";
  52                 reg = <0x0 0x8000000>;  // 128M at 0x0
  53         };
  54
  55         soc8548@e0000000 {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 device_type = "soc";
  59                 compatible = "simple-bus";
  60                 ranges = <0x0 0xe0000000 0x100000>;
  61                 bus-frequency = <0>;
  62
  63                 ecm-law@0 {
  64                         compatible = "fsl,ecm-law";
  65                         reg = <0x0 0x1000>;
  66                         fsl,num-laws = <10>;
  67                 };
  68
  69                 ecm@1000 {
  70                         compatible = "fsl,mpc8548-ecm", "fsl,ecm";
  71                         reg = <0x1000 0x1000>;
  72                         interrupts = <17 2>;
  73                         interrupt-parent = <&mpic>;
  74                 };
  75
  76                 memory-controller@2000 {
  77                         compatible = "fsl,8548-memory-controller";
  78                         reg = <0x2000 0x1000>;
  79                         interrupt-parent = <&mpic>;
  80                         interrupts = <18 2>;
  81                 };
  82
  83                 L2: l2-cache-controller@20000 {
  84                         compatible = "fsl,8548-l2-cache-controller";
  85                         reg = <0x20000 0x1000>;
  86                         cache-line-size = <32>; // 32 bytes
  87                         cache-size = <0x80000>; // L2, 512K
  88                         interrupt-parent = <&mpic>;
  89                         interrupts = <16 2>;
  90                 };
  91
  92                 i2c@3000 {
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         cell-index = <0>;
  96                         compatible = "fsl-i2c";
  97                         reg = <0x3000 0x100>;
  98                         interrupts = <43 2>;
  99                         interrupt-parent = <&mpic>;
 100                         dfsrr;
 101
 102                         eeprom@50 {
 103                                 compatible = "atmel,24c64";
 104                                 reg = <0x50>;
 105                         };
 106
 107                         eeprom@56 {
 108                                 compatible = "atmel,24c64";
 109                                 reg = <0x56>;
 110                         };
 111
 112                         eeprom@57 {
 113                                 compatible = "atmel,24c64";
 114                                 reg = <0x57>;
 115                         };
 116                 };
 117
 118                 i2c@3100 {
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         cell-index = <1>;
 122                         compatible = "fsl-i2c";
 123                         reg = <0x3100 0x100>;
 124                         interrupts = <43 2>;
 125                         interrupt-parent = <&mpic>;
 126                         dfsrr;
 127
 128                         eeprom@50 {
 129                                 compatible = "atmel,24c64";
 130                                 reg = <0x50>;
 131                         };
 132                 };
 133
 134                 dma@21300 {
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 138                         reg = <0x21300 0x4>;
 139                         ranges = <0x0 0x21100 0x200>;
 140                         cell-index = <0>;
 141                         dma-channel@0 {
 142                                 compatible = "fsl,mpc8548-dma-channel",
 143                                                 "fsl,eloplus-dma-channel";
 144                                 reg = <0x0 0x80>;
 145                                 cell-index = <0>;
 146                                 interrupt-parent = <&mpic>;
 147                                 interrupts = <20 2>;
 148                         };
 149                         dma-channel@80 {
 150                                 compatible = "fsl,mpc8548-dma-channel",
 151                                                 "fsl,eloplus-dma-channel";
 152                                 reg = <0x80 0x80>;
 153                                 cell-index = <1>;
 154                                 interrupt-parent = <&mpic>;
 155                                 interrupts = <21 2>;
 156                         };
 157                         dma-channel@100 {
 158                                 compatible = "fsl,mpc8548-dma-channel",
 159                                                 "fsl,eloplus-dma-channel";
 160                                 reg = <0x100 0x80>;
 161                                 cell-index = <2>;
 162                                 interrupt-parent = <&mpic>;
 163                                 interrupts = <22 2>;
 164                         };
 165                         dma-channel@180 {
 166                                 compatible = "fsl,mpc8548-dma-channel",
 167                                                 "fsl,eloplus-dma-channel";
 168                                 reg = <0x180 0x80>;
 169                                 cell-index = <3>;
 170                                 interrupt-parent = <&mpic>;
 171                                 interrupts = <23 2>;
 172                         };
 173                 };
 174
 175                 enet0: ethernet@24000 {
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178                         cell-index = <0>;
 179                         device_type = "network";
 180                         model = "eTSEC";
 181                         compatible = "gianfar";
 182                         reg = <0x24000 0x1000>;
 183                         ranges = <0x0 0x24000 0x1000>;
 184                         local-mac-address = [ 00 00 00 00 00 00 ];
 185                         interrupts = <29 2 30 2 34 2>;
 186                         interrupt-parent = <&mpic>;
 187                         tbi-handle = <&tbi0>;
 188                         phy-handle = <&phy0>;
 189
 190                         mdio@520 {
 191                                 #address-cells = <1>;
 192                                 #size-cells = <0>;
 193                                 compatible = "fsl,gianfar-mdio";
 194                                 reg = <0x520 0x20>;
 195
 196                                 phy0: ethernet-phy@0 {
 197                                         interrupt-parent = <&mpic>;
 198                                         interrupts = <5 1>;
 199                                         reg = <0x0>;
 200                                         device_type = "ethernet-phy";
 201                                 };
 202                                 phy1: ethernet-phy@1 {
 203                                         interrupt-parent = <&mpic>;
 204                                         interrupts = <5 1>;
 205                                         reg = <0x1>;
 206                                         device_type = "ethernet-phy";
 207                                 };
 208                                 phy2: ethernet-phy@2 {
 209                                         interrupt-parent = <&mpic>;
 210                                         interrupts = <5 1>;
 211                                         reg = <0x2>;
 212                                         device_type = "ethernet-phy";
 213                                 };
 214                                 phy3: ethernet-phy@3 {
 215                                         interrupt-parent = <&mpic>;
 216                                         interrupts = <5 1>;
 217                                         reg = <0x3>;
 218                                         device_type = "ethernet-phy";
 219                                 };
 220                                 tbi0: tbi-phy@11 {
 221                                         reg = <0x11>;
 222                                         device_type = "tbi-phy";
 223                                 };
 224                         };
 225                 };
 226
 227                 enet1: ethernet@25000 {
 228                         #address-cells = <1>;
 229                         #size-cells = <1>;
 230                         cell-index = <1>;
 231                         device_type = "network";
 232                         model = "eTSEC";
 233                         compatible = "gianfar";
 234                         reg = <0x25000 0x1000>;
 235                         ranges = <0x0 0x25000 0x1000>;
 236                         local-mac-address = [ 00 00 00 00 00 00 ];
 237                         interrupts = <35 2 36 2 40 2>;
 238                         interrupt-parent = <&mpic>;
 239                         tbi-handle = <&tbi1>;
 240                         phy-handle = <&phy1>;
 241
 242                         mdio@520 {
 243                                 #address-cells = <1>;
 244                                 #size-cells = <0>;
 245                                 compatible = "fsl,gianfar-tbi";
 246                                 reg = <0x520 0x20>;
 247
 248                                 tbi1: tbi-phy@11 {
 249                                         reg = <0x11>;
 250                                         device_type = "tbi-phy";
 251                                 };
 252                         };
 253                 };
 254
 255                 enet2: ethernet@26000 {
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         cell-index = <2>;
 259                         device_type = "network";
 260                         model = "eTSEC";
 261                         compatible = "gianfar";
 262                         reg = <0x26000 0x1000>;
 263                         ranges = <0x0 0x26000 0x1000>;
 264                         local-mac-address = [ 00 00 00 00 00 00 ];
 265                         interrupts = <31 2 32 2 33 2>;
 266                         interrupt-parent = <&mpic>;
 267                         tbi-handle = <&tbi2>;
 268                         phy-handle = <&phy2>;
 269
 270                         mdio@520 {
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273                                 compatible = "fsl,gianfar-tbi";
 274                                 reg = <0x520 0x20>;
 275
 276                                 tbi2: tbi-phy@11 {
 277                                         reg = <0x11>;
 278                                         device_type = "tbi-phy";
 279                                 };
 280                         };
 281                 };
 282
 283                 enet3: ethernet@27000 {
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         cell-index = <3>;
 287                         device_type = "network";
 288                         model = "eTSEC";
 289                         compatible = "gianfar";
 290                         reg = <0x27000 0x1000>;
 291                         ranges = <0x0 0x27000 0x1000>;
 292                         local-mac-address = [ 00 00 00 00 00 00 ];
 293                         interrupts = <37 2 38 2 39 2>;
 294                         interrupt-parent = <&mpic>;
 295                         tbi-handle = <&tbi3>;
 296                         phy-handle = <&phy3>;
 297
 298                         mdio@520 {
 299                                 #address-cells = <1>;
 300                                 #size-cells = <0>;
 301                                 compatible = "fsl,gianfar-tbi";
 302                                 reg = <0x520 0x20>;
 303
 304                                 tbi3: tbi-phy@11 {
 305                                         reg = <0x11>;
 306                                         device_type = "tbi-phy";
 307                                 };
 308                         };
 309                 };
 310
 311                 serial0: serial@4500 {
 312                         cell-index = <0>;
 313                         device_type = "serial";
 314                         compatible = "ns16550";
 315                         reg = <0x4500 0x100>;   // reg base, size
 316                         clock-frequency = <0>;  // should we fill in in uboot?
 317                         interrupts = <42 2>;
 318                         interrupt-parent = <&mpic>;
 319                 };
 320
 321                 serial1: serial@4600 {
 322                         cell-index = <1>;
 323                         device_type = "serial";
 324                         compatible = "ns16550";
 325                         reg = <0x4600 0x100>;   // reg base, size
 326                         clock-frequency = <0>;  // should we fill in in uboot?
 327                         interrupts = <42 2>;
 328                         interrupt-parent = <&mpic>;
 329                 };
 330
 331                 global-utilities@e0000 {        //global utilities reg
 332                         compatible = "fsl,mpc8548-guts";
 333                         reg = <0xe0000 0x1000>;
 334                         fsl,has-rstcr;
 335                 };
 336
 337                 crypto@30000 {
 338                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 339                         reg = <0x30000 0x10000>;
 340                         interrupts = <45 2>;
 341                         interrupt-parent = <&mpic>;
 342                         fsl,num-channels = <4>;
 343                         fsl,channel-fifo-len = <24>;
 344                         fsl,exec-units-mask = <0xfe>;
 345                         fsl,descriptor-types-mask = <0x12b0ebf>;
 346                 };
 347
 348                 mpic: pic@40000 {
 349                         interrupt-controller;
 350                         #address-cells = <0>;
 351                         #interrupt-cells = <2>;
 352                         reg = <0x40000 0x40000>;
 353                         compatible = "chrp,open-pic";
 354                         device_type = "open-pic";
 355                 };
 356         };
 357
 358         pci0: pci@e0008000 {
 359                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 360                 interrupt-map = <
 361                         /* IDSEL 0x4 (PCIX Slot 2) */
 362                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 363                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 364                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 365                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 366
 367                         /* IDSEL 0x5 (PCIX Slot 3) */
 368                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 369                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
 370                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
 371                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 372
 373                         /* IDSEL 0x6 (PCIX Slot 4) */
 374                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 375                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 376                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 377                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 378
 379                         /* IDSEL 0x8 (PCIX Slot 5) */
 380                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
 381                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
 382                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
 383                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 384
 385                         /* IDSEL 0xC (Tsi310 bridge) */
 386                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
 387                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
 388                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
 389                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 390
 391                         /* IDSEL 0x14 (Slot 2) */
 392                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
 393                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
 394                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
 395                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 396
 397                         /* IDSEL 0x15 (Slot 3) */
 398                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
 399                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
 400                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
 401                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 402
 403                         /* IDSEL 0x16 (Slot 4) */
 404                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
 405                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
 406                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
 407                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 408
 409                         /* IDSEL 0x18 (Slot 5) */
 410                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
 411                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
 412                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
 413                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 414
 415                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 416                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
 417                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
 418                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
 419                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 420
 421                 interrupt-parent = <&mpic>;
 422                 interrupts = <24 2>;
 423                 bus-range = <0 0>;
 424                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 425                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 426                 clock-frequency = <66666666>;
 427                 #interrupt-cells = <1>;
 428                 #size-cells = <2>;
 429                 #address-cells = <3>;
 430                 reg = <0xe0008000 0x1000>;
 431                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 432                 device_type = "pci";
 433
 434                 pci_bridge@1c {
 435                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 436                         interrupt-map = <
 437
 438                                 /* IDSEL 0x00 (PrPMC Site) */
 439                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
 440                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
 441                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
 442                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
 443
 444                                 /* IDSEL 0x04 (VIA chip) */
 445                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 446                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 447                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 448                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 449
 450                                 /* IDSEL 0x05 (8139) */
 451                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 452
 453                                 /* IDSEL 0x06 (Slot 6) */
 454                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 455                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 456                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 457                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 458
 459                                 /* IDESL 0x07 (Slot 7) */
 460                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
 461                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
 462                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
 463                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 464
 465                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 466                         #interrupt-cells = <1>;
 467                         #size-cells = <2>;
 468                         #address-cells = <3>;
 469                         ranges = <0x2000000 0x0 0x80000000
 470                                   0x2000000 0x0 0x80000000
 471                                   0x0 0x20000000
 472                                   0x1000000 0x0 0x0
 473                                   0x1000000 0x0 0x0
 474                                   0x0 0x80000>;
 475                         clock-frequency = <33333333>;
 476
 477                         isa@4 {
 478                                 device_type = "isa";
 479                                 #interrupt-cells = <2>;
 480                                 #size-cells = <1>;
 481                                 #address-cells = <2>;
 482                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 483                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 484                                 interrupt-parent = <&i8259>;
 485
 486                                 i8259: interrupt-controller@20 {
 487                                         interrupt-controller;
 488                                         device_type = "interrupt-controller";
 489                                         reg = <0x1 0x20 0x2
 490                                                0x1 0xa0 0x2
 491                                                0x1 0x4d0 0x2>;
 492                                         #address-cells = <0>;
 493                                         #interrupt-cells = <2>;
 494                                         compatible = "chrp,iic";
 495                                         interrupts = <0 1>;
 496                                         interrupt-parent = <&mpic>;
 497                                 };
 498
 499                                 rtc@70 {
 500                                         compatible = "pnpPNP,b00";
 501                                         reg = <0x1 0x70 0x2>;
 502                                 };
 503                         };
 504                 };
 505         };
 506
 507         pci1: pci@e0009000 {
 508                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 509                 interrupt-map = <
 510
 511                         /* IDSEL 0x15 */
 512                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 513                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
 514                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
 515                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 516
 517                 interrupt-parent = <&mpic>;
 518                 interrupts = <25 2>;
 519                 bus-range = <0 0>;
 520                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 521                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 522                 clock-frequency = <66666666>;
 523                 #interrupt-cells = <1>;
 524                 #size-cells = <2>;
 525                 #address-cells = <3>;
 526                 reg = <0xe0009000 0x1000>;
 527                 compatible = "fsl,mpc8540-pci";
 528                 device_type = "pci";
 529         };
 530
 531         pci2: pcie@e000a000 {
 532                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 533                 interrupt-map = <
 534
 535                         /* IDSEL 0x0 (PEX) */
 536                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 537                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 538                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 539                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 540
 541                 interrupt-parent = <&mpic>;
 542                 interrupts = <26 2>;
 543                 bus-range = <0 255>;
 544                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 545                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 546                 clock-frequency = <33333333>;
 547                 #interrupt-cells = <1>;
 548                 #size-cells = <2>;
 549                 #address-cells = <3>;
 550                 reg = <0xe000a000 0x1000>;
 551                 compatible = "fsl,mpc8548-pcie";
 552                 device_type = "pci";
 553                 pcie@0 {
 554                         reg = <0x0 0x0 0x0 0x0 0x0>;
 555                         #size-cells = <2>;
 556                         #address-cells = <3>;
 557                         device_type = "pci";
 558                         ranges = <0x2000000 0x0 0xa0000000
 559                                   0x2000000 0x0 0xa0000000
 560                                   0x0 0x20000000
 561
 562                                   0x1000000 0x0 0x0
 563                                   0x1000000 0x0 0x0
 564                                   0x0 0x100000>;
 565                 };
 566         };
 567 };