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[POWERPC] Cleanup mpic nodes in .dts
[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8568mds.dts
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 /dts-v1/;
13
14 / {
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8568@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x0 0x10000000>;
51 };
52
53 bcsr@f8000000 {
54 device_type = "board-control";
55 reg = <0xf8000000 0x8000>;
56 };
57
58 soc8568@e0000000 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 device_type = "soc";
62 ranges = <0x0 0xe0000000 0x100000>;
63 reg = <0xe0000000 0x1000>;
64 bus-frequency = <0>;
65
66 memory-controller@2000 {
67 compatible = "fsl,8568-memory-controller";
68 reg = <0x2000 0x1000>;
69 interrupt-parent = <&mpic>;
70 interrupts = <18 2>;
71 };
72
73 l2-cache-controller@20000 {
74 compatible = "fsl,8568-l2-cache-controller";
75 reg = <0x20000 0x1000>;
76 cache-line-size = <32>; // 32 bytes
77 cache-size = <0x80000>; // L2, 512K
78 interrupt-parent = <&mpic>;
79 interrupts = <16 2>;
80 };
81
82 i2c@3000 {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 cell-index = <0>;
86 compatible = "fsl-i2c";
87 reg = <0x3000 0x100>;
88 interrupts = <43 2>;
89 interrupt-parent = <&mpic>;
90 dfsrr;
91
92 rtc@68 {
93 compatible = "dallas,ds1374";
94 reg = <0x68>;
95 };
96 };
97
98 i2c@3100 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 cell-index = <1>;
102 compatible = "fsl-i2c";
103 reg = <0x3100 0x100>;
104 interrupts = <43 2>;
105 interrupt-parent = <&mpic>;
106 dfsrr;
107 };
108
109 mdio@24520 {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "fsl,gianfar-mdio";
113 reg = <0x24520 0x20>;
114
115 phy0: ethernet-phy@7 {
116 interrupt-parent = <&mpic>;
117 interrupts = <1 1>;
118 reg = <0x7>;
119 device_type = "ethernet-phy";
120 };
121 phy1: ethernet-phy@1 {
122 interrupt-parent = <&mpic>;
123 interrupts = <2 1>;
124 reg = <0x1>;
125 device_type = "ethernet-phy";
126 };
127 phy2: ethernet-phy@2 {
128 interrupt-parent = <&mpic>;
129 interrupts = <1 1>;
130 reg = <0x2>;
131 device_type = "ethernet-phy";
132 };
133 phy3: ethernet-phy@3 {
134 interrupt-parent = <&mpic>;
135 interrupts = <2 1>;
136 reg = <0x3>;
137 device_type = "ethernet-phy";
138 };
139 };
140
141 enet0: ethernet@24000 {
142 cell-index = <0>;
143 device_type = "network";
144 model = "eTSEC";
145 compatible = "gianfar";
146 reg = <0x24000 0x1000>;
147 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <29 2 30 2 34 2>;
149 interrupt-parent = <&mpic>;
150 phy-handle = <&phy2>;
151 };
152
153 enet1: ethernet@25000 {
154 cell-index = <1>;
155 device_type = "network";
156 model = "eTSEC";
157 compatible = "gianfar";
158 reg = <0x25000 0x1000>;
159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <35 2 36 2 40 2>;
161 interrupt-parent = <&mpic>;
162 phy-handle = <&phy3>;
163 };
164
165 serial0: serial@4500 {
166 cell-index = <0>;
167 device_type = "serial";
168 compatible = "ns16550";
169 reg = <0x4500 0x100>;
170 clock-frequency = <0>;
171 interrupts = <42 2>;
172 interrupt-parent = <&mpic>;
173 };
174
175 global-utilities@e0000 { //global utilities block
176 compatible = "fsl,mpc8548-guts";
177 reg = <0xe0000 0x1000>;
178 fsl,has-rstcr;
179 };
180
181 serial1: serial@4600 {
182 cell-index = <1>;
183 device_type = "serial";
184 compatible = "ns16550";
185 reg = <0x4600 0x100>;
186 clock-frequency = <0>;
187 interrupts = <42 2>;
188 interrupt-parent = <&mpic>;
189 };
190
191 crypto@30000 {
192 device_type = "crypto";
193 model = "SEC2";
194 compatible = "talitos";
195 reg = <0x30000 0xf000>;
196 interrupts = <45 2>;
197 interrupt-parent = <&mpic>;
198 num-channels = <4>;
199 channel-fifo-len = <24>;
200 exec-units-mask = <0xfe>;
201 descriptor-types-mask = <0x12b0ebf>;
202 };
203
204 mpic: pic@40000 {
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <2>;
208 reg = <0x40000 0x40000>;
209 compatible = "chrp,open-pic";
210 device_type = "open-pic";
211 };
212
213 par_io@e0100 {
214 reg = <0xe0100 0x100>;
215 device_type = "par_io";
216 num-ports = <7>;
217
218 pio1: ucc_pin@01 {
219 pio-map = <
220 /* port pin dir open_drain assignment has_irq */
221 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
222 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
223 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
224 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
225 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
226 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
227 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
228 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
229 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
230 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
231 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
232 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
233 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
234 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
235 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
236 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
237 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
238 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
239 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
240 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
241 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
242 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
243 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
244 };
245
246 pio2: ucc_pin@02 {
247 pio-map = <
248 /* port pin dir open_drain assignment has_irq */
249 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
250 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
251 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
252 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
253 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
254 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
255 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
256 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
257 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
258 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
259 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
260 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
261 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
262 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
263 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
264 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
265 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
266 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
267 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
268 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
269 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
270 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
271 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
272 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
273 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
274 };
275 };
276 };
277
278 qe@e0080000 {
279 #address-cells = <1>;
280 #size-cells = <1>;
281 device_type = "qe";
282 compatible = "fsl,qe";
283 ranges = <0x0 0xe0080000 0x40000>;
284 reg = <0xe0080000 0x480>;
285 brg-frequency = <0>;
286 bus-frequency = <396000000>;
287
288 muram@10000 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 compatible = "fsl,qe-muram", "fsl,cpm-muram";
292 ranges = <0x0 0x10000 0x10000>;
293
294 data-only@0 {
295 compatible = "fsl,qe-muram-data",
296 "fsl,cpm-muram-data";
297 reg = <0x0 0x10000>;
298 };
299 };
300
301 spi@4c0 {
302 cell-index = <0>;
303 compatible = "fsl,spi";
304 reg = <0x4c0 0x40>;
305 interrupts = <2>;
306 interrupt-parent = <&qeic>;
307 mode = "cpu";
308 };
309
310 spi@500 {
311 cell-index = <1>;
312 compatible = "fsl,spi";
313 reg = <0x500 0x40>;
314 interrupts = <1>;
315 interrupt-parent = <&qeic>;
316 mode = "cpu";
317 };
318
319 enet2: ucc@2000 {
320 device_type = "network";
321 compatible = "ucc_geth";
322 cell-index = <1>;
323 reg = <0x2000 0x200>;
324 interrupts = <32>;
325 interrupt-parent = <&qeic>;
326 local-mac-address = [ 00 00 00 00 00 00 ];
327 rx-clock-name = "none";
328 tx-clock-name = "clk16";
329 pio-handle = <&pio1>;
330 phy-handle = <&phy0>;
331 phy-connection-type = "rgmii-id";
332 };
333
334 enet3: ucc@3000 {
335 device_type = "network";
336 compatible = "ucc_geth";
337 cell-index = <2>;
338 reg = <0x3000 0x200>;
339 interrupts = <33>;
340 interrupt-parent = <&qeic>;
341 local-mac-address = [ 00 00 00 00 00 00 ];
342 rx-clock-name = "none";
343 tx-clock-name = "clk16";
344 pio-handle = <&pio2>;
345 phy-handle = <&phy1>;
346 phy-connection-type = "rgmii-id";
347 };
348
349 mdio@2120 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <0x2120 0x18>;
353 compatible = "fsl,ucc-mdio";
354
355 /* These are the same PHYs as on
356 * gianfar's MDIO bus */
357 qe_phy0: ethernet-phy@07 {
358 interrupt-parent = <&mpic>;
359 interrupts = <1 1>;
360 reg = <0x7>;
361 device_type = "ethernet-phy";
362 };
363 qe_phy1: ethernet-phy@01 {
364 interrupt-parent = <&mpic>;
365 interrupts = <2 1>;
366 reg = <0x1>;
367 device_type = "ethernet-phy";
368 };
369 qe_phy2: ethernet-phy@02 {
370 interrupt-parent = <&mpic>;
371 interrupts = <1 1>;
372 reg = <0x2>;
373 device_type = "ethernet-phy";
374 };
375 qe_phy3: ethernet-phy@03 {
376 interrupt-parent = <&mpic>;
377 interrupts = <2 1>;
378 reg = <0x3>;
379 device_type = "ethernet-phy";
380 };
381 };
382
383 qeic: interrupt-controller@80 {
384 interrupt-controller;
385 compatible = "fsl,qe-ic";
386 #address-cells = <0>;
387 #interrupt-cells = <1>;
388 reg = <0x80 0x80>;
389 big-endian;
390 interrupts = <46 2 46 2>; //high:30 low:30
391 interrupt-parent = <&mpic>;
392 };
393
394 };
395
396 pci0: pci@e0008000 {
397 cell-index = <0>;
398 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = <
400 /* IDSEL 0x12 AD18 */
401 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
402 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
403 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
404 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
405
406 /* IDSEL 0x13 AD19 */
407 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
408 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
409 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
410 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
411
412 interrupt-parent = <&mpic>;
413 interrupts = <24 2>;
414 bus-range = <0 255>;
415 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
416 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
417 clock-frequency = <66666666>;
418 #interrupt-cells = <1>;
419 #size-cells = <2>;
420 #address-cells = <3>;
421 reg = <0xe0008000 0x1000>;
422 compatible = "fsl,mpc8540-pci";
423 device_type = "pci";
424 };
425
426 /* PCI Express */
427 pci1: pcie@e000a000 {
428 cell-index = <2>;
429 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
430 interrupt-map = <
431
432 /* IDSEL 0x0 (PEX) */
433 00000 0x0 0x0 0x1 &mpic 0x0 0x1
434 00000 0x0 0x0 0x2 &mpic 0x1 0x1
435 00000 0x0 0x0 0x3 &mpic 0x2 0x1
436 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
437
438 interrupt-parent = <&mpic>;
439 interrupts = <26 2>;
440 bus-range = <0 255>;
441 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
442 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
443 clock-frequency = <33333333>;
444 #interrupt-cells = <1>;
445 #size-cells = <2>;
446 #address-cells = <3>;
447 reg = <0xe000a000 0x1000>;
448 compatible = "fsl,mpc8548-pcie";
449 device_type = "pci";
450 pcie@0 {
451 reg = <0x0 0x0 0x0 0x0 0x0>;
452 #size-cells = <2>;
453 #address-cells = <3>;
454 device_type = "pci";
455 ranges = <0x2000000 0x0 0xa0000000
456 0x2000000 0x0 0xa0000000
457 0x0 0x10000000
458
459 0x1000000 0x0 0x0
460 0x1000000 0x0 0x0
461 0x0 0x800000>;
462 };
463 };
464 };
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