arch/powerpc/include/asm/eeh.h

   1 /*
   2  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   3  * Copyright 2001-2012 IBM Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _POWERPC_EEH_H
  21 #define _POWERPC_EEH_H
  22 #ifdef __KERNEL__
  23
  24 #include <linux/init.h>
  25 #include <linux/list.h>
  26 #include <linux/string.h>
  27 #include <linux/time.h>
  28 #include <linux/atomic.h>
  29
  30 struct pci_dev;
  31 struct pci_bus;
  32 struct pci_dn;
  33
  34 #ifdef CONFIG_EEH
  35
  36 /* EEH subsystem flags */
  37 #define EEH_ENABLED             0x01    /* EEH enabled          */
  38 #define EEH_FORCE_DISABLED      0x02    /* EEH disabled         */
  39 #define EEH_PROBE_MODE_DEV      0x04    /* From PCI device      */
  40 #define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree     */
  41 #define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid        */
  42 #define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log    */
  43 #define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately */
  44
  45 /*
  46  * Delay for PE reset, all in ms
  47  *
  48  * PCI specification has reset hold time of 100 milliseconds.
  49  * We have 250 milliseconds here. The PCI bus settlement time
  50  * is specified as 1.5 seconds and we have 1.8 seconds.
  51  */
  52 #define EEH_PE_RST_HOLD_TIME            250
  53 #define EEH_PE_RST_SETTLE_TIME          1800
  54
  55 /*
  56  * The struct is used to trace PE related EEH functionality.
  57  * In theory, there will have one instance of the struct to
  58  * be created against particular PE. In nature, PEs corelate
  59  * to each other. the struct has to reflect that hierarchy in
  60  * order to easily pick up those affected PEs when one particular
  61  * PE has EEH errors.
  62  *
  63  * Also, one particular PE might be composed of PCI device, PCI
  64  * bus and its subordinate components. The struct also need ship
  65  * the information. Further more, one particular PE is only meaingful
  66  * in the corresponding PHB. Therefore, the root PEs should be created
  67  * against existing PHBs in on-to-one fashion.
  68  */
  69 #define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  70 #define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  71 #define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  72 #define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  73
  74 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  75 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  76 #define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
  77 #define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
  78
  79 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  80 #define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
  81 #define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
  82
  83 struct eeh_pe {
  84         int type;                       /* PE type: PHB/Bus/Device      */
  85         int state;                      /* PE EEH dependent mode        */
  86         int config_addr;                /* Traditional PCI address      */
  87         int addr;                       /* PE configuration address     */
  88         struct pci_controller *phb;     /* Associated PHB               */
  89         struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  90         int check_count;                /* Times of ignored error       */
  91         int freeze_count;               /* Times of froze up            */
  92         struct timeval tstamp;          /* Time on first-time freeze    */
  93         int false_positives;            /* Times of reported #ff's      */
  94         atomic_t pass_dev_cnt;          /* Count of passed through devs */
  95         struct eeh_pe *parent;          /* Parent PE                    */
  96         void *data;                     /* PE auxillary data            */
  97         struct list_head child_list;    /* Link PE to the child list    */
  98         struct list_head edevs;         /* Link list of EEH devices     */
  99         struct list_head child;         /* Child PEs                    */
 100 };
 101
 102 #define eeh_pe_for_each_dev(pe, edev, tmp) \
 103                 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
 104
 105 static inline bool eeh_pe_passed(struct eeh_pe *pe)
 106 {
 107         return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
 108 }
 109
 110 /*
 111  * The struct is used to trace EEH state for the associated
 112  * PCI device node or PCI device. In future, it might
 113  * represent PE as well so that the EEH device to form
 114  * another tree except the currently existing tree of PCI
 115  * buses and PCI devices
 116  */
 117 #define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 118 #define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 119 #define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 120 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 121 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 122
 123 #define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 124 #define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 125 #define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 126
 127 struct eeh_dev {
 128         int mode;                       /* EEH mode                     */
 129         int class_code;                 /* Class code of the device     */
 130         int config_addr;                /* Config address               */
 131         int pe_config_addr;             /* PE config address            */
 132         u32 config_space[16];           /* Saved PCI config space       */
 133         int pcix_cap;                   /* Saved PCIx capability        */
 134         int pcie_cap;                   /* Saved PCIe capability        */
 135         int aer_cap;                    /* Saved AER capability         */
 136         struct eeh_pe *pe;              /* Associated PE                */
 137         struct list_head list;          /* Form link list in the PE     */
 138         struct pci_controller *phb;     /* Associated PHB               */
 139         struct pci_dn *pdn;             /* Associated PCI device node   */
 140         struct pci_dev *pdev;           /* Associated PCI device        */
 141         struct pci_bus *bus;            /* PCI bus for partial hotplug  */
 142 };
 143
 144 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
 145 {
 146         return edev ? edev->pdn : NULL;
 147 }
 148
 149 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 150 {
 151         return edev ? edev->pdev : NULL;
 152 }
 153
 154 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
 155 {
 156         return edev ? edev->pe : NULL;
 157 }
 158
 159 /* Return values from eeh_ops::next_error */
 160 enum {
 161         EEH_NEXT_ERR_NONE = 0,
 162         EEH_NEXT_ERR_INF,
 163         EEH_NEXT_ERR_FROZEN_PE,
 164         EEH_NEXT_ERR_FENCED_PHB,
 165         EEH_NEXT_ERR_DEAD_PHB,
 166         EEH_NEXT_ERR_DEAD_IOC
 167 };
 168
 169 /*
 170  * The struct is used to trace the registered EEH operation
 171  * callback functions. Actually, those operation callback
 172  * functions are heavily platform dependent. That means the
 173  * platform should register its own EEH operation callback
 174  * functions before any EEH further operations.
 175  */
 176 #define EEH_OPT_DISABLE         0       /* EEH disable  */
 177 #define EEH_OPT_ENABLE          1       /* EEH enable   */
 178 #define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 179 #define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 180 #define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
 181 #define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 182 #define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 183 #define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 184 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 185 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 186 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 187 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 188 #define EEH_PE_STATE_NORMAL             0       /* Normal state         */
 189 #define EEH_PE_STATE_RESET              1       /* PE reset asserted    */
 190 #define EEH_PE_STATE_STOPPED_IO_DMA     2       /* Frozen PE            */
 191 #define EEH_PE_STATE_STOPPED_DMA        4       /* Stopped DMA, Enabled IO */
 192 #define EEH_PE_STATE_UNAVAIL            5       /* Unavailable          */
 193 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 194 #define EEH_RESET_HOT           1       /* Hot reset                    */
 195 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 196 #define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 197 #define EEH_LOG_PERM            2       /* EEH permanent error log      */
 198
 199 struct eeh_ops {
 200         char *name;
 201         int (*init)(void);
 202         int (*post_init)(void);
 203         void* (*probe)(struct pci_dn *pdn, void *data);
 204         int (*set_option)(struct eeh_pe *pe, int option);
 205         int (*get_pe_addr)(struct eeh_pe *pe);
 206         int (*get_state)(struct eeh_pe *pe, int *state);
 207         int (*reset)(struct eeh_pe *pe, int option);
 208         int (*wait_state)(struct eeh_pe *pe, int max_wait);
 209         int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 210         int (*configure_bridge)(struct eeh_pe *pe);
 211         int (*err_inject)(struct eeh_pe *pe, int type, int func,
 212                           unsigned long addr, unsigned long mask);
 213         int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
 214         int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
 215         int (*next_error)(struct eeh_pe **pe);
 216         int (*restore_config)(struct pci_dn *pdn);
 217 };
 218
 219 extern int eeh_subsystem_flags;
 220 extern int eeh_max_freezes;
 221 extern struct eeh_ops *eeh_ops;
 222 extern raw_spinlock_t confirm_error_lock;
 223
 224 static inline void eeh_add_flag(int flag)
 225 {
 226         eeh_subsystem_flags |= flag;
 227 }
 228
 229 static inline void eeh_clear_flag(int flag)
 230 {
 231         eeh_subsystem_flags &= ~flag;
 232 }
 233
 234 static inline bool eeh_has_flag(int flag)
 235 {
 236         return !!(eeh_subsystem_flags & flag);
 237 }
 238
 239 static inline bool eeh_enabled(void)
 240 {
 241         if (eeh_has_flag(EEH_FORCE_DISABLED) ||
 242             !eeh_has_flag(EEH_ENABLED))
 243                 return false;
 244
 245         return true;
 246 }
 247
 248 static inline void eeh_serialize_lock(unsigned long *flags)
 249 {
 250         raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 251 }
 252
 253 static inline void eeh_serialize_unlock(unsigned long flags)
 254 {
 255         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 256 }
 257
 258 typedef void *(*eeh_traverse_func)(void *data, void *flag);
 259 void eeh_set_pe_aux_size(int size);
 260 int eeh_phb_pe_create(struct pci_controller *phb);
 261 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 262 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
 263 int eeh_add_to_parent_pe(struct eeh_dev *edev);
 264 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 265 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 266 void *eeh_pe_traverse(struct eeh_pe *root,
 267                 eeh_traverse_func fn, void *flag);
 268 void *eeh_pe_dev_traverse(struct eeh_pe *root,
 269                 eeh_traverse_func fn, void *flag);
 270 void eeh_pe_restore_bars(struct eeh_pe *pe);
 271 const char *eeh_pe_loc_get(struct eeh_pe *pe);
 272 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 273
 274 void *eeh_dev_init(struct pci_dn *pdn, void *data);
 275 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 276 int eeh_init(void);
 277 int __init eeh_ops_register(struct eeh_ops *ops);
 278 int __exit eeh_ops_unregister(const char *name);
 279 int eeh_check_failure(const volatile void __iomem *token);
 280 int eeh_dev_check_failure(struct eeh_dev *edev);
 281 void eeh_addr_cache_build(void);
 282 void eeh_add_device_early(struct pci_dn *);
 283 void eeh_add_device_tree_early(struct pci_dn *);
 284 void eeh_add_device_late(struct pci_dev *);
 285 void eeh_add_device_tree_late(struct pci_bus *);
 286 void eeh_add_sysfs_files(struct pci_bus *);
 287 void eeh_remove_device(struct pci_dev *);
 288 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
 289 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
 290 int eeh_dev_open(struct pci_dev *pdev);
 291 void eeh_dev_release(struct pci_dev *pdev);
 292 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
 293 int eeh_pe_set_option(struct eeh_pe *pe, int option);
 294 int eeh_pe_get_state(struct eeh_pe *pe);
 295 int eeh_pe_reset(struct eeh_pe *pe, int option);
 296 int eeh_pe_configure(struct eeh_pe *pe);
 297
 298 /**
 299  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 300  *
 301  * If this macro yields TRUE, the caller relays to eeh_check_failure()
 302  * which does further tests out of line.
 303  */
 304 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 305
 306 /*
 307  * Reads from a device which has been isolated by EEH will return
 308  * all 1s.  This macro gives an all-1s value of the given size (in
 309  * bytes: 1, 2, or 4) for comparing with the result of a read.
 310  */
 311 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 312
 313 #else /* !CONFIG_EEH */
 314
 315 static inline bool eeh_enabled(void)
 316 {
 317         return false;
 318 }
 319
 320 static inline int eeh_init(void)
 321 {
 322         return 0;
 323 }
 324
 325 static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
 326 {
 327         return NULL;
 328 }
 329
 330 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 331
 332 static inline int eeh_check_failure(const volatile void __iomem *token)
 333 {
 334         return 0;
 335 }
 336
 337 #define eeh_dev_check_failure(x) (0)
 338
 339 static inline void eeh_addr_cache_build(void) { }
 340
 341 static inline void eeh_add_device_early(struct pci_dn *pdn) { }
 342
 343 static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
 344
 345 static inline void eeh_add_device_late(struct pci_dev *dev) { }
 346
 347 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 348
 349 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 350
 351 static inline void eeh_remove_device(struct pci_dev *dev) { }
 352
 353 #define EEH_POSSIBLE_ERROR(val, type) (0)
 354 #define EEH_IO_ERROR_VALUE(size) (-1UL)
 355 #endif /* CONFIG_EEH */
 356
 357 #ifdef CONFIG_PPC64
 358 /*
 359  * MMIO read/write operations with EEH support.
 360  */
 361 static inline u8 eeh_readb(const volatile void __iomem *addr)
 362 {
 363         u8 val = in_8(addr);
 364         if (EEH_POSSIBLE_ERROR(val, u8))
 365                 eeh_check_failure(addr);
 366         return val;
 367 }
 368
 369 static inline u16 eeh_readw(const volatile void __iomem *addr)
 370 {
 371         u16 val = in_le16(addr);
 372         if (EEH_POSSIBLE_ERROR(val, u16))
 373                 eeh_check_failure(addr);
 374         return val;
 375 }
 376
 377 static inline u32 eeh_readl(const volatile void __iomem *addr)
 378 {
 379         u32 val = in_le32(addr);
 380         if (EEH_POSSIBLE_ERROR(val, u32))
 381                 eeh_check_failure(addr);
 382         return val;
 383 }
 384
 385 static inline u64 eeh_readq(const volatile void __iomem *addr)
 386 {
 387         u64 val = in_le64(addr);
 388         if (EEH_POSSIBLE_ERROR(val, u64))
 389                 eeh_check_failure(addr);
 390         return val;
 391 }
 392
 393 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 394 {
 395         u16 val = in_be16(addr);
 396         if (EEH_POSSIBLE_ERROR(val, u16))
 397                 eeh_check_failure(addr);
 398         return val;
 399 }
 400
 401 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 402 {
 403         u32 val = in_be32(addr);
 404         if (EEH_POSSIBLE_ERROR(val, u32))
 405                 eeh_check_failure(addr);
 406         return val;
 407 }
 408
 409 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 410 {
 411         u64 val = in_be64(addr);
 412         if (EEH_POSSIBLE_ERROR(val, u64))
 413                 eeh_check_failure(addr);
 414         return val;
 415 }
 416
 417 static inline void eeh_memcpy_fromio(void *dest, const
 418                                      volatile void __iomem *src,
 419                                      unsigned long n)
 420 {
 421         _memcpy_fromio(dest, src, n);
 422
 423         /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 424          * were copied. Check all four bytes.
 425          */
 426         if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 427                 eeh_check_failure(src);
 428 }
 429
 430 /* in-string eeh macros */
 431 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 432                               int ns)
 433 {
 434         _insb(addr, buf, ns);
 435         if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 436                 eeh_check_failure(addr);
 437 }
 438
 439 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 440                               int ns)
 441 {
 442         _insw(addr, buf, ns);
 443         if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 444                 eeh_check_failure(addr);
 445 }
 446
 447 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 448                               int nl)
 449 {
 450         _insl(addr, buf, nl);
 451         if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 452                 eeh_check_failure(addr);
 453 }
 454
 455 #endif /* CONFIG_PPC64 */
 456 #endif /* __KERNEL__ */
 457 #endif /* _POWERPC_EEH_H */