2 * PowerNV OPAL definitions.
4 * Copyright 2011 IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
19 * WARNING: The current implementation requires each entry
20 * to represent a block that is 4k aligned *and* each block
21 * size except the last one in the list to be as well.
23 struct opal_sg_entry
{
32 struct opal_sg_entry entry
[];
35 /* We calculate number of sg entries based on PAGE_SIZE */
36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
38 #endif /* __ASSEMBLY__ */
40 /****** OPAL APIs ******/
43 #define OPAL_SUCCESS 0
44 #define OPAL_PARAMETER -1
46 #define OPAL_PARTIAL -3
47 #define OPAL_CONSTRAINED -4
48 #define OPAL_CLOSED -5
49 #define OPAL_HARDWARE -6
50 #define OPAL_UNSUPPORTED -7
51 #define OPAL_PERMISSION -8
52 #define OPAL_NO_MEM -9
53 #define OPAL_RESOURCE -10
54 #define OPAL_INTERNAL_ERROR -11
55 #define OPAL_BUSY_EVENT -12
56 #define OPAL_HARDWARE_FROZEN -13
57 #define OPAL_WRONG_STATE -14
58 #define OPAL_ASYNC_COMPLETION -15
60 /* API Tokens (in r0) */
61 #define OPAL_INVALID_CALL -1
62 #define OPAL_CONSOLE_WRITE 1
63 #define OPAL_CONSOLE_READ 2
64 #define OPAL_RTC_READ 3
65 #define OPAL_RTC_WRITE 4
66 #define OPAL_CEC_POWER_DOWN 5
67 #define OPAL_CEC_REBOOT 6
68 #define OPAL_READ_NVRAM 7
69 #define OPAL_WRITE_NVRAM 8
70 #define OPAL_HANDLE_INTERRUPT 9
71 #define OPAL_POLL_EVENTS 10
72 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
73 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
74 #define OPAL_PCI_CONFIG_READ_BYTE 13
75 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
76 #define OPAL_PCI_CONFIG_READ_WORD 15
77 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
79 #define OPAL_PCI_CONFIG_WRITE_WORD 18
80 #define OPAL_SET_XIVE 19
81 #define OPAL_GET_XIVE 20
82 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
84 #define OPAL_PCI_EEH_FREEZE_STATUS 23
85 #define OPAL_PCI_SHPC 24
86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
87 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
88 #define OPAL_PCI_PHB_MMIO_ENABLE 27
89 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
92 #define OPAL_PCI_SET_PE 31
93 #define OPAL_PCI_SET_PELTV 32
94 #define OPAL_PCI_SET_MVE 33
95 #define OPAL_PCI_SET_MVE_ENABLE 34
96 #define OPAL_PCI_GET_XIVE_REISSUE 35
97 #define OPAL_PCI_SET_XIVE_REISSUE 36
98 #define OPAL_PCI_SET_XIVE_PE 37
99 #define OPAL_GET_XIVE_SOURCE 38
100 #define OPAL_GET_MSI_32 39
101 #define OPAL_GET_MSI_64 40
102 #define OPAL_START_CPU 41
103 #define OPAL_QUERY_CPU_STATUS 42
104 #define OPAL_WRITE_OPPANEL 43
105 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
107 #define OPAL_PCI_RESET 49
108 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
109 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
110 #define OPAL_PCI_FENCE_PHB 52
111 #define OPAL_PCI_REINIT 53
112 #define OPAL_PCI_MASK_PE_ERROR 54
113 #define OPAL_SET_SLOT_LED_STATUS 55
114 #define OPAL_GET_EPOW_STATUS 56
115 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
116 #define OPAL_RESERVED1 58
117 #define OPAL_RESERVED2 59
118 #define OPAL_PCI_NEXT_ERROR 60
119 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
120 #define OPAL_PCI_POLL 62
121 #define OPAL_PCI_MSI_EOI 63
122 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
123 #define OPAL_XSCOM_READ 65
124 #define OPAL_XSCOM_WRITE 66
125 #define OPAL_LPC_READ 67
126 #define OPAL_LPC_WRITE 68
127 #define OPAL_RETURN_CPU 69
128 #define OPAL_REINIT_CPUS 70
129 #define OPAL_ELOG_READ 71
130 #define OPAL_ELOG_WRITE 72
131 #define OPAL_ELOG_ACK 73
132 #define OPAL_ELOG_RESEND 74
133 #define OPAL_ELOG_SIZE 75
134 #define OPAL_FLASH_VALIDATE 76
135 #define OPAL_FLASH_MANAGE 77
136 #define OPAL_FLASH_UPDATE 78
137 #define OPAL_RESYNC_TIMEBASE 79
138 #define OPAL_DUMP_INIT 81
139 #define OPAL_DUMP_INFO 82
140 #define OPAL_DUMP_READ 83
141 #define OPAL_DUMP_ACK 84
142 #define OPAL_GET_MSG 85
143 #define OPAL_CHECK_ASYNC_COMPLETION 86
144 #define OPAL_SYNC_HOST_REBOOT 87
145 #define OPAL_SENSOR_READ 88
146 #define OPAL_GET_PARAM 89
147 #define OPAL_SET_PARAM 90
148 #define OPAL_DUMP_RESEND 91
149 #define OPAL_DUMP_INFO2 94
150 #define OPAL_PCI_EEH_FREEZE_SET 97
154 #include <linux/notifier.h>
157 enum OpalVendorApiTokens
{
158 OPAL_START_VENDOR_API_RANGE
= 1000, OPAL_END_VENDOR_API_RANGE
= 1999
161 enum OpalFreezeState
{
162 OPAL_EEH_STOPPED_NOT_FROZEN
= 0,
163 OPAL_EEH_STOPPED_MMIO_FREEZE
= 1,
164 OPAL_EEH_STOPPED_DMA_FREEZE
= 2,
165 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE
= 3,
166 OPAL_EEH_STOPPED_RESET
= 4,
167 OPAL_EEH_STOPPED_TEMP_UNAVAIL
= 5,
168 OPAL_EEH_STOPPED_PERM_UNAVAIL
= 6
171 enum OpalEehFreezeActionToken
{
172 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO
= 1,
173 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA
= 2,
174 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
= 3,
176 OPAL_EEH_ACTION_SET_FREEZE_MMIO
= 1,
177 OPAL_EEH_ACTION_SET_FREEZE_DMA
= 2,
178 OPAL_EEH_ACTION_SET_FREEZE_ALL
= 3
181 enum OpalPciStatusToken
{
182 OPAL_EEH_NO_ERROR
= 0,
183 OPAL_EEH_IOC_ERROR
= 1,
184 OPAL_EEH_PHB_ERROR
= 2,
185 OPAL_EEH_PE_ERROR
= 3,
186 OPAL_EEH_PE_MMIO_ERROR
= 4,
187 OPAL_EEH_PE_DMA_ERROR
= 5
190 enum OpalPciErrorSeverity
{
191 OPAL_EEH_SEV_NO_ERROR
= 0,
192 OPAL_EEH_SEV_IOC_DEAD
= 1,
193 OPAL_EEH_SEV_PHB_DEAD
= 2,
194 OPAL_EEH_SEV_PHB_FENCED
= 3,
195 OPAL_EEH_SEV_PE_ER
= 4,
199 enum OpalShpcAction
{
200 OPAL_SHPC_GET_LINK_STATE
= 0,
201 OPAL_SHPC_GET_SLOT_STATE
= 1
204 enum OpalShpcLinkState
{
205 OPAL_SHPC_LINK_DOWN
= 0,
206 OPAL_SHPC_LINK_UP
= 1
209 enum OpalMmioWindowType
{
210 OPAL_M32_WINDOW_TYPE
= 1,
211 OPAL_M64_WINDOW_TYPE
= 2,
212 OPAL_IO_WINDOW_TYPE
= 3
215 enum OpalShpcSlotState
{
216 OPAL_SHPC_DEV_NOT_PRESENT
= 0,
217 OPAL_SHPC_DEV_PRESENT
= 1
220 enum OpalExceptionHandler
{
221 OPAL_MACHINE_CHECK_HANDLER
= 1,
222 OPAL_HYPERVISOR_MAINTENANCE_HANDLER
= 2,
223 OPAL_SOFTPATCH_HANDLER
= 3
226 enum OpalPendingState
{
227 OPAL_EVENT_OPAL_INTERNAL
= 0x1,
228 OPAL_EVENT_NVRAM
= 0x2,
229 OPAL_EVENT_RTC
= 0x4,
230 OPAL_EVENT_CONSOLE_OUTPUT
= 0x8,
231 OPAL_EVENT_CONSOLE_INPUT
= 0x10,
232 OPAL_EVENT_ERROR_LOG_AVAIL
= 0x20,
233 OPAL_EVENT_ERROR_LOG
= 0x40,
234 OPAL_EVENT_EPOW
= 0x80,
235 OPAL_EVENT_LED_STATUS
= 0x100,
236 OPAL_EVENT_PCI_ERROR
= 0x200,
237 OPAL_EVENT_DUMP_AVAIL
= 0x400,
238 OPAL_EVENT_MSG_PENDING
= 0x800,
241 enum OpalMessageType
{
242 OPAL_MSG_ASYNC_COMP
= 0, /* params[0] = token, params[1] = rc,
243 * additional params function-specific
251 /* Machine check related definitions */
252 enum OpalMCE_Version
{
256 enum OpalMCE_Severity
{
257 OpalMCE_SEV_NO_ERROR
= 0,
258 OpalMCE_SEV_WARNING
= 1,
259 OpalMCE_SEV_ERROR_SYNC
= 2,
260 OpalMCE_SEV_FATAL
= 3,
263 enum OpalMCE_Disposition
{
264 OpalMCE_DISPOSITION_RECOVERED
= 0,
265 OpalMCE_DISPOSITION_NOT_RECOVERED
= 1,
268 enum OpalMCE_Initiator
{
269 OpalMCE_INITIATOR_UNKNOWN
= 0,
270 OpalMCE_INITIATOR_CPU
= 1,
273 enum OpalMCE_ErrorType
{
274 OpalMCE_ERROR_TYPE_UNKNOWN
= 0,
275 OpalMCE_ERROR_TYPE_UE
= 1,
276 OpalMCE_ERROR_TYPE_SLB
= 2,
277 OpalMCE_ERROR_TYPE_ERAT
= 3,
278 OpalMCE_ERROR_TYPE_TLB
= 4,
281 enum OpalMCE_UeErrorType
{
282 OpalMCE_UE_ERROR_INDETERMINATE
= 0,
283 OpalMCE_UE_ERROR_IFETCH
= 1,
284 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH
= 2,
285 OpalMCE_UE_ERROR_LOAD_STORE
= 3,
286 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE
= 4,
289 enum OpalMCE_SlbErrorType
{
290 OpalMCE_SLB_ERROR_INDETERMINATE
= 0,
291 OpalMCE_SLB_ERROR_PARITY
= 1,
292 OpalMCE_SLB_ERROR_MULTIHIT
= 2,
295 enum OpalMCE_EratErrorType
{
296 OpalMCE_ERAT_ERROR_INDETERMINATE
= 0,
297 OpalMCE_ERAT_ERROR_PARITY
= 1,
298 OpalMCE_ERAT_ERROR_MULTIHIT
= 2,
301 enum OpalMCE_TlbErrorType
{
302 OpalMCE_TLB_ERROR_INDETERMINATE
= 0,
303 OpalMCE_TLB_ERROR_PARITY
= 1,
304 OpalMCE_TLB_ERROR_MULTIHIT
= 2,
307 enum OpalThreadStatus
{
308 OPAL_THREAD_INACTIVE
= 0x0,
309 OPAL_THREAD_STARTED
= 0x1,
310 OPAL_THREAD_UNAVAILABLE
= 0x2 /* opal-v3 */
313 enum OpalPciBusCompare
{
314 OpalPciBusAny
= 0, /* Any bus number match */
315 OpalPciBus3Bits
= 2, /* Match top 3 bits of bus number */
316 OpalPciBus4Bits
= 3, /* Match top 4 bits of bus number */
317 OpalPciBus5Bits
= 4, /* Match top 5 bits of bus number */
318 OpalPciBus6Bits
= 5, /* Match top 6 bits of bus number */
319 OpalPciBus7Bits
= 6, /* Match top 7 bits of bus number */
320 OpalPciBusAll
= 7, /* Match bus number exactly */
323 enum OpalDeviceCompare
{
324 OPAL_IGNORE_RID_DEVICE_NUMBER
= 0,
325 OPAL_COMPARE_RID_DEVICE_NUMBER
= 1
328 enum OpalFuncCompare
{
329 OPAL_IGNORE_RID_FUNCTION_NUMBER
= 0,
330 OPAL_COMPARE_RID_FUNCTION_NUMBER
= 1
338 enum OpalPeltvAction
{
339 OPAL_REMOVE_PE_FROM_DOMAIN
= 0,
340 OPAL_ADD_PE_TO_DOMAIN
= 1
343 enum OpalMveEnableAction
{
344 OPAL_DISABLE_MVE
= 0,
348 enum OpalM64EnableAction
{
349 OPAL_DISABLE_M64
= 0,
350 OPAL_ENABLE_M64_SPLIT
= 1,
351 OPAL_ENABLE_M64_NON_SPLIT
= 2
354 enum OpalPciResetScope
{
355 OPAL_PHB_COMPLETE
= 1, OPAL_PCI_LINK
= 2, OPAL_PHB_ERROR
= 3,
356 OPAL_PCI_HOT_RESET
= 4, OPAL_PCI_FUNDAMENTAL_RESET
= 5,
357 OPAL_PCI_IODA_TABLE_RESET
= 6,
360 enum OpalPciReinitScope
{
361 OPAL_REINIT_PCI_DEV
= 1000
364 enum OpalPciResetState
{
365 OPAL_DEASSERT_RESET
= 0,
366 OPAL_ASSERT_RESET
= 1
369 enum OpalPciMaskAction
{
370 OPAL_UNMASK_ERROR_TYPE
= 0,
371 OPAL_MASK_ERROR_TYPE
= 1
374 enum OpalSlotLedType
{
375 OPAL_SLOT_LED_ID_TYPE
= 0,
376 OPAL_SLOT_LED_FAULT_TYPE
= 1
380 OPAL_TURN_OFF_LED
= 0,
381 OPAL_TURN_ON_LED
= 1,
382 OPAL_QUERY_LED_STATE_AFTER_BUSY
= 2
385 enum OpalEpowStatus
{
388 OPAL_EPOW_OVER_AMBIENT_TEMP
= 2,
389 OPAL_EPOW_OVER_INTERNAL_TEMP
= 3
393 * Address cycle types for LPC accesses. These also correspond
394 * to the content of the first cell of the "reg" property for
395 * device nodes on the LPC bus
397 enum OpalLPCAddressType
{
403 /* System parameter permission */
404 enum OpalSysparamPerm
{
405 OPAL_SYSPARAM_READ
= 0x1,
406 OPAL_SYSPARAM_WRITE
= 0x2,
407 OPAL_SYSPARAM_RW
= (OPAL_SYSPARAM_READ
| OPAL_SYSPARAM_WRITE
),
416 struct opal_machine_check_event
{
417 enum OpalMCE_Version version
:8; /* 0x00 */
418 uint8_t in_use
; /* 0x01 */
419 enum OpalMCE_Severity severity
:8; /* 0x02 */
420 enum OpalMCE_Initiator initiator
:8; /* 0x03 */
421 enum OpalMCE_ErrorType error_type
:8; /* 0x04 */
422 enum OpalMCE_Disposition disposition
:8; /* 0x05 */
423 uint8_t reserved_1
[2]; /* 0x06 */
424 uint64_t gpr3
; /* 0x08 */
425 uint64_t srr0
; /* 0x10 */
426 uint64_t srr1
; /* 0x18 */
429 enum OpalMCE_UeErrorType ue_error_type
:8;
430 uint8_t effective_address_provided
;
431 uint8_t physical_address_provided
;
432 uint8_t reserved_1
[5];
433 uint64_t effective_address
;
434 uint64_t physical_address
;
435 uint8_t reserved_2
[8];
439 enum OpalMCE_SlbErrorType slb_error_type
:8;
440 uint8_t effective_address_provided
;
441 uint8_t reserved_1
[6];
442 uint64_t effective_address
;
443 uint8_t reserved_2
[16];
447 enum OpalMCE_EratErrorType erat_error_type
:8;
448 uint8_t effective_address_provided
;
449 uint8_t reserved_1
[6];
450 uint64_t effective_address
;
451 uint8_t reserved_2
[16];
455 enum OpalMCE_TlbErrorType tlb_error_type
:8;
456 uint8_t effective_address_provided
;
457 uint8_t reserved_1
[6];
458 uint64_t effective_address
;
459 uint8_t reserved_2
[16];
464 /* FSP memory errors handling */
465 enum OpalMemErr_Version
{
469 enum OpalMemErrType
{
470 OPAL_MEM_ERR_TYPE_RESILIENCE
= 0,
471 OPAL_MEM_ERR_TYPE_DYN_DALLOC
,
472 OPAL_MEM_ERR_TYPE_SCRUB
,
475 /* Memory Reilience error type */
476 enum OpalMemErr_ResilErrType
{
477 OPAL_MEM_RESILIENCE_CE
= 0,
478 OPAL_MEM_RESILIENCE_UE
,
479 OPAL_MEM_RESILIENCE_UE_SCRUB
,
482 /* Dynamic Memory Deallocation type */
483 enum OpalMemErr_DynErrType
{
484 OPAL_MEM_DYNAMIC_DEALLOC
= 0,
487 /* OpalMemoryErrorData->flags */
488 #define OPAL_MEM_CORRECTED_ERROR 0x0001
489 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
490 #define OPAL_MEM_ACK_REQUIRED 0x8000
492 struct OpalMemoryErrorData
{
493 enum OpalMemErr_Version version
:8; /* 0x00 */
494 enum OpalMemErrType type
:8; /* 0x01 */
495 __be16 flags
; /* 0x02 */
496 uint8_t reserved_1
[4]; /* 0x04 */
499 /* Memory Resilience corrected/uncorrected error info */
501 enum OpalMemErr_ResilErrType resil_err_type
:8;
502 uint8_t reserved_1
[7];
503 __be64 physical_address_start
;
504 __be64 physical_address_end
;
506 /* Dynamic memory deallocation error info */
508 enum OpalMemErr_DynErrType dyn_err_type
:8;
509 uint8_t reserved_1
[7];
510 __be64 physical_address_start
;
511 __be64 physical_address_end
;
517 OPAL_P7IOC_DIAG_TYPE_NONE
= 0,
518 OPAL_P7IOC_DIAG_TYPE_RGC
= 1,
519 OPAL_P7IOC_DIAG_TYPE_BI
= 2,
520 OPAL_P7IOC_DIAG_TYPE_CI
= 3,
521 OPAL_P7IOC_DIAG_TYPE_MISC
= 4,
522 OPAL_P7IOC_DIAG_TYPE_I2C
= 5,
523 OPAL_P7IOC_DIAG_TYPE_LAST
= 6
526 struct OpalIoP7IOCErrorData
{
544 struct OpalIoP7IOCRgcErrorData
{
545 __be64 rgcStatus
; /* 3E1C10 */
546 __be64 rgcLdcp
; /* 3E1C18 */
548 struct OpalIoP7IOCBiErrorData
{
549 __be64 biLdcp0
; /* 3C0100, 3C0118 */
550 __be64 biLdcp1
; /* 3C0108, 3C0120 */
551 __be64 biLdcp2
; /* 3C0110, 3C0128 */
552 __be64 biFenceStatus
; /* 3C0130, 3C0130 */
554 u8 biDownbound
; /* BI Downbound or Upbound */
556 struct OpalIoP7IOCCiErrorData
{
557 __be64 ciPortStatus
; /* 3Dn008 */
558 __be64 ciPortLdcp
; /* 3Dn010 */
560 u8 ciPort
; /* Index of CI port: 0/1 */
566 * This structure defines the overlay which will be used to store PHB error
570 OPAL_PHB_ERROR_DATA_VERSION_1
= 1,
574 OPAL_PHB_ERROR_DATA_TYPE_P7IOC
= 1,
575 OPAL_PHB_ERROR_DATA_TYPE_PHB3
= 2
579 OPAL_P7IOC_NUM_PEST_REGS
= 128,
580 OPAL_PHB3_NUM_PEST_REGS
= 256
583 struct OpalIoPhbErrorCommon
{
589 struct OpalIoP7IOCPhbErrorData
{
590 struct OpalIoPhbErrorCommon common
;
595 __be32 portStatusReg
;
596 __be32 rootCmplxStatus
;
597 __be32 busAgentStatus
;
607 __be32 rootErrorStatus
;
608 __be32 uncorrErrorStatus
;
609 __be32 corrErrorStatus
;
618 // Record data about the call to allocate a buffer.
622 //P7IOC MMIO Error Regs
623 __be64 p7iocPlssr
; // n120
624 __be64 p7iocCsr
; // n110
625 __be64 lemFir
; // nC00
626 __be64 lemErrorMask
; // nC18
627 __be64 lemWOF
; // nC40
628 __be64 phbErrorStatus
; // nC80
629 __be64 phbFirstErrorStatus
; // nC88
630 __be64 phbErrorLog0
; // nCC0
631 __be64 phbErrorLog1
; // nCC8
632 __be64 mmioErrorStatus
; // nD00
633 __be64 mmioFirstErrorStatus
; // nD08
634 __be64 mmioErrorLog0
; // nD40
635 __be64 mmioErrorLog1
; // nD48
636 __be64 dma0ErrorStatus
; // nD80
637 __be64 dma0FirstErrorStatus
; // nD88
638 __be64 dma0ErrorLog0
; // nDC0
639 __be64 dma0ErrorLog1
; // nDC8
640 __be64 dma1ErrorStatus
; // nE00
641 __be64 dma1FirstErrorStatus
; // nE08
642 __be64 dma1ErrorLog0
; // nE40
643 __be64 dma1ErrorLog1
; // nE48
644 __be64 pestA
[OPAL_P7IOC_NUM_PEST_REGS
];
645 __be64 pestB
[OPAL_P7IOC_NUM_PEST_REGS
];
648 struct OpalIoPhb3ErrorData
{
649 struct OpalIoPhbErrorCommon common
;
654 __be32 portStatusReg
;
655 __be32 rootCmplxStatus
;
656 __be32 busAgentStatus
;
666 __be32 rootErrorStatus
;
667 __be32 uncorrErrorStatus
;
668 __be32 corrErrorStatus
;
677 /* Record data about the call to allocate a buffer */
681 __be64 nFir
; /* 000 */
682 __be64 nFirMask
; /* 003 */
683 __be64 nFirWOF
; /* 008 */
685 /* PHB3 MMIO Error Regs */
686 __be64 phbPlssr
; /* 120 */
687 __be64 phbCsr
; /* 110 */
688 __be64 lemFir
; /* C00 */
689 __be64 lemErrorMask
; /* C18 */
690 __be64 lemWOF
; /* C40 */
691 __be64 phbErrorStatus
; /* C80 */
692 __be64 phbFirstErrorStatus
; /* C88 */
693 __be64 phbErrorLog0
; /* CC0 */
694 __be64 phbErrorLog1
; /* CC8 */
695 __be64 mmioErrorStatus
; /* D00 */
696 __be64 mmioFirstErrorStatus
; /* D08 */
697 __be64 mmioErrorLog0
; /* D40 */
698 __be64 mmioErrorLog1
; /* D48 */
699 __be64 dma0ErrorStatus
; /* D80 */
700 __be64 dma0FirstErrorStatus
; /* D88 */
701 __be64 dma0ErrorLog0
; /* DC0 */
702 __be64 dma0ErrorLog1
; /* DC8 */
703 __be64 dma1ErrorStatus
; /* E00 */
704 __be64 dma1FirstErrorStatus
; /* E08 */
705 __be64 dma1ErrorLog0
; /* E40 */
706 __be64 dma1ErrorLog1
; /* E48 */
707 __be64 pestA
[OPAL_PHB3_NUM_PEST_REGS
];
708 __be64 pestB
[OPAL_PHB3_NUM_PEST_REGS
];
712 OPAL_REINIT_CPUS_HILE_BE
= (1 << 0),
713 OPAL_REINIT_CPUS_HILE_LE
= (1 << 1),
716 typedef struct oppanel_line
{
721 /* /sys/firmware/opal */
722 extern struct kobject
*opal_kobj
;
725 extern struct device_node
*opal_node
;
728 int64_t opal_invalid_call(void);
729 int64_t opal_console_write(int64_t term_number
, __be64
*length
,
730 const uint8_t *buffer
);
731 int64_t opal_console_read(int64_t term_number
, __be64
*length
,
733 int64_t opal_console_write_buffer_space(int64_t term_number
,
735 int64_t opal_rtc_read(__be32
*year_month_day
,
736 __be64
*hour_minute_second_millisecond
);
737 int64_t opal_rtc_write(uint32_t year_month_day
,
738 uint64_t hour_minute_second_millisecond
);
739 int64_t opal_cec_power_down(uint64_t request
);
740 int64_t opal_cec_reboot(void);
741 int64_t opal_read_nvram(uint64_t buffer
, uint64_t size
, uint64_t offset
);
742 int64_t opal_write_nvram(uint64_t buffer
, uint64_t size
, uint64_t offset
);
743 int64_t opal_handle_interrupt(uint64_t isn
, __be64
*outstanding_event_mask
);
744 int64_t opal_poll_events(__be64
*outstanding_event_mask
);
745 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id
, uint64_t tce_mem_addr
,
746 uint64_t tce_mem_size
);
747 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id
, uint64_t tce_mem_addr
,
748 uint64_t tce_mem_size
);
749 int64_t opal_pci_config_read_byte(uint64_t phb_id
, uint64_t bus_dev_func
,
750 uint64_t offset
, uint8_t *data
);
751 int64_t opal_pci_config_read_half_word(uint64_t phb_id
, uint64_t bus_dev_func
,
752 uint64_t offset
, __be16
*data
);
753 int64_t opal_pci_config_read_word(uint64_t phb_id
, uint64_t bus_dev_func
,
754 uint64_t offset
, __be32
*data
);
755 int64_t opal_pci_config_write_byte(uint64_t phb_id
, uint64_t bus_dev_func
,
756 uint64_t offset
, uint8_t data
);
757 int64_t opal_pci_config_write_half_word(uint64_t phb_id
, uint64_t bus_dev_func
,
758 uint64_t offset
, uint16_t data
);
759 int64_t opal_pci_config_write_word(uint64_t phb_id
, uint64_t bus_dev_func
,
760 uint64_t offset
, uint32_t data
);
761 int64_t opal_set_xive(uint32_t isn
, uint16_t server
, uint8_t priority
);
762 int64_t opal_get_xive(uint32_t isn
, __be16
*server
, uint8_t *priority
);
763 int64_t opal_register_exception_handler(uint64_t opal_exception
,
764 uint64_t handler_address
,
765 uint64_t glue_cache_line
);
766 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id
, uint64_t pe_number
,
767 uint8_t *freeze_state
,
768 __be16
*pci_error_type
,
770 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id
, uint64_t pe_number
,
771 uint64_t eeh_action_token
);
772 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id
, uint64_t pe_number
,
773 uint64_t eeh_action_token
);
774 int64_t opal_pci_shpc(uint64_t phb_id
, uint64_t shpc_action
, uint8_t *state
);
778 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id
, uint16_t window_type
,
779 uint16_t window_num
, uint16_t enable
);
780 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id
, uint16_t window_type
,
782 uint64_t starting_real_address
,
783 uint64_t starting_pci_address
,
785 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id
, uint16_t pe_number
,
786 uint16_t window_type
, uint16_t window_num
,
787 uint16_t segment_num
);
788 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id
, uint64_t rtt_addr
,
789 uint64_t ivt_addr
, uint64_t ivt_len
,
790 uint64_t reject_array_addr
,
791 uint64_t peltv_addr
);
792 int64_t opal_pci_set_pe(uint64_t phb_id
, uint64_t pe_number
, uint64_t bus_dev_func
,
793 uint8_t bus_compare
, uint8_t dev_compare
, uint8_t func_compare
,
795 int64_t opal_pci_set_peltv(uint64_t phb_id
, uint32_t parent_pe
, uint32_t child_pe
,
797 int64_t opal_pci_set_mve(uint64_t phb_id
, uint32_t mve_number
, uint32_t pe_number
);
798 int64_t opal_pci_set_mve_enable(uint64_t phb_id
, uint32_t mve_number
,
800 int64_t opal_pci_get_xive_reissue(uint64_t phb_id
, uint32_t xive_number
,
801 uint8_t *p_bit
, uint8_t *q_bit
);
802 int64_t opal_pci_set_xive_reissue(uint64_t phb_id
, uint32_t xive_number
,
803 uint8_t p_bit
, uint8_t q_bit
);
804 int64_t opal_pci_msi_eoi(uint64_t phb_id
, uint32_t hw_irq
);
805 int64_t opal_pci_set_xive_pe(uint64_t phb_id
, uint32_t pe_number
,
807 int64_t opal_get_xive_source(uint64_t phb_id
, uint32_t xive_num
,
808 __be32
*interrupt_source_number
);
809 int64_t opal_get_msi_32(uint64_t phb_id
, uint32_t mve_number
, uint32_t xive_num
,
810 uint8_t msi_range
, __be32
*msi_address
,
811 __be32
*message_data
);
812 int64_t opal_get_msi_64(uint64_t phb_id
, uint32_t mve_number
,
813 uint32_t xive_num
, uint8_t msi_range
,
814 __be64
*msi_address
, __be32
*message_data
);
815 int64_t opal_start_cpu(uint64_t thread_number
, uint64_t start_address
);
816 int64_t opal_query_cpu_status(uint64_t thread_number
, uint8_t *thread_status
);
817 int64_t opal_write_oppanel(oppanel_line_t
*lines
, uint64_t num_lines
);
818 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id
, uint16_t pe_number
, uint16_t window_id
,
819 uint16_t tce_levels
, uint64_t tce_table_addr
,
820 uint64_t tce_table_size
, uint64_t tce_page_size
);
821 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id
, uint16_t pe_number
,
822 uint16_t dma_window_number
, uint64_t pci_start_addr
,
823 uint64_t pci_mem_size
);
824 int64_t opal_pci_reset(uint64_t phb_id
, uint8_t reset_scope
, uint8_t assert_state
);
826 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id
, void *diag_buffer
,
827 uint64_t diag_buffer_len
);
828 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id
, void *diag_buffer
,
829 uint64_t diag_buffer_len
);
830 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id
, void *diag_buffer
,
831 uint64_t diag_buffer_len
);
832 int64_t opal_pci_fence_phb(uint64_t phb_id
);
833 int64_t opal_pci_reinit(uint64_t phb_id
, uint64_t reinit_scope
, uint64_t data
);
834 int64_t opal_pci_mask_pe_error(uint64_t phb_id
, uint16_t pe_number
, uint8_t error_type
, uint8_t mask_action
);
835 int64_t opal_set_slot_led_status(uint64_t phb_id
, uint64_t slot_id
, uint8_t led_type
, uint8_t led_action
);
836 int64_t opal_get_epow_status(__be64
*status
);
837 int64_t opal_set_system_attention_led(uint8_t led_action
);
838 int64_t opal_pci_next_error(uint64_t phb_id
, __be64
*first_frozen_pe
,
839 __be16
*pci_error_type
, __be16
*severity
);
840 int64_t opal_pci_poll(uint64_t phb_id
);
841 int64_t opal_return_cpu(void);
842 int64_t opal_reinit_cpus(uint64_t flags
);
844 int64_t opal_xscom_read(uint32_t gcid
, uint64_t pcb_addr
, __be64
*val
);
845 int64_t opal_xscom_write(uint32_t gcid
, uint64_t pcb_addr
, uint64_t val
);
847 int64_t opal_lpc_write(uint32_t chip_id
, enum OpalLPCAddressType addr_type
,
848 uint32_t addr
, uint32_t data
, uint32_t sz
);
849 int64_t opal_lpc_read(uint32_t chip_id
, enum OpalLPCAddressType addr_type
,
850 uint32_t addr
, __be32
*data
, uint32_t sz
);
852 int64_t opal_read_elog(uint64_t buffer
, uint64_t size
, uint64_t log_id
);
853 int64_t opal_get_elog_size(__be64
*log_id
, __be64
*size
, __be64
*elog_type
);
854 int64_t opal_write_elog(uint64_t buffer
, uint64_t size
, uint64_t offset
);
855 int64_t opal_send_ack_elog(uint64_t log_id
);
856 void opal_resend_pending_logs(void);
858 int64_t opal_validate_flash(uint64_t buffer
, uint32_t *size
, uint32_t *result
);
859 int64_t opal_manage_flash(uint8_t op
);
860 int64_t opal_update_flash(uint64_t blk_list
);
861 int64_t opal_dump_init(uint8_t dump_type
);
862 int64_t opal_dump_info(__be32
*dump_id
, __be32
*dump_size
);
863 int64_t opal_dump_info2(__be32
*dump_id
, __be32
*dump_size
, __be32
*dump_type
);
864 int64_t opal_dump_read(uint32_t dump_id
, uint64_t buffer
);
865 int64_t opal_dump_ack(uint32_t dump_id
);
866 int64_t opal_dump_resend_notification(void);
868 int64_t opal_get_msg(uint64_t buffer
, uint64_t size
);
869 int64_t opal_check_completion(uint64_t buffer
, uint64_t size
, uint64_t token
);
870 int64_t opal_sync_host_reboot(void);
871 int64_t opal_get_param(uint64_t token
, uint32_t param_id
, uint64_t buffer
,
873 int64_t opal_set_param(uint64_t token
, uint32_t param_id
, uint64_t buffer
,
875 int64_t opal_sensor_read(uint32_t sensor_hndl
, int token
, __be32
*sensor_data
);
877 /* Internal functions */
878 extern int early_init_dt_scan_opal(unsigned long node
, const char *uname
,
879 int depth
, void *data
);
880 extern int early_init_dt_scan_recoverable_ranges(unsigned long node
,
881 const char *uname
, int depth
, void *data
);
883 extern int opal_get_chars(uint32_t vtermno
, char *buf
, int count
);
884 extern int opal_put_chars(uint32_t vtermno
, const char *buf
, int total_len
);
886 extern void hvc_opal_init_early(void);
888 extern int opal_notifier_register(struct notifier_block
*nb
);
889 extern int opal_notifier_unregister(struct notifier_block
*nb
);
891 extern int opal_message_notifier_register(enum OpalMessageType msg_type
,
892 struct notifier_block
*nb
);
893 extern void opal_notifier_enable(void);
894 extern void opal_notifier_disable(void);
895 extern void opal_notifier_update_evt(uint64_t evt_mask
, uint64_t evt_val
);
897 extern int __opal_async_get_token(void);
898 extern int opal_async_get_token_interruptible(void);
899 extern int __opal_async_release_token(int token
);
900 extern int opal_async_release_token(int token
);
901 extern int opal_async_wait_response(uint64_t token
, struct opal_msg
*msg
);
902 extern int opal_get_sensor_data(u32 sensor_hndl
, u32
*sensor_data
);
905 extern int opal_set_rtc_time(struct rtc_time
*tm
);
906 extern void opal_get_rtc_time(struct rtc_time
*tm
);
907 extern unsigned long opal_get_boot_time(void);
908 extern void opal_nvram_init(void);
909 extern void opal_flash_init(void);
910 extern void opal_flash_term_callback(void);
911 extern int opal_elog_init(void);
912 extern void opal_platform_dump_init(void);
913 extern void opal_sys_param_init(void);
914 extern void opal_msglog_init(void);
916 extern int opal_machine_check(struct pt_regs
*regs
);
917 extern bool opal_mce_check_early_recovery(struct pt_regs
*regs
);
919 extern void opal_shutdown(void);
920 extern int opal_resync_timebase(void);
922 extern void opal_lpc_init(void);
924 struct opal_sg_list
*opal_vmalloc_to_sg_list(void *vmalloc_addr
,
925 unsigned long vmalloc_size
);
926 void opal_free_sg_list(struct opal_sg_list
*sg
);
928 #endif /* __ASSEMBLY__ */
930 #endif /* __OPAL_H */