2 * Performance event support - PowerPC classic/server specific definitions.
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <asm/hw_irq.h>
14 #include <linux/device.h>
16 #define MAX_HWEVENTS 8
17 #define MAX_EVENT_ALTERNATIVES 8
18 #define MAX_LIMITED_HWCOUNTERS 2
21 * This struct provides the constants and functions needed to
22 * describe the PMU on a particular POWER-family CPU.
28 unsigned long add_fields
;
29 unsigned long test_adder
;
30 int (*compute_mmcr
)(u64 events
[], int n_ev
,
31 unsigned int hwc
[], unsigned long mmcr
[]);
32 int (*get_constraint
)(u64 event_id
, unsigned long *mskp
,
34 int (*get_alternatives
)(u64 event_id
, unsigned int flags
,
36 u64 (*bhrb_filter_map
)(u64 branch_sample_type
);
37 void (*config_bhrb
)(u64 pmu_bhrb_filter
);
38 void (*disable_pmc
)(unsigned int pmc
, unsigned long mmcr
[]);
39 int (*limited_pmc_event
)(u64 event_id
);
41 const struct attribute_group
**attr_groups
;
44 int (*cache_events
)[PERF_COUNT_HW_CACHE_MAX
]
45 [PERF_COUNT_HW_CACHE_OP_MAX
]
46 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
48 /* BHRB entries in the PMU */
53 * Values for power_pmu.flags
55 #define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */
56 #define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */
57 #define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */
58 #define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */
59 #define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
60 #define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
61 #define PPMU_HAS_SIER 0x00000040 /* Has SIER */
62 #define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */
63 #define PPMU_EBB 0x00000100 /* supports event based branch */
66 * Values for flags to get_alternatives()
68 #define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
69 #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
70 #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
73 * We use the event config bit 63 as a flag to request EBB.
75 #define EVENT_CONFIG_EBB_SHIFT 63
77 extern int register_power_pmu(struct power_pmu
*);
80 extern unsigned long perf_misc_flags(struct pt_regs
*regs
);
81 extern unsigned long perf_instruction_pointer(struct pt_regs
*regs
);
82 extern unsigned long int read_bhrb(int n
);
85 * Only override the default definitions in include/linux/perf_event.h
86 * if we have hardware PMU support.
88 #ifdef CONFIG_PPC_PERF_CTRS
89 #define perf_misc_flags(regs) perf_misc_flags(regs)
93 * The power_pmu.get_constraint function returns a 32/64-bit value and
94 * a 32/64-bit mask that express the constraints between this event_id and
97 * The value and mask are divided up into (non-overlapping) bitfields
98 * of three different types:
100 * Select field: this expresses the constraint that some set of bits
101 * in MMCR* needs to be set to a specific value for this event_id. For a
102 * select field, the mask contains 1s in every bit of the field, and
103 * the value contains a unique value for each possible setting of the
104 * MMCR* bits. The constraint checking code will ensure that two events
105 * that set the same field in their masks have the same value in their
108 * Add field: this expresses the constraint that there can be at most
109 * N events in a particular class. A field of k bits can be used for
110 * N <= 2^(k-1) - 1. The mask has the most significant bit of the field
111 * set (and the other bits 0), and the value has only the least significant
112 * bit of the field set. In addition, the 'add_fields' and 'test_adder'
113 * in the struct power_pmu for this processor come into play. The
114 * add_fields value contains 1 in the LSB of the field, and the
115 * test_adder contains 2^(k-1) - 1 - N in the field.
117 * NAND field: this expresses the constraint that you may not have events
118 * in all of a set of classes. (For example, on PPC970, you can't select
119 * events from the FPU, ISU and IDU simultaneously, although any two are
120 * possible.) For N classes, the field is N+1 bits wide, and each class
121 * is assigned one bit from the least-significant N bits. The mask has
122 * only the most-significant bit set, and the value has only the bit
123 * for the event_id's class set. The test_adder has the least significant
124 * bit set in the field.
126 * If an event_id is not subject to the constraint expressed by a particular
127 * field, then it will have 0 in both the mask and value for that field.
130 extern ssize_t
power_events_sysfs_show(struct device
*dev
,
131 struct device_attribute
*attr
, char *page
);
134 * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
136 * Having a suffix allows us to have aliases in sysfs - eg: the generic
137 * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
138 * 'PM_CYC' where the latter is the name by which the event is known in
139 * POWER CPU specification.
141 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
142 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
144 #define EVENT_ATTR(_name, _id, _suffix) \
145 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id, \
146 power_events_sysfs_show)
148 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
149 #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
151 #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(PM_##_name, _id, _p)
152 #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p)