1 #ifndef _ASM_POWERPC_PROCESSOR_H
2 #define _ASM_POWERPC_PROCESSOR_H
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
22 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
23 #define PPR_PRIORITY 3
25 #define INIT_PPR (PPR_PRIORITY << 50)
27 #define INIT_PPR ((u64)PPR_PRIORITY << 50)
28 #endif /* __ASSEMBLY__ */
29 #endif /* CONFIG_PPC64 */
32 #include <linux/compiler.h>
33 #include <linux/cache.h>
34 #include <asm/ptrace.h>
35 #include <asm/types.h>
36 #include <asm/hw_breakpoint.h>
38 /* We do _not_ want to define new machine types at all, those must die
39 * in favor of using the device-tree
43 /* PREP sub-platform types. Unused */
44 #define _PREP_Motorola 0x01 /* motorola prep */
45 #define _PREP_Firm 0x02 /* firmworks prep */
46 #define _PREP_IBM 0x00 /* ibm prep */
47 #define _PREP_Bull 0x03 /* bull prep */
49 /* CHRP sub-platform types. These are arbitrary */
50 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
51 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
52 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
53 #define _CHRP_briq 0x07 /* TotalImpact's briQ */
55 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
57 extern int _chrp_type
;
59 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
62 * Default implementation of macro that returns current
63 * instruction pointer ("program counter").
65 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
67 /* Macros for adjusting thread priority (hardware multi-threading) */
68 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
69 #define HMT_low() asm volatile("or 1,1,1 # low priority")
70 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
71 #define HMT_medium() asm volatile("or 2,2,2 # medium priority")
72 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
73 #define HMT_high() asm volatile("or 3,3,3 # high priority")
78 void start_thread(struct pt_regs
*regs
, unsigned long fdptr
, unsigned long sp
);
79 void release_thread(struct task_struct
*);
81 /* Lazy FPU handling on uni-processor */
82 extern struct task_struct
*last_task_used_math
;
83 extern struct task_struct
*last_task_used_altivec
;
84 extern struct task_struct
*last_task_used_vsx
;
85 extern struct task_struct
*last_task_used_spe
;
89 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
90 #error User TASK_SIZE overlaps with KERNEL_START address
92 #define TASK_SIZE (CONFIG_TASK_SIZE)
94 /* This decides where the kernel will search for a free chunk of vm
95 * space during mmap's.
97 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
101 /* 64-bit user address space is 46-bits (64TB user VM) */
102 #define TASK_SIZE_USER64 (0x0000400000000000UL)
105 * 32-bit user address space is 4GB - 1 page
106 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
108 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
110 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
111 TASK_SIZE_USER32 : TASK_SIZE_USER64)
112 #define TASK_SIZE TASK_SIZE_OF(current)
114 /* This decides where the kernel will search for a free chunk of vm
115 * space during mmap's.
117 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
118 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
120 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
121 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
126 #define STACK_TOP_USER64 TASK_SIZE_USER64
127 #define STACK_TOP_USER32 TASK_SIZE_USER32
129 #define STACK_TOP (is_32bit_task() ? \
130 STACK_TOP_USER32 : STACK_TOP_USER64)
132 #define STACK_TOP_MAX STACK_TOP_USER64
134 #else /* __powerpc64__ */
136 #define STACK_TOP TASK_SIZE
137 #define STACK_TOP_MAX STACK_TOP
139 #endif /* __powerpc64__ */
145 #define TS_FPROFFSET 0
146 #define TS_VSRLOWOFFSET 1
147 #define TS_FPR(i) fpr[i][TS_FPROFFSET]
148 #define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]
150 struct thread_struct
{
151 unsigned long ksp
; /* Kernel stack pointer */
152 unsigned long ksp_limit
; /* if ksp <= ksp_limit stack overflow */
155 unsigned long ksp_vsid
;
157 struct pt_regs
*regs
; /* Pointer to saved register state */
158 mm_segment_t fs
; /* for get_fs() validation */
160 /* BookE base exception scratch space; align on cacheline */
161 unsigned long normsave
[8] ____cacheline_aligned
;
164 void *pgdir
; /* root of page-table tree */
166 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
168 * The following help to manage the use of Debug Control Registers
169 * om the BookE platforms.
177 * The stored value of the DBSR register will be the value at the
178 * last debug interrupt. This register can only be read from the
179 * user (will never be written to) and has value while helping to
180 * describe the reason for the last debug trap. Torez
184 * The following will contain addresses used by debug applications
185 * to help trace and trap on particular address locations.
186 * The bits in the Debug Control Registers above help define which
187 * of the following registers will contain valid data and/or addresses.
191 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
197 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
202 /* FP and VSX 0-31 register set */
203 double fpr
[32][TS_FPRWIDTH
] __attribute__((aligned(16)));
207 unsigned int val
; /* Floating point status */
209 int fpexc_mode
; /* floating-point exception mode */
210 unsigned int align_ctl
; /* alignment handling control */
212 unsigned long start_tb
; /* Start purr when proc switched in */
213 unsigned long accum_tb
; /* Total accumilated purr for process */
214 #ifdef CONFIG_HAVE_HW_BREAKPOINT
215 struct perf_event
*ptrace_bps
[HBP_NUM
];
217 * Helps identify source of single-step exception and subsequent
218 * hw-breakpoint enablement
220 struct perf_event
*last_hit_ubp
;
221 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
223 struct arch_hw_breakpoint hw_brk
; /* info on the hardware breakpoint */
224 unsigned long trap_nr
; /* last trap # on this thread */
225 #ifdef CONFIG_ALTIVEC
226 /* Complete AltiVec register set */
227 vector128 vr
[32] __attribute__((aligned(16)));
229 vector128 vscr
__attribute__((aligned(16)));
230 unsigned long vrsave
;
231 int used_vr
; /* set if process has used altivec */
232 #endif /* CONFIG_ALTIVEC */
235 int used_vsr
; /* set if process has used altivec */
236 #endif /* CONFIG_VSX */
238 unsigned long evr
[32]; /* upper 32-bits of SPE regs */
239 u64 acc
; /* Accumulator */
240 unsigned long spefscr
; /* SPE & eFP status */
241 int used_spe
; /* set if process has used spe */
242 #endif /* CONFIG_SPE */
243 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
244 u64 tm_tfhar
; /* Transaction fail handler addr */
245 u64 tm_texasr
; /* Transaction exception & summary */
246 u64 tm_tfiar
; /* Transaction fail instr address reg */
247 unsigned long tm_orig_msr
; /* Thread's MSR on ctx switch */
248 struct pt_regs ckpt_regs
; /* Checkpointed registers */
251 * Transactional FP and VSX 0-31 register set.
252 * NOTE: the sense of these is the opposite of the integer ckpt_regs!
254 * When a transaction is active/signalled/scheduled etc., *regs is the
255 * most recent set of/speculated GPRs with ckpt_regs being the older
256 * checkpointed regs to which we roll back if transaction aborts.
258 * However, fpr[] is the checkpointed 'base state' of FP regs, and
259 * transact_fpr[] is the new set of transactional values.
260 * VRs work the same way.
262 double transact_fpr
[32][TS_FPRWIDTH
];
265 unsigned int val
; /* Floating point status */
267 vector128 transact_vr
[32] __attribute__((aligned(16)));
268 vector128 transact_vscr
__attribute__((aligned(16)));
269 unsigned long transact_vrsave
;
270 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
271 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
272 void* kvm_shadow_vcpu
; /* KVM internal data */
273 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
274 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
275 struct kvm_vcpu
*kvm_vcpu
;
280 unsigned long ppr
; /* used to save/restore SMT priority */
282 #ifdef CONFIG_PPC_BOOK3S_64
296 #define ARCH_MIN_TASKALIGN 16
298 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
299 #define INIT_SP_LIMIT \
300 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
303 #define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
309 #define INIT_THREAD { \
311 .ksp_limit = INIT_SP_LIMIT, \
313 .pgdir = swapper_pg_dir, \
314 .fpexc_mode = MSR_FE0 | MSR_FE1, \
318 #define INIT_THREAD { \
320 .ksp_limit = INIT_SP_LIMIT, \
321 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
324 .fpscr = { .val = 0, }, \
331 * Return saved PC of a blocked thread. For now, this is the "user" PC
333 #define thread_saved_pc(tsk) \
334 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
336 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
338 unsigned long get_wchan(struct task_struct
*p
);
340 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
341 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
343 /* Get/set floating-point exception mode */
344 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
345 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
347 extern int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
);
348 extern int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
);
350 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
351 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
353 extern int get_endian(struct task_struct
*tsk
, unsigned long adr
);
354 extern int set_endian(struct task_struct
*tsk
, unsigned int val
);
356 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
357 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
359 extern int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
);
360 extern int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
);
362 static inline unsigned int __unpack_fe01(unsigned long msr_bits
)
364 return ((msr_bits
& MSR_FE0
) >> 10) | ((msr_bits
& MSR_FE1
) >> 8);
367 static inline unsigned long __pack_fe01(unsigned int fpmode
)
369 return ((fpmode
<< 10) & MSR_FE0
) | ((fpmode
<< 8) & MSR_FE1
);
373 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
375 #define cpu_relax() barrier()
378 /* Check that a certain kernel stack pointer is valid in task_struct p */
379 int validate_sp(unsigned long sp
, struct task_struct
*p
,
380 unsigned long nbytes
);
385 #define ARCH_HAS_PREFETCH
386 #define ARCH_HAS_PREFETCHW
387 #define ARCH_HAS_SPINLOCK_PREFETCH
389 static inline void prefetch(const void *x
)
394 __asm__
__volatile__ ("dcbt 0,%0" : : "r" (x
));
397 static inline void prefetchw(const void *x
)
402 __asm__
__volatile__ ("dcbtst 0,%0" : : "r" (x
));
405 #define spin_lock_prefetch(x) prefetchw(x)
407 #define HAVE_ARCH_PICK_MMAP_LAYOUT
410 static inline unsigned long get_clean_sp(unsigned long sp
, int is_32
)
413 return sp
& 0x0ffffffffUL
;
417 static inline unsigned long get_clean_sp(unsigned long sp
, int is_32
)
423 extern unsigned long cpuidle_disable
;
424 enum idle_boot_override
{IDLE_NO_OVERRIDE
= 0, IDLE_POWERSAVE_OFF
};
426 extern int powersave_nap
; /* set if nap mode can be used in idle loop */
427 extern void power7_nap(void);
429 #ifdef CONFIG_PSERIES_IDLE
430 extern void update_smt_snooze_delay(int cpu
, int residency
);
432 static inline void update_smt_snooze_delay(int cpu
, int residency
) {}
435 extern void flush_instruction_cache(void);
436 extern void hard_reset_now(void);
437 extern void poweroff_now(void);
438 extern int fix_alignment(struct pt_regs
*);
439 extern void cvt_fd(float *from
, double *to
);
440 extern void cvt_df(double *from
, float *to
);
441 extern void _nmask_and_or_msr(unsigned long nmask
, unsigned long or_val
);
445 * We handle most unaligned accesses in hardware. On the other hand
446 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
447 * powers of 2 writes until it reaches sufficient alignment).
449 * Based on this we disable the IP header alignment in network drivers.
451 #define NET_IP_ALIGN 0
454 #endif /* __KERNEL__ */
455 #endif /* __ASSEMBLY__ */
456 #endif /* _ASM_POWERPC_PROCESSOR_H */