arch/powerpc/kernel/cpu_setup_fsl_booke.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  * Kumar Gala <galak@kernel.crashing.org>
   4  * Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * Based on cpu_setup_6xx code by
   7  * Benjamin Herrenschmidt <benh@kernel.crashing.org>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  */
  15
  16 #include <asm/processor.h>
  17 #include <asm/cputable.h>
  18 #include <asm/ppc_asm.h>
  19 #include <asm/mmu-book3e.h>
  20 #include <asm/asm-offsets.h>
  21
  22 _GLOBAL(__e500_icache_setup)
  23         mfspr   r0, SPRN_L1CSR1
  24         andi.   r3, r0, L1CSR1_ICE
  25         bnelr                           /* Already enabled */
  26         oris    r0, r0, L1CSR1_CPE@h
  27         ori     r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR |  L1CSR1_ICE)
  28         mtspr   SPRN_L1CSR1, r0         /* Enable I-Cache */
  29         isync
  30         blr
  31
  32 _GLOBAL(__e500_dcache_setup)
  33         mfspr   r0, SPRN_L1CSR0
  34         andi.   r3, r0, L1CSR0_DCE
  35         bnelr                           /* Already enabled */
  36         msync
  37         isync
  38         li      r0, 0
  39         mtspr   SPRN_L1CSR0, r0         /* Disable */
  40         msync
  41         isync
  42         li      r0, (L1CSR0_DCFI | L1CSR0_CLFC)
  43         mtspr   SPRN_L1CSR0, r0         /* Invalidate */
  44         isync
  45 1:      mfspr   r0, SPRN_L1CSR0
  46         andi.   r3, r0, L1CSR0_CLFC
  47         bne+    1b                      /* Wait for lock bits reset */
  48         oris    r0, r0, L1CSR0_CPE@h
  49         ori     r0, r0, L1CSR0_DCE
  50         msync
  51         isync
  52         mtspr   SPRN_L1CSR0, r0         /* Enable */
  53         isync
  54         blr
  55
  56 #ifdef CONFIG_PPC32
  57 _GLOBAL(__setup_cpu_e200)
  58         /* enable dedicated debug exception handling resources (Debug APU) */
  59         mfspr   r3,SPRN_HID0
  60         ori     r3,r3,HID0_DAPUEN@l
  61         mtspr   SPRN_HID0,r3
  62         b       __setup_e200_ivors
  63 _GLOBAL(__setup_cpu_e500v1)
  64 _GLOBAL(__setup_cpu_e500v2)
  65         mflr    r4
  66         bl      __e500_icache_setup
  67         bl      __e500_dcache_setup
  68         bl      __setup_e500_ivors
  69 #ifdef CONFIG_FSL_RIO
  70         /* Ensure that RFXE is set */
  71         mfspr   r3,SPRN_HID1
  72         oris    r3,r3,HID1_RFXE@h
  73         mtspr   SPRN_HID1,r3
  74 #endif
  75         mtlr    r4
  76         blr
  77 _GLOBAL(__setup_cpu_e500mc)
  78 _GLOBAL(__setup_cpu_e5500)
  79         mflr    r5
  80         bl      __e500_icache_setup
  81         bl      __e500_dcache_setup
  82         bl      __setup_e500mc_ivors
  83         /*
  84          * We only want to touch IVOR38-41 if we're running on hardware
  85          * that supports category E.HV.  The architectural way to determine
  86          * this is MMUCFG[LPIDSIZE].
  87          */
  88         mfspr   r3, SPRN_MMUCFG
  89         rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
  90         beq     1f
  91         bl      __setup_ehv_ivors
  92         b       2f
  93 1:
  94         lwz     r3, CPU_SPEC_FEATURES(r4)
  95         /* We need this check as cpu_setup is also called for
  96          * the secondary cores. So, if we have already cleared
  97          * the feature on the primary core, avoid doing it on the
  98          * secondary core.
  99          */
 100         andis.  r6, r3, CPU_FTR_EMB_HV@h
 101         beq     2f
 102         rlwinm  r3, r3, 0, ~CPU_FTR_EMB_HV
 103         stw     r3, CPU_SPEC_FEATURES(r4)
 104 2:
 105         mtlr    r5
 106         blr
 107 #endif
 108
 109 #ifdef CONFIG_PPC_BOOK3E_64
 110 _GLOBAL(__restore_cpu_e5500)
 111         mflr    r4
 112         bl      __e500_icache_setup
 113         bl      __e500_dcache_setup
 114         bl      .__setup_base_ivors
 115         bl      .setup_perfmon_ivor
 116         bl      .setup_doorbell_ivors
 117         /*
 118          * We only want to touch IVOR38-41 if we're running on hardware
 119          * that supports category E.HV.  The architectural way to determine
 120          * this is MMUCFG[LPIDSIZE].
 121          */
 122         mfspr   r10,SPRN_MMUCFG
 123         rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
 124         beq     1f
 125         bl      .setup_ehv_ivors
 126 1:
 127         mtlr    r4
 128         blr
 129
 130 _GLOBAL(__setup_cpu_e5500)
 131         mflr    r5
 132         bl      __e500_icache_setup
 133         bl      __e500_dcache_setup
 134         bl      .__setup_base_ivors
 135         bl      .setup_perfmon_ivor
 136         bl      .setup_doorbell_ivors
 137         /*
 138          * We only want to touch IVOR38-41 if we're running on hardware
 139          * that supports category E.HV.  The architectural way to determine
 140          * this is MMUCFG[LPIDSIZE].
 141          */
 142         mfspr   r10,SPRN_MMUCFG
 143         rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
 144         beq     1f
 145         bl      .setup_ehv_ivors
 146         b       2f
 147 1:
 148         ld      r10,CPU_SPEC_FEATURES(r4)
 149         LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
 150         andc    r10,r10,r9
 151         std     r10,CPU_SPEC_FEATURES(r4)
 152 2:
 153         mtlr    r5
 154         blr
 155 #endif