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powerpc: Save the TAR register earlier
[deliverable/linux.git] / arch / powerpc / kernel / entry_64.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
31 #include <asm/bug.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
37
38 /*
39 * System calls.
40 */
41 .section ".toc","aw"
42 .SYS_CALL_TABLE:
43 .tc .sys_call_table[TC],.sys_call_table
44
45 /* This value is used to mark exception frames on the stack. */
46 exception_marker:
47 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
48
49 .section ".text"
50 .align 7
51
52 #undef SHOW_SYSCALLS
53
54 .globl system_call_common
55 system_call_common:
56 andi. r10,r12,MSR_PR
57 mr r10,r1
58 addi r1,r1,-INT_FRAME_SIZE
59 beq- 1f
60 ld r1,PACAKSAVE(r13)
61 1: std r10,0(r1)
62 std r11,_NIP(r1)
63 std r12,_MSR(r1)
64 std r0,GPR0(r1)
65 std r10,GPR1(r1)
66 beq 2f /* if from kernel mode */
67 ACCOUNT_CPU_USER_ENTRY(r10, r11)
68 2: std r2,GPR2(r1)
69 std r3,GPR3(r1)
70 mfcr r2
71 std r4,GPR4(r1)
72 std r5,GPR5(r1)
73 std r6,GPR6(r1)
74 std r7,GPR7(r1)
75 std r8,GPR8(r1)
76 li r11,0
77 std r11,GPR9(r1)
78 std r11,GPR10(r1)
79 std r11,GPR11(r1)
80 std r11,GPR12(r1)
81 std r11,_XER(r1)
82 std r11,_CTR(r1)
83 std r9,GPR13(r1)
84 mflr r10
85 /*
86 * This clears CR0.SO (bit 28), which is the error indication on
87 * return from this system call.
88 */
89 rldimi r2,r11,28,(63-28)
90 li r11,0xc01
91 std r10,_LINK(r1)
92 std r11,_TRAP(r1)
93 std r3,ORIG_GPR3(r1)
94 std r2,_CCR(r1)
95 ld r2,PACATOC(r13)
96 addi r9,r1,STACK_FRAME_OVERHEAD
97 ld r11,exception_marker@toc(r2)
98 std r11,-16(r9) /* "regshere" marker */
99 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
100 BEGIN_FW_FTR_SECTION
101 beq 33f
102 /* if from user, see if there are any DTL entries to process */
103 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
104 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
105 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
106 cmpd cr1,r11,r10
107 beq+ cr1,33f
108 bl .accumulate_stolen_time
109 REST_GPR(0,r1)
110 REST_4GPRS(3,r1)
111 REST_2GPRS(7,r1)
112 addi r9,r1,STACK_FRAME_OVERHEAD
113 33:
114 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
115 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
116
117 /*
118 * A syscall should always be called with interrupts enabled
119 * so we just unconditionally hard-enable here. When some kind
120 * of irq tracing is used, we additionally check that condition
121 * is correct
122 */
123 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
124 lbz r10,PACASOFTIRQEN(r13)
125 xori r10,r10,1
126 1: tdnei r10,0
127 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
128 #endif
129
130 #ifdef CONFIG_PPC_BOOK3E
131 wrteei 1
132 #else
133 ld r11,PACAKMSR(r13)
134 ori r11,r11,MSR_EE
135 mtmsrd r11,1
136 #endif /* CONFIG_PPC_BOOK3E */
137
138 /* We do need to set SOFTE in the stack frame or the return
139 * from interrupt will be painful
140 */
141 li r10,1
142 std r10,SOFTE(r1)
143
144 #ifdef SHOW_SYSCALLS
145 bl .do_show_syscall
146 REST_GPR(0,r1)
147 REST_4GPRS(3,r1)
148 REST_2GPRS(7,r1)
149 addi r9,r1,STACK_FRAME_OVERHEAD
150 #endif
151 CURRENT_THREAD_INFO(r11, r1)
152 ld r10,TI_FLAGS(r11)
153 andi. r11,r10,_TIF_SYSCALL_T_OR_A
154 bne syscall_dotrace
155 .Lsyscall_dotrace_cont:
156 cmpldi 0,r0,NR_syscalls
157 bge- syscall_enosys
158
159 system_call: /* label this so stack traces look sane */
160 /*
161 * Need to vector to 32 Bit or default sys_call_table here,
162 * based on caller's run-mode / personality.
163 */
164 ld r11,.SYS_CALL_TABLE@toc(2)
165 andi. r10,r10,_TIF_32BIT
166 beq 15f
167 addi r11,r11,8 /* use 32-bit syscall entries */
168 clrldi r3,r3,32
169 clrldi r4,r4,32
170 clrldi r5,r5,32
171 clrldi r6,r6,32
172 clrldi r7,r7,32
173 clrldi r8,r8,32
174 15:
175 slwi r0,r0,4
176 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
177 mtctr r10
178 bctrl /* Call handler */
179
180 syscall_exit:
181 std r3,RESULT(r1)
182 #ifdef SHOW_SYSCALLS
183 bl .do_show_syscall_exit
184 ld r3,RESULT(r1)
185 #endif
186 CURRENT_THREAD_INFO(r12, r1)
187
188 ld r8,_MSR(r1)
189 #ifdef CONFIG_PPC_BOOK3S
190 /* No MSR:RI on BookE */
191 andi. r10,r8,MSR_RI
192 beq- unrecov_restore
193 #endif
194 /*
195 * Disable interrupts so current_thread_info()->flags can't change,
196 * and so that we don't get interrupted after loading SRR0/1.
197 */
198 #ifdef CONFIG_PPC_BOOK3E
199 wrteei 0
200 #else
201 ld r10,PACAKMSR(r13)
202 /*
203 * For performance reasons we clear RI the same time that we
204 * clear EE. We only need to clear RI just before we restore r13
205 * below, but batching it with EE saves us one expensive mtmsrd call.
206 * We have to be careful to restore RI if we branch anywhere from
207 * here (eg syscall_exit_work).
208 */
209 li r9,MSR_RI
210 andc r11,r10,r9
211 mtmsrd r11,1
212 #endif /* CONFIG_PPC_BOOK3E */
213
214 ld r9,TI_FLAGS(r12)
215 li r11,-_LAST_ERRNO
216 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
217 bne- syscall_exit_work
218 cmpld r3,r11
219 ld r5,_CCR(r1)
220 bge- syscall_error
221 .Lsyscall_error_cont:
222 ld r7,_NIP(r1)
223 BEGIN_FTR_SECTION
224 stdcx. r0,0,r1 /* to clear the reservation */
225 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
226 andi. r6,r8,MSR_PR
227 ld r4,_LINK(r1)
228
229 beq- 1f
230 ACCOUNT_CPU_USER_EXIT(r11, r12)
231 HMT_MEDIUM_LOW_HAS_PPR
232 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
233 1: ld r2,GPR2(r1)
234 ld r1,GPR1(r1)
235 mtlr r4
236 mtcr r5
237 mtspr SPRN_SRR0,r7
238 mtspr SPRN_SRR1,r8
239 RFI
240 b . /* prevent speculative execution */
241
242 syscall_error:
243 oris r5,r5,0x1000 /* Set SO bit in CR */
244 neg r3,r3
245 std r5,_CCR(r1)
246 b .Lsyscall_error_cont
247
248 /* Traced system call support */
249 syscall_dotrace:
250 bl .save_nvgprs
251 addi r3,r1,STACK_FRAME_OVERHEAD
252 bl .do_syscall_trace_enter
253 /*
254 * Restore argument registers possibly just changed.
255 * We use the return value of do_syscall_trace_enter
256 * for the call number to look up in the table (r0).
257 */
258 mr r0,r3
259 ld r3,GPR3(r1)
260 ld r4,GPR4(r1)
261 ld r5,GPR5(r1)
262 ld r6,GPR6(r1)
263 ld r7,GPR7(r1)
264 ld r8,GPR8(r1)
265 addi r9,r1,STACK_FRAME_OVERHEAD
266 CURRENT_THREAD_INFO(r10, r1)
267 ld r10,TI_FLAGS(r10)
268 b .Lsyscall_dotrace_cont
269
270 syscall_enosys:
271 li r3,-ENOSYS
272 b syscall_exit
273
274 syscall_exit_work:
275 #ifdef CONFIG_PPC_BOOK3S
276 mtmsrd r10,1 /* Restore RI */
277 #endif
278 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
279 If TIF_NOERROR is set, just save r3 as it is. */
280
281 andi. r0,r9,_TIF_RESTOREALL
282 beq+ 0f
283 REST_NVGPRS(r1)
284 b 2f
285 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
286 blt+ 1f
287 andi. r0,r9,_TIF_NOERROR
288 bne- 1f
289 ld r5,_CCR(r1)
290 neg r3,r3
291 oris r5,r5,0x1000 /* Set SO bit in CR */
292 std r5,_CCR(r1)
293 1: std r3,GPR3(r1)
294 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
295 beq 4f
296
297 /* Clear per-syscall TIF flags if any are set. */
298
299 li r11,_TIF_PERSYSCALL_MASK
300 addi r12,r12,TI_FLAGS
301 3: ldarx r10,0,r12
302 andc r10,r10,r11
303 stdcx. r10,0,r12
304 bne- 3b
305 subi r12,r12,TI_FLAGS
306
307 4: /* Anything else left to do? */
308 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
309 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
310 beq .ret_from_except_lite
311
312 /* Re-enable interrupts */
313 #ifdef CONFIG_PPC_BOOK3E
314 wrteei 1
315 #else
316 ld r10,PACAKMSR(r13)
317 ori r10,r10,MSR_EE
318 mtmsrd r10,1
319 #endif /* CONFIG_PPC_BOOK3E */
320
321 bl .save_nvgprs
322 addi r3,r1,STACK_FRAME_OVERHEAD
323 bl .do_syscall_trace_leave
324 b .ret_from_except
325
326 /* Save non-volatile GPRs, if not already saved. */
327 _GLOBAL(save_nvgprs)
328 ld r11,_TRAP(r1)
329 andi. r0,r11,1
330 beqlr-
331 SAVE_NVGPRS(r1)
332 clrrdi r0,r11,1
333 std r0,_TRAP(r1)
334 blr
335
336
337 /*
338 * The sigsuspend and rt_sigsuspend system calls can call do_signal
339 * and thus put the process into the stopped state where we might
340 * want to examine its user state with ptrace. Therefore we need
341 * to save all the nonvolatile registers (r14 - r31) before calling
342 * the C code. Similarly, fork, vfork and clone need the full
343 * register state on the stack so that it can be copied to the child.
344 */
345
346 _GLOBAL(ppc_fork)
347 bl .save_nvgprs
348 bl .sys_fork
349 b syscall_exit
350
351 _GLOBAL(ppc_vfork)
352 bl .save_nvgprs
353 bl .sys_vfork
354 b syscall_exit
355
356 _GLOBAL(ppc_clone)
357 bl .save_nvgprs
358 bl .sys_clone
359 b syscall_exit
360
361 _GLOBAL(ppc32_swapcontext)
362 bl .save_nvgprs
363 bl .compat_sys_swapcontext
364 b syscall_exit
365
366 _GLOBAL(ppc64_swapcontext)
367 bl .save_nvgprs
368 bl .sys_swapcontext
369 b syscall_exit
370
371 _GLOBAL(ret_from_fork)
372 bl .schedule_tail
373 REST_NVGPRS(r1)
374 li r3,0
375 b syscall_exit
376
377 _GLOBAL(ret_from_kernel_thread)
378 bl .schedule_tail
379 REST_NVGPRS(r1)
380 ld r14, 0(r14)
381 mtlr r14
382 mr r3,r15
383 blrl
384 li r3,0
385 b syscall_exit
386
387 .section ".toc","aw"
388 DSCR_DEFAULT:
389 .tc dscr_default[TC],dscr_default
390
391 .section ".text"
392
393 /*
394 * This routine switches between two different tasks. The process
395 * state of one is saved on its kernel stack. Then the state
396 * of the other is restored from its kernel stack. The memory
397 * management hardware is updated to the second process's state.
398 * Finally, we can return to the second process, via ret_from_except.
399 * On entry, r3 points to the THREAD for the current task, r4
400 * points to the THREAD for the new task.
401 *
402 * Note: there are two ways to get to the "going out" portion
403 * of this code; either by coming in via the entry (_switch)
404 * or via "fork" which must set up an environment equivalent
405 * to the "_switch" path. If you change this you'll have to change
406 * the fork code also.
407 *
408 * The code which creates the new task context is in 'copy_thread'
409 * in arch/powerpc/kernel/process.c
410 */
411 .align 7
412 _GLOBAL(_switch)
413 mflr r0
414 std r0,16(r1)
415 stdu r1,-SWITCH_FRAME_SIZE(r1)
416 /* r3-r13 are caller saved -- Cort */
417 SAVE_8GPRS(14, r1)
418 SAVE_10GPRS(22, r1)
419 mflr r20 /* Return to switch caller */
420 mfmsr r22
421 li r0, MSR_FP
422 #ifdef CONFIG_VSX
423 BEGIN_FTR_SECTION
424 oris r0,r0,MSR_VSX@h /* Disable VSX */
425 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
426 #endif /* CONFIG_VSX */
427 #ifdef CONFIG_ALTIVEC
428 BEGIN_FTR_SECTION
429 oris r0,r0,MSR_VEC@h /* Disable altivec */
430 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
431 std r24,THREAD_VRSAVE(r3)
432 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
433 #endif /* CONFIG_ALTIVEC */
434 #ifdef CONFIG_PPC64
435 BEGIN_FTR_SECTION
436 mfspr r25,SPRN_DSCR
437 std r25,THREAD_DSCR(r3)
438 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
439 #endif
440 and. r0,r0,r22
441 beq+ 1f
442 andc r22,r22,r0
443 MTMSRD(r22)
444 isync
445 1: std r20,_NIP(r1)
446 mfcr r23
447 std r23,_CCR(r1)
448 std r1,KSP(r3) /* Set old stack pointer */
449
450 #ifdef CONFIG_PPC_BOOK3S_64
451 BEGIN_FTR_SECTION
452 /* Event based branch registers */
453 mfspr r0, SPRN_BESCR
454 std r0, THREAD_BESCR(r3)
455 mfspr r0, SPRN_EBBHR
456 std r0, THREAD_EBBHR(r3)
457 mfspr r0, SPRN_EBBRR
458 std r0, THREAD_EBBRR(r3)
459 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
460 #endif
461
462 #ifdef CONFIG_SMP
463 /* We need a sync somewhere here to make sure that if the
464 * previous task gets rescheduled on another CPU, it sees all
465 * stores it has performed on this one.
466 */
467 sync
468 #endif /* CONFIG_SMP */
469
470 /*
471 * If we optimise away the clear of the reservation in system
472 * calls because we know the CPU tracks the address of the
473 * reservation, then we need to clear it here to cover the
474 * case that the kernel context switch path has no larx
475 * instructions.
476 */
477 BEGIN_FTR_SECTION
478 ldarx r6,0,r1
479 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
480
481 #ifdef CONFIG_PPC_BOOK3S
482 /* Cancel all explict user streams as they will have no use after context
483 * switch and will stop the HW from creating streams itself
484 */
485 DCBT_STOP_ALL_STREAM_IDS(r6)
486 #endif
487
488 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
489 std r6,PACACURRENT(r13) /* Set new 'current' */
490
491 ld r8,KSP(r4) /* new stack pointer */
492 #ifdef CONFIG_PPC_BOOK3S
493 BEGIN_FTR_SECTION
494 BEGIN_FTR_SECTION_NESTED(95)
495 clrrdi r6,r8,28 /* get its ESID */
496 clrrdi r9,r1,28 /* get current sp ESID */
497 FTR_SECTION_ELSE_NESTED(95)
498 clrrdi r6,r8,40 /* get its 1T ESID */
499 clrrdi r9,r1,40 /* get current sp 1T ESID */
500 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
501 FTR_SECTION_ELSE
502 b 2f
503 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
504 clrldi. r0,r6,2 /* is new ESID c00000000? */
505 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
506 cror eq,4*cr1+eq,eq
507 beq 2f /* if yes, don't slbie it */
508
509 /* Bolt in the new stack SLB entry */
510 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
511 oris r0,r6,(SLB_ESID_V)@h
512 ori r0,r0,(SLB_NUM_BOLTED-1)@l
513 BEGIN_FTR_SECTION
514 li r9,MMU_SEGSIZE_1T /* insert B field */
515 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
516 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
517 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
518
519 /* Update the last bolted SLB. No write barriers are needed
520 * here, provided we only update the current CPU's SLB shadow
521 * buffer.
522 */
523 ld r9,PACA_SLBSHADOWPTR(r13)
524 li r12,0
525 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
526 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
527 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
528
529 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
530 * we have 1TB segments, the only CPUs known to have the errata
531 * only support less than 1TB of system memory and we'll never
532 * actually hit this code path.
533 */
534
535 slbie r6
536 slbie r6 /* Workaround POWER5 < DD2.1 issue */
537 slbmte r7,r0
538 isync
539 2:
540 #endif /* !CONFIG_PPC_BOOK3S */
541
542 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
543 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
544 because we don't need to leave the 288-byte ABI gap at the
545 top of the kernel stack. */
546 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
547
548 mr r1,r8 /* start using new stack pointer */
549 std r7,PACAKSAVE(r13)
550
551 #ifdef CONFIG_PPC_BOOK3S_64
552 BEGIN_FTR_SECTION
553 /* Event based branch registers */
554 ld r0, THREAD_BESCR(r4)
555 mtspr SPRN_BESCR, r0
556 ld r0, THREAD_EBBHR(r4)
557 mtspr SPRN_EBBHR, r0
558 ld r0, THREAD_EBBRR(r4)
559 mtspr SPRN_EBBRR, r0
560
561 ld r0,THREAD_TAR(r4)
562 mtspr SPRN_TAR,r0
563 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
564 #endif
565
566 #ifdef CONFIG_ALTIVEC
567 BEGIN_FTR_SECTION
568 ld r0,THREAD_VRSAVE(r4)
569 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
570 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
571 #endif /* CONFIG_ALTIVEC */
572 #ifdef CONFIG_PPC64
573 BEGIN_FTR_SECTION
574 lwz r6,THREAD_DSCR_INHERIT(r4)
575 ld r7,DSCR_DEFAULT@toc(2)
576 ld r0,THREAD_DSCR(r4)
577 cmpwi r6,0
578 li r8, FSCR_DSCR
579 bne 1f
580 ld r0,0(r7)
581 b 3f
582 1:
583 BEGIN_FTR_SECTION_NESTED(70)
584 mfspr r6, SPRN_FSCR
585 or r6, r6, r8
586 mtspr SPRN_FSCR, r6
587 BEGIN_FTR_SECTION_NESTED(69)
588 mfspr r6, SPRN_HFSCR
589 or r6, r6, r8
590 mtspr SPRN_HFSCR, r6
591 END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
592 b 4f
593 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
594 3:
595 BEGIN_FTR_SECTION_NESTED(70)
596 mfspr r6, SPRN_FSCR
597 andc r6, r6, r8
598 mtspr SPRN_FSCR, r6
599 BEGIN_FTR_SECTION_NESTED(69)
600 mfspr r6, SPRN_HFSCR
601 andc r6, r6, r8
602 mtspr SPRN_HFSCR, r6
603 END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
604 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
605 4: cmpd r0,r25
606 beq 2f
607 mtspr SPRN_DSCR,r0
608 2:
609 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
610 #endif
611
612 ld r6,_CCR(r1)
613 mtcrf 0xFF,r6
614
615 /* r3-r13 are destroyed -- Cort */
616 REST_8GPRS(14, r1)
617 REST_10GPRS(22, r1)
618
619 /* convert old thread to its task_struct for return value */
620 addi r3,r3,-THREAD
621 ld r7,_NIP(r1) /* Return to _switch caller in new task */
622 mtlr r7
623 addi r1,r1,SWITCH_FRAME_SIZE
624 blr
625
626 .align 7
627 _GLOBAL(ret_from_except)
628 ld r11,_TRAP(r1)
629 andi. r0,r11,1
630 bne .ret_from_except_lite
631 REST_NVGPRS(r1)
632
633 _GLOBAL(ret_from_except_lite)
634 /*
635 * Disable interrupts so that current_thread_info()->flags
636 * can't change between when we test it and when we return
637 * from the interrupt.
638 */
639 #ifdef CONFIG_PPC_BOOK3E
640 wrteei 0
641 #else
642 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
643 mtmsrd r10,1 /* Update machine state */
644 #endif /* CONFIG_PPC_BOOK3E */
645
646 CURRENT_THREAD_INFO(r9, r1)
647 ld r3,_MSR(r1)
648 #ifdef CONFIG_PPC_BOOK3E
649 ld r10,PACACURRENT(r13)
650 #endif /* CONFIG_PPC_BOOK3E */
651 ld r4,TI_FLAGS(r9)
652 andi. r3,r3,MSR_PR
653 beq resume_kernel
654 #ifdef CONFIG_PPC_BOOK3E
655 lwz r3,(THREAD+THREAD_DBCR0)(r10)
656 #endif /* CONFIG_PPC_BOOK3E */
657
658 /* Check current_thread_info()->flags */
659 andi. r0,r4,_TIF_USER_WORK_MASK
660 #ifdef CONFIG_PPC_BOOK3E
661 bne 1f
662 /*
663 * Check to see if the dbcr0 register is set up to debug.
664 * Use the internal debug mode bit to do this.
665 */
666 andis. r0,r3,DBCR0_IDM@h
667 beq restore
668 mfmsr r0
669 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
670 mtmsr r0
671 mtspr SPRN_DBCR0,r3
672 li r10, -1
673 mtspr SPRN_DBSR,r10
674 b restore
675 #else
676 beq restore
677 #endif
678 1: andi. r0,r4,_TIF_NEED_RESCHED
679 beq 2f
680 bl .restore_interrupts
681 SCHEDULE_USER
682 b .ret_from_except_lite
683
684 2: bl .save_nvgprs
685 bl .restore_interrupts
686 addi r3,r1,STACK_FRAME_OVERHEAD
687 bl .do_notify_resume
688 b .ret_from_except
689
690 resume_kernel:
691 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
692 CURRENT_THREAD_INFO(r9, r1)
693 ld r8,TI_FLAGS(r9)
694 andis. r8,r8,_TIF_EMULATE_STACK_STORE@h
695 beq+ 1f
696
697 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
698
699 lwz r3,GPR1(r1)
700 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
701 mr r4,r1 /* src: current exception frame */
702 mr r1,r3 /* Reroute the trampoline frame to r1 */
703
704 /* Copy from the original to the trampoline. */
705 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
706 li r6,0 /* start offset: 0 */
707 mtctr r5
708 2: ldx r0,r6,r4
709 stdx r0,r6,r3
710 addi r6,r6,8
711 bdnz 2b
712
713 /* Do real store operation to complete stwu */
714 lwz r5,GPR1(r1)
715 std r8,0(r5)
716
717 /* Clear _TIF_EMULATE_STACK_STORE flag */
718 lis r11,_TIF_EMULATE_STACK_STORE@h
719 addi r5,r9,TI_FLAGS
720 0: ldarx r4,0,r5
721 andc r4,r4,r11
722 stdcx. r4,0,r5
723 bne- 0b
724 1:
725
726 #ifdef CONFIG_PREEMPT
727 /* Check if we need to preempt */
728 andi. r0,r4,_TIF_NEED_RESCHED
729 beq+ restore
730 /* Check that preempt_count() == 0 and interrupts are enabled */
731 lwz r8,TI_PREEMPT(r9)
732 cmpwi cr1,r8,0
733 ld r0,SOFTE(r1)
734 cmpdi r0,0
735 crandc eq,cr1*4+eq,eq
736 bne restore
737
738 /*
739 * Here we are preempting the current task. We want to make
740 * sure we are soft-disabled first
741 */
742 SOFT_DISABLE_INTS(r3,r4)
743 1: bl .preempt_schedule_irq
744
745 /* Re-test flags and eventually loop */
746 CURRENT_THREAD_INFO(r9, r1)
747 ld r4,TI_FLAGS(r9)
748 andi. r0,r4,_TIF_NEED_RESCHED
749 bne 1b
750
751 /*
752 * arch_local_irq_restore() from preempt_schedule_irq above may
753 * enable hard interrupt but we really should disable interrupts
754 * when we return from the interrupt, and so that we don't get
755 * interrupted after loading SRR0/1.
756 */
757 #ifdef CONFIG_PPC_BOOK3E
758 wrteei 0
759 #else
760 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
761 mtmsrd r10,1 /* Update machine state */
762 #endif /* CONFIG_PPC_BOOK3E */
763 #endif /* CONFIG_PREEMPT */
764
765 .globl fast_exc_return_irq
766 fast_exc_return_irq:
767 restore:
768 /*
769 * This is the main kernel exit path. First we check if we
770 * are about to re-enable interrupts
771 */
772 ld r5,SOFTE(r1)
773 lbz r6,PACASOFTIRQEN(r13)
774 cmpwi cr0,r5,0
775 beq restore_irq_off
776
777 /* We are enabling, were we already enabled ? Yes, just return */
778 cmpwi cr0,r6,1
779 beq cr0,do_restore
780
781 /*
782 * We are about to soft-enable interrupts (we are hard disabled
783 * at this point). We check if there's anything that needs to
784 * be replayed first.
785 */
786 lbz r0,PACAIRQHAPPENED(r13)
787 cmpwi cr0,r0,0
788 bne- restore_check_irq_replay
789
790 /*
791 * Get here when nothing happened while soft-disabled, just
792 * soft-enable and move-on. We will hard-enable as a side
793 * effect of rfi
794 */
795 restore_no_replay:
796 TRACE_ENABLE_INTS
797 li r0,1
798 stb r0,PACASOFTIRQEN(r13);
799
800 /*
801 * Final return path. BookE is handled in a different file
802 */
803 do_restore:
804 #ifdef CONFIG_PPC_BOOK3E
805 b .exception_return_book3e
806 #else
807 /*
808 * Clear the reservation. If we know the CPU tracks the address of
809 * the reservation then we can potentially save some cycles and use
810 * a larx. On POWER6 and POWER7 this is significantly faster.
811 */
812 BEGIN_FTR_SECTION
813 stdcx. r0,0,r1 /* to clear the reservation */
814 FTR_SECTION_ELSE
815 ldarx r4,0,r1
816 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
817
818 /*
819 * Some code path such as load_up_fpu or altivec return directly
820 * here. They run entirely hard disabled and do not alter the
821 * interrupt state. They also don't use lwarx/stwcx. and thus
822 * are known not to leave dangling reservations.
823 */
824 .globl fast_exception_return
825 fast_exception_return:
826 ld r3,_MSR(r1)
827 ld r4,_CTR(r1)
828 ld r0,_LINK(r1)
829 mtctr r4
830 mtlr r0
831 ld r4,_XER(r1)
832 mtspr SPRN_XER,r4
833
834 REST_8GPRS(5, r1)
835
836 andi. r0,r3,MSR_RI
837 beq- unrecov_restore
838
839 /*
840 * Clear RI before restoring r13. If we are returning to
841 * userspace and we take an exception after restoring r13,
842 * we end up corrupting the userspace r13 value.
843 */
844 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
845 andc r4,r4,r0 /* r0 contains MSR_RI here */
846 mtmsrd r4,1
847
848 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
849 /* TM debug */
850 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
851 #endif
852 /*
853 * r13 is our per cpu area, only restore it if we are returning to
854 * userspace the value stored in the stack frame may belong to
855 * another CPU.
856 */
857 andi. r0,r3,MSR_PR
858 beq 1f
859 ACCOUNT_CPU_USER_EXIT(r2, r4)
860 RESTORE_PPR(r2, r4)
861 REST_GPR(13, r1)
862 1:
863 mtspr SPRN_SRR1,r3
864
865 ld r2,_CCR(r1)
866 mtcrf 0xFF,r2
867 ld r2,_NIP(r1)
868 mtspr SPRN_SRR0,r2
869
870 ld r0,GPR0(r1)
871 ld r2,GPR2(r1)
872 ld r3,GPR3(r1)
873 ld r4,GPR4(r1)
874 ld r1,GPR1(r1)
875
876 rfid
877 b . /* prevent speculative execution */
878
879 #endif /* CONFIG_PPC_BOOK3E */
880
881 /*
882 * We are returning to a context with interrupts soft disabled.
883 *
884 * However, we may also about to hard enable, so we need to
885 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
886 * or that bit can get out of sync and bad things will happen
887 */
888 restore_irq_off:
889 ld r3,_MSR(r1)
890 lbz r7,PACAIRQHAPPENED(r13)
891 andi. r0,r3,MSR_EE
892 beq 1f
893 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
894 stb r7,PACAIRQHAPPENED(r13)
895 1: li r0,0
896 stb r0,PACASOFTIRQEN(r13);
897 TRACE_DISABLE_INTS
898 b do_restore
899
900 /*
901 * Something did happen, check if a re-emit is needed
902 * (this also clears paca->irq_happened)
903 */
904 restore_check_irq_replay:
905 /* XXX: We could implement a fast path here where we check
906 * for irq_happened being just 0x01, in which case we can
907 * clear it and return. That means that we would potentially
908 * miss a decrementer having wrapped all the way around.
909 *
910 * Still, this might be useful for things like hash_page
911 */
912 bl .__check_irq_replay
913 cmpwi cr0,r3,0
914 beq restore_no_replay
915
916 /*
917 * We need to re-emit an interrupt. We do so by re-using our
918 * existing exception frame. We first change the trap value,
919 * but we need to ensure we preserve the low nibble of it
920 */
921 ld r4,_TRAP(r1)
922 clrldi r4,r4,60
923 or r4,r4,r3
924 std r4,_TRAP(r1)
925
926 /*
927 * Then find the right handler and call it. Interrupts are
928 * still soft-disabled and we keep them that way.
929 */
930 cmpwi cr0,r3,0x500
931 bne 1f
932 addi r3,r1,STACK_FRAME_OVERHEAD;
933 bl .do_IRQ
934 b .ret_from_except
935 1: cmpwi cr0,r3,0x900
936 bne 1f
937 addi r3,r1,STACK_FRAME_OVERHEAD;
938 bl .timer_interrupt
939 b .ret_from_except
940 #ifdef CONFIG_PPC_DOORBELL
941 1:
942 #ifdef CONFIG_PPC_BOOK3E
943 cmpwi cr0,r3,0x280
944 #else
945 BEGIN_FTR_SECTION
946 cmpwi cr0,r3,0xe80
947 FTR_SECTION_ELSE
948 cmpwi cr0,r3,0xa00
949 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
950 #endif /* CONFIG_PPC_BOOK3E */
951 bne 1f
952 addi r3,r1,STACK_FRAME_OVERHEAD;
953 bl .doorbell_exception
954 b .ret_from_except
955 #endif /* CONFIG_PPC_DOORBELL */
956 1: b .ret_from_except /* What else to do here ? */
957
958 unrecov_restore:
959 addi r3,r1,STACK_FRAME_OVERHEAD
960 bl .unrecoverable_exception
961 b unrecov_restore
962
963 #ifdef CONFIG_PPC_RTAS
964 /*
965 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
966 * called with the MMU off.
967 *
968 * In addition, we need to be in 32b mode, at least for now.
969 *
970 * Note: r3 is an input parameter to rtas, so don't trash it...
971 */
972 _GLOBAL(enter_rtas)
973 mflr r0
974 std r0,16(r1)
975 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
976
977 /* Because RTAS is running in 32b mode, it clobbers the high order half
978 * of all registers that it saves. We therefore save those registers
979 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
980 */
981 SAVE_GPR(2, r1) /* Save the TOC */
982 SAVE_GPR(13, r1) /* Save paca */
983 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
984 SAVE_10GPRS(22, r1) /* ditto */
985
986 mfcr r4
987 std r4,_CCR(r1)
988 mfctr r5
989 std r5,_CTR(r1)
990 mfspr r6,SPRN_XER
991 std r6,_XER(r1)
992 mfdar r7
993 std r7,_DAR(r1)
994 mfdsisr r8
995 std r8,_DSISR(r1)
996
997 /* Temporary workaround to clear CR until RTAS can be modified to
998 * ignore all bits.
999 */
1000 li r0,0
1001 mtcr r0
1002
1003 #ifdef CONFIG_BUG
1004 /* There is no way it is acceptable to get here with interrupts enabled,
1005 * check it with the asm equivalent of WARN_ON
1006 */
1007 lbz r0,PACASOFTIRQEN(r13)
1008 1: tdnei r0,0
1009 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1010 #endif
1011
1012 /* Hard-disable interrupts */
1013 mfmsr r6
1014 rldicl r7,r6,48,1
1015 rotldi r7,r7,16
1016 mtmsrd r7,1
1017
1018 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1019 * so they are saved in the PACA which allows us to restore
1020 * our original state after RTAS returns.
1021 */
1022 std r1,PACAR1(r13)
1023 std r6,PACASAVEDMSR(r13)
1024
1025 /* Setup our real return addr */
1026 LOAD_REG_ADDR(r4,.rtas_return_loc)
1027 clrldi r4,r4,2 /* convert to realmode address */
1028 mtlr r4
1029
1030 li r0,0
1031 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1032 andc r0,r6,r0
1033
1034 li r9,1
1035 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1036 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
1037 andc r6,r0,r9
1038 sync /* disable interrupts so SRR0/1 */
1039 mtmsrd r0 /* don't get trashed */
1040
1041 LOAD_REG_ADDR(r4, rtas)
1042 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1043 ld r4,RTASBASE(r4) /* get the rtas->base value */
1044
1045 mtspr SPRN_SRR0,r5
1046 mtspr SPRN_SRR1,r6
1047 rfid
1048 b . /* prevent speculative execution */
1049
1050 _STATIC(rtas_return_loc)
1051 /* relocation is off at this point */
1052 GET_PACA(r4)
1053 clrldi r4,r4,2 /* convert to realmode address */
1054
1055 bcl 20,31,$+4
1056 0: mflr r3
1057 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
1058
1059 mfmsr r6
1060 li r0,MSR_RI
1061 andc r6,r6,r0
1062 sync
1063 mtmsrd r6
1064
1065 ld r1,PACAR1(r4) /* Restore our SP */
1066 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1067
1068 mtspr SPRN_SRR0,r3
1069 mtspr SPRN_SRR1,r4
1070 rfid
1071 b . /* prevent speculative execution */
1072
1073 .align 3
1074 1: .llong .rtas_restore_regs
1075
1076 _STATIC(rtas_restore_regs)
1077 /* relocation is on at this point */
1078 REST_GPR(2, r1) /* Restore the TOC */
1079 REST_GPR(13, r1) /* Restore paca */
1080 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1081 REST_10GPRS(22, r1) /* ditto */
1082
1083 GET_PACA(r13)
1084
1085 ld r4,_CCR(r1)
1086 mtcr r4
1087 ld r5,_CTR(r1)
1088 mtctr r5
1089 ld r6,_XER(r1)
1090 mtspr SPRN_XER,r6
1091 ld r7,_DAR(r1)
1092 mtdar r7
1093 ld r8,_DSISR(r1)
1094 mtdsisr r8
1095
1096 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1097 ld r0,16(r1) /* get return address */
1098
1099 mtlr r0
1100 blr /* return to caller */
1101
1102 #endif /* CONFIG_PPC_RTAS */
1103
1104 _GLOBAL(enter_prom)
1105 mflr r0
1106 std r0,16(r1)
1107 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1108
1109 /* Because PROM is running in 32b mode, it clobbers the high order half
1110 * of all registers that it saves. We therefore save those registers
1111 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1112 */
1113 SAVE_GPR(2, r1)
1114 SAVE_GPR(13, r1)
1115 SAVE_8GPRS(14, r1)
1116 SAVE_10GPRS(22, r1)
1117 mfcr r10
1118 mfmsr r11
1119 std r10,_CCR(r1)
1120 std r11,_MSR(r1)
1121
1122 /* Get the PROM entrypoint */
1123 mtlr r4
1124
1125 /* Switch MSR to 32 bits mode
1126 */
1127 #ifdef CONFIG_PPC_BOOK3E
1128 rlwinm r11,r11,0,1,31
1129 mtmsr r11
1130 #else /* CONFIG_PPC_BOOK3E */
1131 mfmsr r11
1132 li r12,1
1133 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1134 andc r11,r11,r12
1135 li r12,1
1136 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1137 andc r11,r11,r12
1138 mtmsrd r11
1139 #endif /* CONFIG_PPC_BOOK3E */
1140 isync
1141
1142 /* Enter PROM here... */
1143 blrl
1144
1145 /* Just make sure that r1 top 32 bits didn't get
1146 * corrupt by OF
1147 */
1148 rldicl r1,r1,0,32
1149
1150 /* Restore the MSR (back to 64 bits) */
1151 ld r0,_MSR(r1)
1152 MTMSRD(r0)
1153 isync
1154
1155 /* Restore other registers */
1156 REST_GPR(2, r1)
1157 REST_GPR(13, r1)
1158 REST_8GPRS(14, r1)
1159 REST_10GPRS(22, r1)
1160 ld r4,_CCR(r1)
1161 mtcr r4
1162
1163 addi r1,r1,PROM_FRAME_SIZE
1164 ld r0,16(r1)
1165 mtlr r0
1166 blr
1167
1168 #ifdef CONFIG_FUNCTION_TRACER
1169 #ifdef CONFIG_DYNAMIC_FTRACE
1170 _GLOBAL(mcount)
1171 _GLOBAL(_mcount)
1172 blr
1173
1174 _GLOBAL(ftrace_caller)
1175 /* Taken from output of objdump from lib64/glibc */
1176 mflr r3
1177 ld r11, 0(r1)
1178 stdu r1, -112(r1)
1179 std r3, 128(r1)
1180 ld r4, 16(r11)
1181 subi r3, r3, MCOUNT_INSN_SIZE
1182 .globl ftrace_call
1183 ftrace_call:
1184 bl ftrace_stub
1185 nop
1186 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1187 .globl ftrace_graph_call
1188 ftrace_graph_call:
1189 b ftrace_graph_stub
1190 _GLOBAL(ftrace_graph_stub)
1191 #endif
1192 ld r0, 128(r1)
1193 mtlr r0
1194 addi r1, r1, 112
1195 _GLOBAL(ftrace_stub)
1196 blr
1197 #else
1198 _GLOBAL(mcount)
1199 blr
1200
1201 _GLOBAL(_mcount)
1202 /* Taken from output of objdump from lib64/glibc */
1203 mflr r3
1204 ld r11, 0(r1)
1205 stdu r1, -112(r1)
1206 std r3, 128(r1)
1207 ld r4, 16(r11)
1208
1209 subi r3, r3, MCOUNT_INSN_SIZE
1210 LOAD_REG_ADDR(r5,ftrace_trace_function)
1211 ld r5,0(r5)
1212 ld r5,0(r5)
1213 mtctr r5
1214 bctrl
1215 nop
1216
1217
1218 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1219 b ftrace_graph_caller
1220 #endif
1221 ld r0, 128(r1)
1222 mtlr r0
1223 addi r1, r1, 112
1224 _GLOBAL(ftrace_stub)
1225 blr
1226
1227 #endif /* CONFIG_DYNAMIC_FTRACE */
1228
1229 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1230 _GLOBAL(ftrace_graph_caller)
1231 /* load r4 with local address */
1232 ld r4, 128(r1)
1233 subi r4, r4, MCOUNT_INSN_SIZE
1234
1235 /* get the parent address */
1236 ld r11, 112(r1)
1237 addi r3, r11, 16
1238
1239 bl .prepare_ftrace_return
1240 nop
1241
1242 ld r0, 128(r1)
1243 mtlr r0
1244 addi r1, r1, 112
1245 blr
1246
1247 _GLOBAL(return_to_handler)
1248 /* need to save return values */
1249 std r4, -24(r1)
1250 std r3, -16(r1)
1251 std r31, -8(r1)
1252 mr r31, r1
1253 stdu r1, -112(r1)
1254
1255 bl .ftrace_return_to_handler
1256 nop
1257
1258 /* return value has real return address */
1259 mtlr r3
1260
1261 ld r1, 0(r1)
1262 ld r4, -24(r1)
1263 ld r3, -16(r1)
1264 ld r31, -8(r1)
1265
1266 /* Jump back to real return address */
1267 blr
1268
1269 _GLOBAL(mod_return_to_handler)
1270 /* need to save return values */
1271 std r4, -32(r1)
1272 std r3, -24(r1)
1273 /* save TOC */
1274 std r2, -16(r1)
1275 std r31, -8(r1)
1276 mr r31, r1
1277 stdu r1, -112(r1)
1278
1279 /*
1280 * We are in a module using the module's TOC.
1281 * Switch to our TOC to run inside the core kernel.
1282 */
1283 ld r2, PACATOC(r13)
1284
1285 bl .ftrace_return_to_handler
1286 nop
1287
1288 /* return value has real return address */
1289 mtlr r3
1290
1291 ld r1, 0(r1)
1292 ld r4, -32(r1)
1293 ld r3, -24(r1)
1294 ld r2, -16(r1)
1295 ld r31, -8(r1)
1296
1297 /* Jump back to real return address */
1298 blr
1299 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1300 #endif /* CONFIG_FUNCTION_TRACER */
Linux kernel - Deliverables
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