arch/powerpc/kernel/idle_power7.S

   1 /*
   2  *  This file contains the power_save function for Power7 CPUs.
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/threads.h>
  11 #include <asm/processor.h>
  12 #include <asm/page.h>
  13 #include <asm/cputable.h>
  14 #include <asm/thread_info.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/ppc-opcode.h>
  18 #include <asm/hw_irq.h>
  19 #include <asm/kvm_book3s_asm.h>
  20 #include <asm/opal.h>
  21 #include <asm/cpuidle.h>
  22 #include <asm/book3s/64/mmu-hash.h>
  23
  24 #undef DEBUG
  25
  26 /*
  27  * Use unused space in the interrupt stack to save and restore
  28  * registers for winkle support.
  29  */
  30 #define _SDR1   GPR3
  31 #define _RPR    GPR4
  32 #define _SPURR  GPR5
  33 #define _PURR   GPR6
  34 #define _TSCR   GPR7
  35 #define _DSCR   GPR8
  36 #define _AMOR   GPR9
  37 #define _WORT   GPR10
  38 #define _WORC   GPR11
  39
  40 /* Idle state entry routines */
  41
  42 #define IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
  43         /* Magic NAP/SLEEP/WINKLE mode enter sequence */        \
  44         std     r0,0(r1);                                       \
  45         ptesync;                                                \
  46         ld      r0,0(r1);                                       \
  47 1:      cmp     cr0,r0,r0;                                      \
  48         bne     1b;                                             \
  49         IDLE_INST;                                              \
  50         b       .
  51
  52         .text
  53
  54 /*
  55  * Used by threads when the lock bit of core_idle_state is set.
  56  * Threads will spin in HMT_LOW until the lock bit is cleared.
  57  * r14 - pointer to core_idle_state
  58  * r15 - used to load contents of core_idle_state
  59  */
  60
  61 core_idle_lock_held:
  62         HMT_LOW
  63 3:      lwz     r15,0(r14)
  64         andi.   r15,r15,PNV_CORE_IDLE_LOCK_BIT
  65         bne     3b
  66         HMT_MEDIUM
  67         lwarx   r15,0,r14
  68         blr
  69
  70 /*
  71  * Pass requested state in r3:
  72  *      r3 - PNV_THREAD_NAP/SLEEP/WINKLE
  73  *
  74  * To check IRQ_HAPPENED in r4
  75  *      0 - don't check
  76  *      1 - check
  77  */
  78 _GLOBAL(power7_powersave_common)
  79         /* Use r3 to pass state nap/sleep/winkle */
  80         /* NAP is a state loss, we create a regs frame on the
  81          * stack, fill it up with the state we care about and
  82          * stick a pointer to it in PACAR1. We really only
  83          * need to save PC, some CR bits and the NV GPRs,
  84          * but for now an interrupt frame will do.
  85          */
  86         mflr    r0
  87         std     r0,16(r1)
  88         stdu    r1,-INT_FRAME_SIZE(r1)
  89         std     r0,_LINK(r1)
  90         std     r0,_NIP(r1)
  91
  92         /* Hard disable interrupts */
  93         mfmsr   r9
  94         rldicl  r9,r9,48,1
  95         rotldi  r9,r9,16
  96         mtmsrd  r9,1                    /* hard-disable interrupts */
  97
  98         /* Check if something happened while soft-disabled */
  99         lbz     r0,PACAIRQHAPPENED(r13)
 100         andi.   r0,r0,~PACA_IRQ_HARD_DIS@l
 101         beq     1f
 102         cmpwi   cr0,r4,0
 103         beq     1f
 104         addi    r1,r1,INT_FRAME_SIZE
 105         ld      r0,16(r1)
 106         li      r3,0                    /* Return 0 (no nap) */
 107         mtlr    r0
 108         blr
 109
 110 1:      /* We mark irqs hard disabled as this is the state we'll
 111          * be in when returning and we need to tell arch_local_irq_restore()
 112          * about it
 113          */
 114         li      r0,PACA_IRQ_HARD_DIS
 115         stb     r0,PACAIRQHAPPENED(r13)
 116
 117         /* We haven't lost state ... yet */
 118         li      r0,0
 119         stb     r0,PACA_NAPSTATELOST(r13)
 120
 121         /* Continue saving state */
 122         SAVE_GPR(2, r1)
 123         SAVE_NVGPRS(r1)
 124         mfcr    r4
 125         std     r4,_CCR(r1)
 126         std     r9,_MSR(r1)
 127         std     r1,PACAR1(r13)
 128
 129         /*
 130          * Go to real mode to do the nap, as required by the architecture.
 131          * Also, we need to be in real mode before setting hwthread_state,
 132          * because as soon as we do that, another thread can switch
 133          * the MMU context to the guest.
 134          */
 135         LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
 136         li      r6, MSR_RI
 137         andc    r6, r9, r6
 138         LOAD_REG_ADDR(r7, power7_enter_nap_mode)
 139         mtmsrd  r6, 1           /* clear RI before setting SRR0/1 */
 140         mtspr   SPRN_SRR0, r7
 141         mtspr   SPRN_SRR1, r5
 142         rfid
 143
 144         .globl  power7_enter_nap_mode
 145 power7_enter_nap_mode:
 146 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 147         /* Tell KVM we're napping */
 148         li      r4,KVM_HWTHREAD_IN_NAP
 149         stb     r4,HSTATE_HWTHREAD_STATE(r13)
 150 #endif
 151         stb     r3,PACA_THREAD_IDLE_STATE(r13)
 152         cmpwi   cr3,r3,PNV_THREAD_SLEEP
 153         bge     cr3,2f
 154         IDLE_STATE_ENTER_SEQ(PPC_NAP)
 155         /* No return */
 156 2:
 157         /* Sleep or winkle */
 158         lbz     r7,PACA_THREAD_MASK(r13)
 159         ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)
 160 lwarx_loop1:
 161         lwarx   r15,0,r14
 162
 163         andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
 164         bnel    core_idle_lock_held
 165
 166         andc    r15,r15,r7                      /* Clear thread bit */
 167
 168         andi.   r15,r15,PNV_CORE_IDLE_THREAD_BITS
 169
 170 /*
 171  * If cr0 = 0, then current thread is the last thread of the core entering
 172  * sleep. Last thread needs to execute the hardware bug workaround code if
 173  * required by the platform.
 174  * Make the workaround call unconditionally here. The below branch call is
 175  * patched out when the idle states are discovered if the platform does not
 176  * require it.
 177  */
 178 .global pnv_fastsleep_workaround_at_entry
 179 pnv_fastsleep_workaround_at_entry:
 180         beq     fastsleep_workaround_at_entry
 181
 182         stwcx.  r15,0,r14
 183         bne-    lwarx_loop1
 184         isync
 185
 186 common_enter: /* common code for all the threads entering sleep or winkle */
 187         bgt     cr3,enter_winkle
 188         IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
 189
 190 fastsleep_workaround_at_entry:
 191         ori     r15,r15,PNV_CORE_IDLE_LOCK_BIT
 192         stwcx.  r15,0,r14
 193         bne-    lwarx_loop1
 194         isync
 195
 196         /* Fast sleep workaround */
 197         li      r3,1
 198         li      r4,1
 199         li      r0,OPAL_CONFIG_CPU_IDLE_STATE
 200         bl      opal_call_realmode
 201
 202         /* Clear Lock bit */
 203         li      r0,0
 204         lwsync
 205         stw     r0,0(r14)
 206         b       common_enter
 207
 208 enter_winkle:
 209         /*
 210          * Note all register i.e per-core, per-subcore or per-thread is saved
 211          * here since any thread in the core might wake up first
 212          */
 213         mfspr   r3,SPRN_SDR1
 214         std     r3,_SDR1(r1)
 215         mfspr   r3,SPRN_RPR
 216         std     r3,_RPR(r1)
 217         mfspr   r3,SPRN_SPURR
 218         std     r3,_SPURR(r1)
 219         mfspr   r3,SPRN_PURR
 220         std     r3,_PURR(r1)
 221         mfspr   r3,SPRN_TSCR
 222         std     r3,_TSCR(r1)
 223         mfspr   r3,SPRN_DSCR
 224         std     r3,_DSCR(r1)
 225         mfspr   r3,SPRN_AMOR
 226         std     r3,_AMOR(r1)
 227         mfspr   r3,SPRN_WORT
 228         std     r3,_WORT(r1)
 229         mfspr   r3,SPRN_WORC
 230         std     r3,_WORC(r1)
 231         IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
 232
 233 _GLOBAL(power7_idle)
 234         /* Now check if user or arch enabled NAP mode */
 235         LOAD_REG_ADDRBASE(r3,powersave_nap)
 236         lwz     r4,ADDROFF(powersave_nap)(r3)
 237         cmpwi   0,r4,0
 238         beqlr
 239         li      r3, 1
 240         /* fall through */
 241
 242 _GLOBAL(power7_nap)
 243         mr      r4,r3
 244         li      r3,PNV_THREAD_NAP
 245         b       power7_powersave_common
 246         /* No return */
 247
 248 _GLOBAL(power7_sleep)
 249         li      r3,PNV_THREAD_SLEEP
 250         li      r4,1
 251         b       power7_powersave_common
 252         /* No return */
 253
 254 _GLOBAL(power7_winkle)
 255         li      r3,3
 256         li      r4,1
 257         b       power7_powersave_common
 258         /* No return */
 259
 260 #define CHECK_HMI_INTERRUPT                                             \
 261         mfspr   r0,SPRN_SRR1;                                           \
 262 BEGIN_FTR_SECTION_NESTED(66);                                           \
 263         rlwinm  r0,r0,45-31,0xf;  /* extract wake reason field (P8) */  \
 264 FTR_SECTION_ELSE_NESTED(66);                                            \
 265         rlwinm  r0,r0,45-31,0xe;  /* P7 wake reason field is 3 bits */  \
 266 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);                \
 267         cmpwi   r0,0xa;                 /* Hypervisor maintenance ? */  \
 268         bne     20f;                                                    \
 269         /* Invoke opal call to handle hmi */                            \
 270         ld      r2,PACATOC(r13);                                        \
 271         ld      r1,PACAR1(r13);                                         \
 272         std     r3,ORIG_GPR3(r1);       /* Save original r3 */          \
 273         li      r0,OPAL_HANDLE_HMI;     /* Pass opal token argument*/   \
 274         bl      opal_call_realmode;                                     \
 275         ld      r3,ORIG_GPR3(r1);       /* Restore original r3 */       \
 276 20:     nop;
 277
 278
 279 _GLOBAL(power7_wakeup_tb_loss)
 280         ld      r2,PACATOC(r13);
 281         ld      r1,PACAR1(r13)
 282         /*
 283          * Before entering any idle state, the NVGPRs are saved in the stack
 284          * and they are restored before switching to the process context. Hence
 285          * until they are restored, they are free to be used.
 286          *
 287          * Save SRR1 in a NVGPR as it might be clobbered in opal_call_realmode
 288          * (called in CHECK_HMI_INTERRUPT). SRR1 is required to determine the
 289          * wakeup reason if we branch to kvm_start_guest.
 290          */
 291
 292         mfspr   r16,SPRN_SRR1
 293 BEGIN_FTR_SECTION
 294         CHECK_HMI_INTERRUPT
 295 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 296
 297         lbz     r7,PACA_THREAD_MASK(r13)
 298         ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)
 299 lwarx_loop2:
 300         lwarx   r15,0,r14
 301         andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
 302         /*
 303          * Lock bit is set in one of the 2 cases-
 304          * a. In the sleep/winkle enter path, the last thread is executing
 305          * fastsleep workaround code.
 306          * b. In the wake up path, another thread is executing fastsleep
 307          * workaround undo code or resyncing timebase or restoring context
 308          * In either case loop until the lock bit is cleared.
 309          */
 310         bnel    core_idle_lock_held
 311
 312         cmpwi   cr2,r15,0
 313         lbz     r4,PACA_SUBCORE_SIBLING_MASK(r13)
 314         and     r4,r4,r15
 315         cmpwi   cr1,r4,0        /* Check if first in subcore */
 316
 317         /*
 318          * At this stage
 319          * cr1 - 0b0100 if first thread to wakeup in subcore
 320          * cr2 - 0b0100 if first thread to wakeup in core
 321          * cr3-  0b0010 if waking up from sleep or winkle
 322          * cr4 - 0b0100 if waking up from winkle
 323          */
 324
 325         or      r15,r15,r7              /* Set thread bit */
 326
 327         beq     cr1,first_thread_in_subcore
 328
 329         /* Not first thread in subcore to wake up */
 330         stwcx.  r15,0,r14
 331         bne-    lwarx_loop2
 332         isync
 333         b       common_exit
 334
 335 first_thread_in_subcore:
 336         /* First thread in subcore to wakeup */
 337         ori     r15,r15,PNV_CORE_IDLE_LOCK_BIT
 338         stwcx.  r15,0,r14
 339         bne-    lwarx_loop2
 340         isync
 341
 342         /*
 343          * If waking up from sleep, subcore state is not lost. Hence
 344          * skip subcore state restore
 345          */
 346         bne     cr4,subcore_state_restored
 347
 348         /* Restore per-subcore state */
 349         ld      r4,_SDR1(r1)
 350         mtspr   SPRN_SDR1,r4
 351         ld      r4,_RPR(r1)
 352         mtspr   SPRN_RPR,r4
 353         ld      r4,_AMOR(r1)
 354         mtspr   SPRN_AMOR,r4
 355
 356 subcore_state_restored:
 357         /*
 358          * Check if the thread is also the first thread in the core. If not,
 359          * skip to clear_lock.
 360          */
 361         bne     cr2,clear_lock
 362
 363 first_thread_in_core:
 364
 365         /*
 366          * First thread in the core waking up from fastsleep. It needs to
 367          * call the fastsleep workaround code if the platform requires it.
 368          * Call it unconditionally here. The below branch instruction will
 369          * be patched out when the idle states are discovered if platform
 370          * does not require workaround.
 371          */
 372 .global pnv_fastsleep_workaround_at_exit
 373 pnv_fastsleep_workaround_at_exit:
 374         b       fastsleep_workaround_at_exit
 375
 376 timebase_resync:
 377         /* Do timebase resync if we are waking up from sleep. Use cr3 value
 378          * set in exceptions-64s.S */
 379         ble     cr3,clear_lock
 380         /* Time base re-sync */
 381         li      r0,OPAL_RESYNC_TIMEBASE
 382         bl      opal_call_realmode;
 383         /* TODO: Check r3 for failure */
 384
 385         /*
 386          * If waking up from sleep, per core state is not lost, skip to
 387          * clear_lock.
 388          */
 389         bne     cr4,clear_lock
 390
 391         /* Restore per core state */
 392         ld      r4,_TSCR(r1)
 393         mtspr   SPRN_TSCR,r4
 394         ld      r4,_WORC(r1)
 395         mtspr   SPRN_WORC,r4
 396
 397 clear_lock:
 398         andi.   r15,r15,PNV_CORE_IDLE_THREAD_BITS
 399         lwsync
 400         stw     r15,0(r14)
 401
 402 common_exit:
 403         /*
 404          * Common to all threads.
 405          *
 406          * If waking up from sleep, hypervisor state is not lost. Hence
 407          * skip hypervisor state restore.
 408          */
 409         bne     cr4,hypervisor_state_restored
 410
 411         /* Waking up from winkle */
 412
 413         /* Restore per thread state */
 414         bl      __restore_cpu_power8
 415
 416         /* Restore SLB  from PACA */
 417         ld      r8,PACA_SLBSHADOWPTR(r13)
 418
 419         .rept   SLB_NUM_BOLTED
 420         li      r3, SLBSHADOW_SAVEAREA
 421         LDX_BE  r5, r8, r3
 422         addi    r3, r3, 8
 423         LDX_BE  r6, r8, r3
 424         andis.  r7,r5,SLB_ESID_V@h
 425         beq     1f
 426         slbmte  r6,r5
 427 1:      addi    r8,r8,16
 428         .endr
 429
 430         ld      r4,_SPURR(r1)
 431         mtspr   SPRN_SPURR,r4
 432         ld      r4,_PURR(r1)
 433         mtspr   SPRN_PURR,r4
 434         ld      r4,_DSCR(r1)
 435         mtspr   SPRN_DSCR,r4
 436         ld      r4,_WORT(r1)
 437         mtspr   SPRN_WORT,r4
 438
 439 hypervisor_state_restored:
 440
 441         li      r5,PNV_THREAD_RUNNING
 442         stb     r5,PACA_THREAD_IDLE_STATE(r13)
 443
 444         mtspr   SPRN_SRR1,r16
 445 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 446         li      r0,KVM_HWTHREAD_IN_KERNEL
 447         stb     r0,HSTATE_HWTHREAD_STATE(r13)
 448         /* Order setting hwthread_state vs. testing hwthread_req */
 449         sync
 450         lbz     r0,HSTATE_HWTHREAD_REQ(r13)
 451         cmpwi   r0,0
 452         beq     6f
 453         b       kvm_start_guest
 454 6:
 455 #endif
 456
 457         REST_NVGPRS(r1)
 458         REST_GPR(2, r1)
 459         ld      r3,_CCR(r1)
 460         ld      r4,_MSR(r1)
 461         ld      r5,_NIP(r1)
 462         addi    r1,r1,INT_FRAME_SIZE
 463         mtcr    r3
 464         mfspr   r3,SPRN_SRR1            /* Return SRR1 */
 465         mtspr   SPRN_SRR1,r4
 466         mtspr   SPRN_SRR0,r5
 467         rfid
 468
 469 fastsleep_workaround_at_exit:
 470         li      r3,1
 471         li      r4,0
 472         li      r0,OPAL_CONFIG_CPU_IDLE_STATE
 473         bl      opal_call_realmode
 474         b       timebase_resync
 475
 476 /*
 477  * R3 here contains the value that will be returned to the caller
 478  * of power7_nap.
 479  */
 480 _GLOBAL(power7_wakeup_loss)
 481         ld      r1,PACAR1(r13)
 482 BEGIN_FTR_SECTION
 483         CHECK_HMI_INTERRUPT
 484 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 485         REST_NVGPRS(r1)
 486         REST_GPR(2, r1)
 487         ld      r6,_CCR(r1)
 488         ld      r4,_MSR(r1)
 489         ld      r5,_NIP(r1)
 490         addi    r1,r1,INT_FRAME_SIZE
 491         mtcr    r6
 492         mtspr   SPRN_SRR1,r4
 493         mtspr   SPRN_SRR0,r5
 494         rfid
 495
 496 /*
 497  * R3 here contains the value that will be returned to the caller
 498  * of power7_nap.
 499  */
 500 _GLOBAL(power7_wakeup_noloss)
 501         lbz     r0,PACA_NAPSTATELOST(r13)
 502         cmpwi   r0,0
 503         bne     power7_wakeup_loss
 504 BEGIN_FTR_SECTION
 505         CHECK_HMI_INTERRUPT
 506 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 507         ld      r1,PACAR1(r13)
 508         ld      r6,_CCR(r1)
 509         ld      r4,_MSR(r1)
 510         ld      r5,_NIP(r1)
 511         addi    r1,r1,INT_FRAME_SIZE
 512         mtcr    r6
 513         mtspr   SPRN_SRR1,r4
 514         mtspr   SPRN_SRR0,r5
 515         rfid