arch/powerpc/kernel/misc_32.S

   1 /*
   2  * This file contains miscellaneous low-level functions.
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
   6  * and Paul Mackerras.
   7  *
   8  * kexec bits:
   9  * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
  10  * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version
  15  * 2 of the License, or (at your option) any later version.
  16  *
  17  */
  18
  19 #include <linux/sys.h>
  20 #include <asm/unistd.h>
  21 #include <asm/errno.h>
  22 #include <asm/reg.h>
  23 #include <asm/page.h>
  24 #include <asm/cache.h>
  25 #include <asm/cputable.h>
  26 #include <asm/mmu.h>
  27 #include <asm/ppc_asm.h>
  28 #include <asm/thread_info.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/processor.h>
  31 #include <asm/kexec.h>
  32 #include <asm/bug.h>
  33 #include <asm/ptrace.h>
  34
  35         .text
  36
  37 _GLOBAL(call_do_softirq)
  38         mflr    r0
  39         stw     r0,4(r1)
  40         stwu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
  41         mr      r1,r3
  42         bl      __do_softirq
  43         lwz     r1,0(r1)
  44         lwz     r0,4(r1)
  45         mtlr    r0
  46         blr
  47
  48 _GLOBAL(call_handle_irq)
  49         mflr    r0
  50         stw     r0,4(r1)
  51         mtctr   r6
  52         stwu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
  53         mr      r1,r5
  54         bctrl
  55         lwz     r1,0(r1)
  56         lwz     r0,4(r1)
  57         mtlr    r0
  58         blr
  59
  60 /*
  61  * This returns the high 64 bits of the product of two 64-bit numbers.
  62  */
  63 _GLOBAL(mulhdu)
  64         cmpwi   r6,0
  65         cmpwi   cr1,r3,0
  66         mr      r10,r4
  67         mulhwu  r4,r4,r5
  68         beq     1f
  69         mulhwu  r0,r10,r6
  70         mullw   r7,r10,r5
  71         addc    r7,r0,r7
  72         addze   r4,r4
  73 1:      beqlr   cr1             /* all done if high part of A is 0 */
  74         mr      r10,r3
  75         mullw   r9,r3,r5
  76         mulhwu  r3,r3,r5
  77         beq     2f
  78         mullw   r0,r10,r6
  79         mulhwu  r8,r10,r6
  80         addc    r7,r0,r7
  81         adde    r4,r4,r8
  82         addze   r3,r3
  83 2:      addc    r4,r4,r9
  84         addze   r3,r3
  85         blr
  86
  87 /*
  88  * sub_reloc_offset(x) returns x - reloc_offset().
  89  */
  90 _GLOBAL(sub_reloc_offset)
  91         mflr    r0
  92         bl      1f
  93 1:      mflr    r5
  94         lis     r4,1b@ha
  95         addi    r4,r4,1b@l
  96         subf    r5,r4,r5
  97         subf    r3,r5,r3
  98         mtlr    r0
  99         blr
 100
 101 /*
 102  * reloc_got2 runs through the .got2 section adding an offset
 103  * to each entry.
 104  */
 105 _GLOBAL(reloc_got2)
 106         mflr    r11
 107         lis     r7,__got2_start@ha
 108         addi    r7,r7,__got2_start@l
 109         lis     r8,__got2_end@ha
 110         addi    r8,r8,__got2_end@l
 111         subf    r8,r7,r8
 112         srwi.   r8,r8,2
 113         beqlr
 114         mtctr   r8
 115         bl      1f
 116 1:      mflr    r0
 117         lis     r4,1b@ha
 118         addi    r4,r4,1b@l
 119         subf    r0,r4,r0
 120         add     r7,r0,r7
 121 2:      lwz     r0,0(r7)
 122         add     r0,r0,r3
 123         stw     r0,0(r7)
 124         addi    r7,r7,4
 125         bdnz    2b
 126         mtlr    r11
 127         blr
 128
 129 /*
 130  * call_setup_cpu - call the setup_cpu function for this cpu
 131  * r3 = data offset, r24 = cpu number
 132  *
 133  * Setup function is called with:
 134  *   r3 = data offset
 135  *   r4 = ptr to CPU spec (relocated)
 136  */
 137 _GLOBAL(call_setup_cpu)
 138         addis   r4,r3,cur_cpu_spec@ha
 139         addi    r4,r4,cur_cpu_spec@l
 140         lwz     r4,0(r4)
 141         add     r4,r4,r3
 142         lwz     r5,CPU_SPEC_SETUP(r4)
 143         cmpwi   0,r5,0
 144         add     r5,r5,r3
 145         beqlr
 146         mtctr   r5
 147         bctr
 148
 149 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
 150
 151 /* This gets called by via-pmu.c to switch the PLL selection
 152  * on 750fx CPU. This function should really be moved to some
 153  * other place (as most of the cpufreq code in via-pmu
 154  */
 155 _GLOBAL(low_choose_750fx_pll)
 156         /* Clear MSR:EE */
 157         mfmsr   r7
 158         rlwinm  r0,r7,0,17,15
 159         mtmsr   r0
 160
 161         /* If switching to PLL1, disable HID0:BTIC */
 162         cmplwi  cr0,r3,0
 163         beq     1f
 164         mfspr   r5,SPRN_HID0
 165         rlwinm  r5,r5,0,27,25
 166         sync
 167         mtspr   SPRN_HID0,r5
 168         isync
 169         sync
 170
 171 1:
 172         /* Calc new HID1 value */
 173         mfspr   r4,SPRN_HID1    /* Build a HID1:PS bit from parameter */
 174         rlwinm  r5,r3,16,15,15  /* Clear out HID1:PS from value read */
 175         rlwinm  r4,r4,0,16,14   /* Could have I used rlwimi here ? */
 176         or      r4,r4,r5
 177         mtspr   SPRN_HID1,r4
 178
 179         /* Store new HID1 image */
 180         rlwinm  r6,r1,0,0,(31-THREAD_SHIFT)
 181         lwz     r6,TI_CPU(r6)
 182         slwi    r6,r6,2
 183         addis   r6,r6,nap_save_hid1@ha
 184         stw     r4,nap_save_hid1@l(r6)
 185
 186         /* If switching to PLL0, enable HID0:BTIC */
 187         cmplwi  cr0,r3,0
 188         bne     1f
 189         mfspr   r5,SPRN_HID0
 190         ori     r5,r5,HID0_BTIC
 191         sync
 192         mtspr   SPRN_HID0,r5
 193         isync
 194         sync
 195
 196 1:
 197         /* Return */
 198         mtmsr   r7
 199         blr
 200
 201 _GLOBAL(low_choose_7447a_dfs)
 202         /* Clear MSR:EE */
 203         mfmsr   r7
 204         rlwinm  r0,r7,0,17,15
 205         mtmsr   r0
 206
 207         /* Calc new HID1 value */
 208         mfspr   r4,SPRN_HID1
 209         insrwi  r4,r3,1,9       /* insert parameter into bit 9 */
 210         sync
 211         mtspr   SPRN_HID1,r4
 212         sync
 213         isync
 214
 215         /* Return */
 216         mtmsr   r7
 217         blr
 218
 219 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
 220
 221 /*
 222  * complement mask on the msr then "or" some values on.
 223  *     _nmask_and_or_msr(nmask, value_to_or)
 224  */
 225 _GLOBAL(_nmask_and_or_msr)
 226         mfmsr   r0              /* Get current msr */
 227         andc    r0,r0,r3        /* And off the bits set in r3 (first parm) */
 228         or      r0,r0,r4        /* Or on the bits in r4 (second parm) */
 229         SYNC                    /* Some chip revs have problems here... */
 230         mtmsr   r0              /* Update machine state */
 231         isync
 232         blr                     /* Done */
 233
 234 #ifdef CONFIG_40x
 235
 236 /*
 237  * Do an IO access in real mode
 238  */
 239 _GLOBAL(real_readb)
 240         mfmsr   r7
 241         ori     r0,r7,MSR_DR
 242         xori    r0,r0,MSR_DR
 243         sync
 244         mtmsr   r0
 245         sync
 246         isync
 247         lbz     r3,0(r3)
 248         sync
 249         mtmsr   r7
 250         sync
 251         isync
 252         blr
 253
 254         /*
 255  * Do an IO access in real mode
 256  */
 257 _GLOBAL(real_writeb)
 258         mfmsr   r7
 259         ori     r0,r7,MSR_DR
 260         xori    r0,r0,MSR_DR
 261         sync
 262         mtmsr   r0
 263         sync
 264         isync
 265         stb     r3,0(r4)
 266         sync
 267         mtmsr   r7
 268         sync
 269         isync
 270         blr
 271
 272 #endif /* CONFIG_40x */
 273
 274
 275 /*
 276  * Flush instruction cache.
 277  * This is a no-op on the 601.
 278  */
 279 _GLOBAL(flush_instruction_cache)
 280 #if defined(CONFIG_8xx)
 281         isync
 282         lis     r5, IDC_INVALL@h
 283         mtspr   SPRN_IC_CST, r5
 284 #elif defined(CONFIG_4xx)
 285 #ifdef CONFIG_403GCX
 286         li      r3, 512
 287         mtctr   r3
 288         lis     r4, KERNELBASE@h
 289 1:      iccci   0, r4
 290         addi    r4, r4, 16
 291         bdnz    1b
 292 #else
 293         lis     r3, KERNELBASE@h
 294         iccci   0,r3
 295 #endif
 296 #elif CONFIG_FSL_BOOKE
 297 BEGIN_FTR_SECTION
 298         mfspr   r3,SPRN_L1CSR0
 299         ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
 300         /* msync; isync recommended here */
 301         mtspr   SPRN_L1CSR0,r3
 302         isync
 303         blr
 304 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
 305         mfspr   r3,SPRN_L1CSR1
 306         ori     r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
 307         mtspr   SPRN_L1CSR1,r3
 308 #else
 309         mfspr   r3,SPRN_PVR
 310         rlwinm  r3,r3,16,16,31
 311         cmpwi   0,r3,1
 312         beqlr                   /* for 601, do nothing */
 313         /* 603/604 processor - use invalidate-all bit in HID0 */
 314         mfspr   r3,SPRN_HID0
 315         ori     r3,r3,HID0_ICFI
 316         mtspr   SPRN_HID0,r3
 317 #endif /* CONFIG_8xx/4xx */
 318         isync
 319         blr
 320
 321 /*
 322  * Write any modified data cache blocks out to memory
 323  * and invalidate the corresponding instruction cache blocks.
 324  * This is a no-op on the 601.
 325  *
 326  * flush_icache_range(unsigned long start, unsigned long stop)
 327  */
 328 _KPROBE(__flush_icache_range)
 329 BEGIN_FTR_SECTION
 330         blr                             /* for 601, do nothing */
 331 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 332         li      r5,L1_CACHE_BYTES-1
 333         andc    r3,r3,r5
 334         subf    r4,r3,r4
 335         add     r4,r4,r5
 336         srwi.   r4,r4,L1_CACHE_SHIFT
 337         beqlr
 338         mtctr   r4
 339         mr      r6,r3
 340 1:      dcbst   0,r3
 341         addi    r3,r3,L1_CACHE_BYTES
 342         bdnz    1b
 343         sync                            /* wait for dcbst's to get to ram */
 344 #ifndef CONFIG_44x
 345         mtctr   r4
 346 2:      icbi    0,r6
 347         addi    r6,r6,L1_CACHE_BYTES
 348         bdnz    2b
 349 #else
 350         /* Flash invalidate on 44x because we are passed kmapped addresses and
 351            this doesn't work for userspace pages due to the virtually tagged
 352            icache.  Sigh. */
 353         iccci   0, r0
 354 #endif
 355         sync                            /* additional sync needed on g4 */
 356         isync
 357         blr
 358 /*
 359  * Write any modified data cache blocks out to memory.
 360  * Does not invalidate the corresponding cache lines (especially for
 361  * any corresponding instruction cache).
 362  *
 363  * clean_dcache_range(unsigned long start, unsigned long stop)
 364  */
 365 _GLOBAL(clean_dcache_range)
 366         li      r5,L1_CACHE_BYTES-1
 367         andc    r3,r3,r5
 368         subf    r4,r3,r4
 369         add     r4,r4,r5
 370         srwi.   r4,r4,L1_CACHE_SHIFT
 371         beqlr
 372         mtctr   r4
 373
 374 1:      dcbst   0,r3
 375         addi    r3,r3,L1_CACHE_BYTES
 376         bdnz    1b
 377         sync                            /* wait for dcbst's to get to ram */
 378         blr
 379
 380 /*
 381  * Write any modified data cache blocks out to memory and invalidate them.
 382  * Does not invalidate the corresponding instruction cache blocks.
 383  *
 384  * flush_dcache_range(unsigned long start, unsigned long stop)
 385  */
 386 _GLOBAL(flush_dcache_range)
 387         li      r5,L1_CACHE_BYTES-1
 388         andc    r3,r3,r5
 389         subf    r4,r3,r4
 390         add     r4,r4,r5
 391         srwi.   r4,r4,L1_CACHE_SHIFT
 392         beqlr
 393         mtctr   r4
 394
 395 1:      dcbf    0,r3
 396         addi    r3,r3,L1_CACHE_BYTES
 397         bdnz    1b
 398         sync                            /* wait for dcbst's to get to ram */
 399         blr
 400
 401 /*
 402  * Like above, but invalidate the D-cache.  This is used by the 8xx
 403  * to invalidate the cache so the PPC core doesn't get stale data
 404  * from the CPM (no cache snooping here :-).
 405  *
 406  * invalidate_dcache_range(unsigned long start, unsigned long stop)
 407  */
 408 _GLOBAL(invalidate_dcache_range)
 409         li      r5,L1_CACHE_BYTES-1
 410         andc    r3,r3,r5
 411         subf    r4,r3,r4
 412         add     r4,r4,r5
 413         srwi.   r4,r4,L1_CACHE_SHIFT
 414         beqlr
 415         mtctr   r4
 416
 417 1:      dcbi    0,r3
 418         addi    r3,r3,L1_CACHE_BYTES
 419         bdnz    1b
 420         sync                            /* wait for dcbi's to get to ram */
 421         blr
 422
 423 /*
 424  * Flush a particular page from the data cache to RAM.
 425  * Note: this is necessary because the instruction cache does *not*
 426  * snoop from the data cache.
 427  * This is a no-op on the 601 which has a unified cache.
 428  *
 429  *      void __flush_dcache_icache(void *page)
 430  */
 431 _GLOBAL(__flush_dcache_icache)
 432 BEGIN_FTR_SECTION
 433         blr
 434 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 435         rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
 436         li      r4,PAGE_SIZE/L1_CACHE_BYTES     /* Number of lines in a page */
 437         mtctr   r4
 438         mr      r6,r3
 439 0:      dcbst   0,r3                            /* Write line to ram */
 440         addi    r3,r3,L1_CACHE_BYTES
 441         bdnz    0b
 442         sync
 443 #ifdef CONFIG_44x
 444         /* We don't flush the icache on 44x. Those have a virtual icache
 445          * and we don't have access to the virtual address here (it's
 446          * not the page vaddr but where it's mapped in user space). The
 447          * flushing of the icache on these is handled elsewhere, when
 448          * a change in the address space occurs, before returning to
 449          * user space
 450          */
 451 BEGIN_MMU_FTR_SECTION
 452         blr
 453 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
 454 #endif /* CONFIG_44x */
 455         mtctr   r4
 456 1:      icbi    0,r6
 457         addi    r6,r6,L1_CACHE_BYTES
 458         bdnz    1b
 459         sync
 460         isync
 461         blr
 462
 463 #ifndef CONFIG_BOOKE
 464 /*
 465  * Flush a particular page from the data cache to RAM, identified
 466  * by its physical address.  We turn off the MMU so we can just use
 467  * the physical address (this may be a highmem page without a kernel
 468  * mapping).
 469  *
 470  *      void __flush_dcache_icache_phys(unsigned long physaddr)
 471  */
 472 _GLOBAL(__flush_dcache_icache_phys)
 473 BEGIN_FTR_SECTION
 474         blr                                     /* for 601, do nothing */
 475 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 476         mfmsr   r10
 477         rlwinm  r0,r10,0,28,26                  /* clear DR */
 478         mtmsr   r0
 479         isync
 480         rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
 481         li      r4,PAGE_SIZE/L1_CACHE_BYTES     /* Number of lines in a page */
 482         mtctr   r4
 483         mr      r6,r3
 484 0:      dcbst   0,r3                            /* Write line to ram */
 485         addi    r3,r3,L1_CACHE_BYTES
 486         bdnz    0b
 487         sync
 488         mtctr   r4
 489 1:      icbi    0,r6
 490         addi    r6,r6,L1_CACHE_BYTES
 491         bdnz    1b
 492         sync
 493         mtmsr   r10                             /* restore DR */
 494         isync
 495         blr
 496 #endif /* CONFIG_BOOKE */
 497
 498 /*
 499  * Clear pages using the dcbz instruction, which doesn't cause any
 500  * memory traffic (except to write out any cache lines which get
 501  * displaced).  This only works on cacheable memory.
 502  *
 503  * void clear_pages(void *page, int order) ;
 504  */
 505 _GLOBAL(clear_pages)
 506         li      r0,PAGE_SIZE/L1_CACHE_BYTES
 507         slw     r0,r0,r4
 508         mtctr   r0
 509 1:      dcbz    0,r3
 510         addi    r3,r3,L1_CACHE_BYTES
 511         bdnz    1b
 512         blr
 513
 514 /*
 515  * Copy a whole page.  We use the dcbz instruction on the destination
 516  * to reduce memory traffic (it eliminates the unnecessary reads of
 517  * the destination into cache).  This requires that the destination
 518  * is cacheable.
 519  */
 520 #define COPY_16_BYTES           \
 521         lwz     r6,4(r4);       \
 522         lwz     r7,8(r4);       \
 523         lwz     r8,12(r4);      \
 524         lwzu    r9,16(r4);      \
 525         stw     r6,4(r3);       \
 526         stw     r7,8(r3);       \
 527         stw     r8,12(r3);      \
 528         stwu    r9,16(r3)
 529
 530 _GLOBAL(copy_page)
 531         addi    r3,r3,-4
 532         addi    r4,r4,-4
 533
 534         li      r5,4
 535
 536 #if MAX_COPY_PREFETCH > 1
 537         li      r0,MAX_COPY_PREFETCH
 538         li      r11,4
 539         mtctr   r0
 540 11:     dcbt    r11,r4
 541         addi    r11,r11,L1_CACHE_BYTES
 542         bdnz    11b
 543 #else /* MAX_COPY_PREFETCH == 1 */
 544         dcbt    r5,r4
 545         li      r11,L1_CACHE_BYTES+4
 546 #endif /* MAX_COPY_PREFETCH */
 547         li      r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
 548         crclr   4*cr0+eq
 549 2:
 550         mtctr   r0
 551 1:
 552         dcbt    r11,r4
 553         dcbz    r5,r3
 554         COPY_16_BYTES
 555 #if L1_CACHE_BYTES >= 32
 556         COPY_16_BYTES
 557 #if L1_CACHE_BYTES >= 64
 558         COPY_16_BYTES
 559         COPY_16_BYTES
 560 #if L1_CACHE_BYTES >= 128
 561         COPY_16_BYTES
 562         COPY_16_BYTES
 563         COPY_16_BYTES
 564         COPY_16_BYTES
 565 #endif
 566 #endif
 567 #endif
 568         bdnz    1b
 569         beqlr
 570         crnot   4*cr0+eq,4*cr0+eq
 571         li      r0,MAX_COPY_PREFETCH
 572         li      r11,4
 573         b       2b
 574
 575 /*
 576  * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
 577  * void atomic_set_mask(atomic_t mask, atomic_t *addr);
 578  */
 579 _GLOBAL(atomic_clear_mask)
 580 10:     lwarx   r5,0,r4
 581         andc    r5,r5,r3
 582         PPC405_ERR77(0,r4)
 583         stwcx.  r5,0,r4
 584         bne-    10b
 585         blr
 586 _GLOBAL(atomic_set_mask)
 587 10:     lwarx   r5,0,r4
 588         or      r5,r5,r3
 589         PPC405_ERR77(0,r4)
 590         stwcx.  r5,0,r4
 591         bne-    10b
 592         blr
 593
 594 /*
 595  * Extended precision shifts.
 596  *
 597  * Updated to be valid for shift counts from 0 to 63 inclusive.
 598  * -- Gabriel
 599  *
 600  * R3/R4 has 64 bit value
 601  * R5    has shift count
 602  * result in R3/R4
 603  *
 604  *  ashrdi3: arithmetic right shift (sign propagation)
 605  *  lshrdi3: logical right shift
 606  *  ashldi3: left shift
 607  */
 608 _GLOBAL(__ashrdi3)
 609         subfic  r6,r5,32
 610         srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
 611         addi    r7,r5,32        # could be xori, or addi with -32
 612         slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
 613         rlwinm  r8,r7,0,32      # t3 = (count < 32) ? 32 : 0
 614         sraw    r7,r3,r7        # t2 = MSW >> (count-32)
 615         or      r4,r4,r6        # LSW |= t1
 616         slw     r7,r7,r8        # t2 = (count < 32) ? 0 : t2
 617         sraw    r3,r3,r5        # MSW = MSW >> count
 618         or      r4,r4,r7        # LSW |= t2
 619         blr
 620
 621 _GLOBAL(__ashldi3)
 622         subfic  r6,r5,32
 623         slw     r3,r3,r5        # MSW = count > 31 ? 0 : MSW << count
 624         addi    r7,r5,32        # could be xori, or addi with -32
 625         srw     r6,r4,r6        # t1 = count > 31 ? 0 : LSW >> (32-count)
 626         slw     r7,r4,r7        # t2 = count < 32 ? 0 : LSW << (count-32)
 627         or      r3,r3,r6        # MSW |= t1
 628         slw     r4,r4,r5        # LSW = LSW << count
 629         or      r3,r3,r7        # MSW |= t2
 630         blr
 631
 632 _GLOBAL(__lshrdi3)
 633         subfic  r6,r5,32
 634         srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
 635         addi    r7,r5,32        # could be xori, or addi with -32
 636         slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
 637         srw     r7,r3,r7        # t2 = count < 32 ? 0 : MSW >> (count-32)
 638         or      r4,r4,r6        # LSW |= t1
 639         srw     r3,r3,r5        # MSW = MSW >> count
 640         or      r4,r4,r7        # LSW |= t2
 641         blr
 642
 643 /*
 644  * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
 645  * Returns 0 if a < b, 1 if a == b, 2 if a > b.
 646  */
 647 _GLOBAL(__ucmpdi2)
 648         cmplw   r3,r5
 649         li      r3,1
 650         bne     1f
 651         cmplw   r4,r6
 652         beqlr
 653 1:      li      r3,0
 654         bltlr
 655         li      r3,2
 656         blr
 657
 658 _GLOBAL(abs)
 659         srawi   r4,r3,31
 660         xor     r3,r3,r4
 661         sub     r3,r3,r4
 662         blr
 663
 664 /*
 665  * Create a kernel thread
 666  *   kernel_thread(fn, arg, flags)
 667  */
 668 _GLOBAL(kernel_thread)
 669         stwu    r1,-16(r1)
 670         stw     r30,8(r1)
 671         stw     r31,12(r1)
 672         mr      r30,r3          /* function */
 673         mr      r31,r4          /* argument */
 674         ori     r3,r5,CLONE_VM  /* flags */
 675         oris    r3,r3,CLONE_UNTRACED>>16
 676         li      r4,0            /* new sp (unused) */
 677         li      r0,__NR_clone
 678         sc
 679         bns+    1f              /* did system call indicate error? */
 680         neg     r3,r3           /* if so, make return code negative */
 681 1:      cmpwi   0,r3,0          /* parent or child? */
 682         bne     2f              /* return if parent */
 683         li      r0,0            /* make top-level stack frame */
 684         stwu    r0,-16(r1)
 685         mtlr    r30             /* fn addr in lr */
 686         mr      r3,r31          /* load arg and call fn */
 687         PPC440EP_ERR42
 688         blrl
 689         li      r0,__NR_exit    /* exit if function returns */
 690         li      r3,0
 691         sc
 692 2:      lwz     r30,8(r1)
 693         lwz     r31,12(r1)
 694         addi    r1,r1,16
 695         blr
 696
 697 /*
 698  * This routine is just here to keep GCC happy - sigh...
 699  */
 700 _GLOBAL(__main)
 701         blr
 702
 703 #ifdef CONFIG_KEXEC
 704         /*
 705          * Must be relocatable PIC code callable as a C function.
 706          */
 707         .globl relocate_new_kernel
 708 relocate_new_kernel:
 709         /* r3 = page_list   */
 710         /* r4 = reboot_code_buffer */
 711         /* r5 = start_address      */
 712
 713 #ifdef CONFIG_FSL_BOOKE
 714
 715         mr      r29, r3
 716         mr      r30, r4
 717         mr      r31, r5
 718
 719 #define ENTRY_MAPPING_KEXEC_SETUP
 720 #include "fsl_booke_entry_mapping.S"
 721 #undef ENTRY_MAPPING_KEXEC_SETUP
 722
 723         mr      r3, r29
 724         mr      r4, r30
 725         mr      r5, r31
 726
 727         li      r0, 0
 728 #else
 729         li      r0, 0
 730
 731         /*
 732          * Set Machine Status Register to a known status,
 733          * switch the MMU off and jump to 1: in a single step.
 734          */
 735
 736         mr      r8, r0
 737         ori     r8, r8, MSR_RI|MSR_ME
 738         mtspr   SPRN_SRR1, r8
 739         addi    r8, r4, 1f - relocate_new_kernel
 740         mtspr   SPRN_SRR0, r8
 741         sync
 742         rfi
 743
 744 1:
 745 #endif
 746         /* from this point address translation is turned off */
 747         /* and interrupts are disabled */
 748
 749         /* set a new stack at the bottom of our page... */
 750         /* (not really needed now) */
 751         addi    r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
 752         stw     r0, 0(r1)
 753
 754         /* Do the copies */
 755         li      r6, 0 /* checksum */
 756         mr      r0, r3
 757         b       1f
 758
 759 0:      /* top, read another word for the indirection page */
 760         lwzu    r0, 4(r3)
 761
 762 1:
 763         /* is it a destination page? (r8) */
 764         rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
 765         beq     2f
 766
 767         rlwinm  r8, r0, 0, 0, 19 /* clear kexec flags, page align */
 768         b       0b
 769
 770 2:      /* is it an indirection page? (r3) */
 771         rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
 772         beq     2f
 773
 774         rlwinm  r3, r0, 0, 0, 19 /* clear kexec flags, page align */
 775         subi    r3, r3, 4
 776         b       0b
 777
 778 2:      /* are we done? */
 779         rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
 780         beq     2f
 781         b       3f
 782
 783 2:      /* is it a source page? (r9) */
 784         rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
 785         beq     0b
 786
 787         rlwinm  r9, r0, 0, 0, 19 /* clear kexec flags, page align */
 788
 789         li      r7, PAGE_SIZE / 4
 790         mtctr   r7
 791         subi    r9, r9, 4
 792         subi    r8, r8, 4
 793 9:
 794         lwzu    r0, 4(r9)  /* do the copy */
 795         xor     r6, r6, r0
 796         stwu    r0, 4(r8)
 797         dcbst   0, r8
 798         sync
 799         icbi    0, r8
 800         bdnz    9b
 801
 802         addi    r9, r9, 4
 803         addi    r8, r8, 4
 804         b       0b
 805
 806 3:
 807
 808         /* To be certain of avoiding problems with self-modifying code
 809          * execute a serializing instruction here.
 810          */
 811         isync
 812         sync
 813
 814         mfspr   r3, SPRN_PIR /* current core we are running on */
 815         mr      r4, r5 /* load physical address of chunk called */
 816
 817         /* jump to the entry point, usually the setup routine */
 818         mtlr    r5
 819         blrl
 820
 821 1:      b       1b
 822
 823 relocate_new_kernel_end:
 824
 825         .globl relocate_new_kernel_size
 826 relocate_new_kernel_size:
 827         .long relocate_new_kernel_end - relocate_new_kernel
 828 #endif