2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
35 #include <asm/ptrace.h>
40 * We store the saved ksp_limit in the unused part
41 * of the STACK_FRAME_OVERHEAD
43 _GLOBAL(call_do_softirq)
46 lwz r10,THREAD+KSP_LIMIT(r2)
47 addi r11,r3,THREAD_INFO_GAP
48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
51 stw r11,THREAD+KSP_LIMIT(r2)
56 stw r10,THREAD+KSP_LIMIT(r2)
61 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
66 lwz r10,THREAD+KSP_LIMIT(r2)
67 addi r11,r4,THREAD_INFO_GAP
68 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
71 stw r11,THREAD+KSP_LIMIT(r2)
76 stw r10,THREAD+KSP_LIMIT(r2)
81 * This returns the high 64 bits of the product of two 64-bit numbers.
93 1: beqlr cr1 /* all done if high part of A is 0 */
107 * sub_reloc_offset(x) returns x - reloc_offset().
109 _GLOBAL(sub_reloc_offset)
121 * reloc_got2 runs through the .got2 section adding an offset
126 lis r7,__got2_start@ha
127 addi r7,r7,__got2_start@l
129 addi r8,r8,__got2_end@l
149 * call_setup_cpu - call the setup_cpu function for this cpu
150 * r3 = data offset, r24 = cpu number
152 * Setup function is called with:
154 * r4 = ptr to CPU spec (relocated)
156 _GLOBAL(call_setup_cpu)
157 addis r4,r3,cur_cpu_spec@ha
158 addi r4,r4,cur_cpu_spec@l
161 lwz r5,CPU_SPEC_SETUP(r4)
168 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
170 /* This gets called by via-pmu.c to switch the PLL selection
171 * on 750fx CPU. This function should really be moved to some
172 * other place (as most of the cpufreq code in via-pmu
174 _GLOBAL(low_choose_750fx_pll)
180 /* If switching to PLL1, disable HID0:BTIC */
191 /* Calc new HID1 value */
192 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
193 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
194 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
198 /* Store new HID1 image */
199 CURRENT_THREAD_INFO(r6, r1)
202 addis r6,r6,nap_save_hid1@ha
203 stw r4,nap_save_hid1@l(r6)
205 /* If switching to PLL0, enable HID0:BTIC */
220 _GLOBAL(low_choose_7447a_dfs)
226 /* Calc new HID1 value */
228 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
238 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
241 * complement mask on the msr then "or" some values on.
242 * _nmask_and_or_msr(nmask, value_to_or)
244 _GLOBAL(_nmask_and_or_msr)
245 mfmsr r0 /* Get current msr */
246 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
247 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
248 SYNC /* Some chip revs have problems here... */
249 mtmsr r0 /* Update machine state */
256 * Do an IO access in real mode
274 * Do an IO access in real mode
291 #endif /* CONFIG_40x */
295 * Flush instruction cache.
296 * This is a no-op on the 601.
298 #ifndef CONFIG_PPC_8xx
299 _GLOBAL(flush_instruction_cache)
300 #if defined(CONFIG_4xx)
312 #elif CONFIG_FSL_BOOKE
315 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
316 /* msync; isync recommended here */
320 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
322 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
326 rlwinm r3,r3,16,16,31
328 beqlr /* for 601, do nothing */
329 /* 603/604 processor - use invalidate-all bit in HID0 */
333 #endif /* CONFIG_4xx */
336 #endif /* CONFIG_PPC_8xx */
339 * Write any modified data cache blocks out to memory
340 * and invalidate the corresponding instruction cache blocks.
341 * This is a no-op on the 601.
343 * flush_icache_range(unsigned long start, unsigned long stop)
345 _KPROBE(flush_icache_range)
348 blr /* for 601, do nothing */
349 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
350 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
352 addi r4,r4,L1_CACHE_BYTES - 1
353 srwi. r4,r4,L1_CACHE_SHIFT
358 addi r3,r3,L1_CACHE_BYTES
360 sync /* wait for dcbst's to get to ram */
364 addi r6,r6,L1_CACHE_BYTES
367 /* Flash invalidate on 44x because we are passed kmapped addresses and
368 this doesn't work for userspace pages due to the virtually tagged
372 sync /* additional sync needed on g4 */
376 * Flush a particular page from the data cache to RAM.
377 * Note: this is necessary because the instruction cache does *not*
378 * snoop from the data cache.
379 * This is a no-op on the 601 which has a unified cache.
381 * void __flush_dcache_icache(void *page)
383 _GLOBAL(__flush_dcache_icache)
387 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
388 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
389 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
392 0: dcbst 0,r3 /* Write line to ram */
393 addi r3,r3,L1_CACHE_BYTES
397 /* We don't flush the icache on 44x. Those have a virtual icache
398 * and we don't have access to the virtual address here (it's
399 * not the page vaddr but where it's mapped in user space). The
400 * flushing of the icache on these is handled elsewhere, when
401 * a change in the address space occurs, before returning to
404 BEGIN_MMU_FTR_SECTION
406 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
407 #endif /* CONFIG_44x */
410 addi r6,r6,L1_CACHE_BYTES
418 * Flush a particular page from the data cache to RAM, identified
419 * by its physical address. We turn off the MMU so we can just use
420 * the physical address (this may be a highmem page without a kernel
423 * void __flush_dcache_icache_phys(unsigned long physaddr)
425 _GLOBAL(__flush_dcache_icache_phys)
428 blr /* for 601, do nothing */
429 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
431 rlwinm r0,r10,0,28,26 /* clear DR */
434 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
435 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
438 0: dcbst 0,r3 /* Write line to ram */
439 addi r3,r3,L1_CACHE_BYTES
444 addi r6,r6,L1_CACHE_BYTES
447 mtmsr r10 /* restore DR */
450 #endif /* CONFIG_BOOKE */
453 * Copy a whole page. We use the dcbz instruction on the destination
454 * to reduce memory traffic (it eliminates the unnecessary reads of
455 * the destination into cache). This requires that the destination
458 #define COPY_16_BYTES \
474 #if MAX_COPY_PREFETCH > 1
475 li r0,MAX_COPY_PREFETCH
479 addi r11,r11,L1_CACHE_BYTES
481 #else /* MAX_COPY_PREFETCH == 1 */
483 li r11,L1_CACHE_BYTES+4
484 #endif /* MAX_COPY_PREFETCH */
485 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
493 #if L1_CACHE_BYTES >= 32
495 #if L1_CACHE_BYTES >= 64
498 #if L1_CACHE_BYTES >= 128
508 crnot 4*cr0+eq,4*cr0+eq
509 li r0,MAX_COPY_PREFETCH
514 * Extended precision shifts.
516 * Updated to be valid for shift counts from 0 to 63 inclusive.
519 * R3/R4 has 64 bit value
523 * ashrdi3: arithmetic right shift (sign propagation)
524 * lshrdi3: logical right shift
525 * ashldi3: left shift
529 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
530 addi r7,r5,32 # could be xori, or addi with -32
531 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
532 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
533 sraw r7,r3,r7 # t2 = MSW >> (count-32)
534 or r4,r4,r6 # LSW |= t1
535 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
536 sraw r3,r3,r5 # MSW = MSW >> count
537 or r4,r4,r7 # LSW |= t2
542 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
543 addi r7,r5,32 # could be xori, or addi with -32
544 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
545 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
546 or r3,r3,r6 # MSW |= t1
547 slw r4,r4,r5 # LSW = LSW << count
548 or r3,r3,r7 # MSW |= t2
553 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
554 addi r7,r5,32 # could be xori, or addi with -32
555 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
556 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
557 or r4,r4,r6 # LSW |= t1
558 srw r3,r3,r5 # MSW = MSW >> count
559 or r4,r4,r7 # LSW |= t2
563 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
564 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
577 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
578 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
596 rlwimi r9,r4,24,16,23
597 rlwimi r10,r3,24,16,23
603 _GLOBAL(start_secondary_resume)
605 CURRENT_THREAD_INFO(r1, r1)
606 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
608 stw r3,0(r1) /* Zero the stack frame pointer */
611 #endif /* CONFIG_SMP */
614 * This routine is just here to keep GCC happy - sigh...
621 * Must be relocatable PIC code callable as a C function.
623 .globl relocate_new_kernel
626 /* r4 = reboot_code_buffer */
627 /* r5 = start_address */
629 #ifdef CONFIG_FSL_BOOKE
635 #define ENTRY_MAPPING_KEXEC_SETUP
636 #include "fsl_booke_entry_mapping.S"
637 #undef ENTRY_MAPPING_KEXEC_SETUP
644 #elif defined(CONFIG_44x)
646 /* Save our parameters */
651 #ifdef CONFIG_PPC_47x
652 /* Check for 47x cores */
655 cmplwi cr0,r3,PVR_476FPE@h
657 cmplwi cr0,r3,PVR_476@h
659 cmplwi cr0,r3,PVR_476_ISS@h
661 #endif /* CONFIG_PPC_47x */
664 * Code for setting up 1:1 mapping for PPC440x for KEXEC
666 * We cannot switch off the MMU on PPC44x.
668 * 1) Invalidate all the mappings except the one we are running from.
669 * 2) Create a tmp mapping for our code in the other address space(TS) and
670 * jump to it. Invalidate the entry we started in.
671 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
672 * 4) Jump to the 1:1 mapping in original TS.
673 * 5) Invalidate the tmp mapping.
675 * - Based on the kexec support code for FSL BookE
680 * Load the PID with kernel PID (0).
681 * Also load our MSR_IS and TID to MMUCR for TLB search.
688 oris r3,r3,PPC44x_MMUCR_STS@h
694 * Invalidate all the TLB entries except the current entry
695 * where we are running from
697 bl 0f /* Find our address */
698 0: mflr r5 /* Make it accessible */
699 tlbsx r23,0,r5 /* Find entry we are in */
700 li r4,0 /* Start at TLB entry 0 */
701 li r3,0 /* Set PAGEID inval value */
702 1: cmpw r23,r4 /* Is this our entry? */
703 beq skip /* If so, skip the inval */
704 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
706 addi r4,r4,1 /* Increment */
707 cmpwi r4,64 /* Are we done? */
708 bne 1b /* If not, repeat */
711 /* Create a temp mapping and jump to it */
712 andi. r6, r23, 1 /* Find the index to use */
713 addi r24, r6, 1 /* r24 will contain 1 or 2 */
715 mfmsr r9 /* get the MSR */
716 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
717 xori r7, r5, 1 /* Use the other address space */
719 /* Read the current mapping entries */
720 tlbre r3, r23, PPC44x_TLB_PAGEID
721 tlbre r4, r23, PPC44x_TLB_XLAT
722 tlbre r5, r23, PPC44x_TLB_ATTRIB
724 /* Save our current XLAT entry */
727 /* Extract the TLB PageSize */
728 li r10, 1 /* r10 will hold PageSize */
729 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
731 /* XXX: As of now we use 256M, 4K pages */
732 cmpwi r11, PPC44x_TLB_256M
734 rotlwi r10, r10, 28 /* r10 = 256M */
737 cmpwi r11, PPC44x_TLB_4K
739 rotlwi r10, r10, 12 /* r10 = 4K */
742 rotlwi r10, r10, 10 /* r10 = 1K */
746 * Write out the tmp 1:1 mapping for this code in other address space
747 * Fixup EPN = RPN , TS=other address space
749 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
751 /* Write out the tmp mapping entries */
752 tlbwe r3, r24, PPC44x_TLB_PAGEID
753 tlbwe r4, r24, PPC44x_TLB_XLAT
754 tlbwe r5, r24, PPC44x_TLB_ATTRIB
756 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
757 not r10, r11 /* Mask for PageNum */
759 /* Switch to other address space in MSR */
760 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
764 addi r8, r8, (2f-1b) /* Find the target offset */
766 /* Jump to the tmp mapping */
772 /* Invalidate the entry we were executing from */
774 tlbwe r3, r23, PPC44x_TLB_PAGEID
776 /* attribute fields. rwx for SUPERVISOR mode */
778 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
780 /* Create 1:1 mapping in 256M pages */
781 xori r7, r7, 1 /* Revert back to Original TS */
783 li r8, 0 /* PageNumber */
784 li r6, 3 /* TLB Index, start at 3 */
787 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
788 mr r4, r3 /* RPN = EPN */
789 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
790 insrwi r3, r7, 1, 23 /* Set TS from r7 */
792 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
793 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
794 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
796 addi r8, r8, 1 /* Increment PN */
797 addi r6, r6, 1 /* Increment TLB Index */
798 cmpwi r8, 8 /* Are we done ? */
802 /* Jump to the new mapping 1:1 */
804 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
808 and r8, r8, r11 /* Get our offset within page */
811 and r5, r25, r10 /* Get our target PageNum */
812 or r8, r8, r5 /* Target jump address */
818 /* Invalidate the tmp entry we used */
820 tlbwe r3, r24, PPC44x_TLB_PAGEID
824 #ifdef CONFIG_PPC_47x
826 /* 1:1 mapping for 47x */
831 * Load the kernel pid (0) to PID and also to MMUCR[TID].
832 * Also set the MSR IS->MMUCR STS
835 mtspr SPRN_PID, r3 /* Set PID */
836 mfmsr r4 /* Get MSR */
837 andi. r4, r4, MSR_IS@l /* TS=1? */
838 beq 1f /* If not, leave STS=0 */
839 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
840 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
843 /* Find the entry we are running from */
847 tlbre r24, r23, 0 /* TLB Word 0 */
848 tlbre r25, r23, 1 /* TLB Word 1 */
849 tlbre r26, r23, 2 /* TLB Word 2 */
853 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
854 * of 4k page size in all 4 ways (0-3 in r3).
855 * This would invalidate the entire UTLB including the one we are
856 * running from. However the shadow TLB entries would help us
857 * to continue the execution, until we flush them (rfi/isync).
859 addis r3, 0, 0x8000 /* specify the way */
860 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
864 /* Align the loop to speed things up. from head_44x.S */
872 addis r3, r3, 0x2000 /* Increment the way */
876 addis r4, r4, 0x100 /* Increment the EPN */
880 /* Create the entries in the other address space */
882 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
883 xori r7, r7, 1 /* r7 = !TS */
885 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
888 * write out the TLB entries for the tmp mapping
889 * Use way '0' so that we could easily invalidate it later.
891 lis r3, 0x8000 /* Way '0' */
897 /* Update the msr to the new TS */
909 * Now we are in the tmp address space.
910 * Create a 1:1 mapping for 0-2GiB in the original TS.
914 li r4, 0 /* TLB Word 0 */
915 li r5, 0 /* TLB Word 1 */
917 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
919 li r8, 0 /* PageIndex */
921 xori r7, r7, 1 /* revert back to original TS */
924 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
925 /* ERPN = 0 as we don't use memory above 2G */
927 mr r4, r5 /* EPN = RPN */
928 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
929 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
931 tlbwe r4, r3, 0 /* Write out the entries */
935 cmpwi r8, 8 /* Have we completed ? */
938 /* make sure we complete the TLB write up */
942 * Prepare to jump to the 1:1 mapping.
943 * 1) Extract page size of the tmp mapping
944 * DSIZ = TLB_Word0[22:27]
945 * 2) Calculate the physical address of the address
948 rlwinm r10, r24, 0, 22, 27
950 cmpwi r10, PPC47x_TLB0_4K
952 li r10, 0x1000 /* r10 = 4k */
956 /* Defaults to 256M */
961 addi r4, r4, (2f-1b) /* virtual address of 2f */
963 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
964 not r10, r11 /* Pagemask = ~(offsetmask) */
966 and r5, r25, r10 /* Physical page */
967 and r6, r4, r11 /* offset within the current page */
969 or r5, r5, r6 /* Physical address for 2f */
971 /* Switch the TS in MSR to the original one */
980 /* Invalidate the tmp mapping */
981 lis r3, 0x8000 /* Way '0' */
983 clrrwi r24, r24, 12 /* Clear the valid bit */
988 /* Make sure we complete the TLB write and flush the shadow TLB */
996 /* Restore the parameters */
1006 * Set Machine Status Register to a known status,
1007 * switch the MMU off and jump to 1: in a single step.
1011 ori r8, r8, MSR_RI|MSR_ME
1013 addi r8, r4, 1f - relocate_new_kernel
1020 /* from this point address translation is turned off */
1021 /* and interrupts are disabled */
1023 /* set a new stack at the bottom of our page... */
1024 /* (not really needed now) */
1025 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1029 li r6, 0 /* checksum */
1033 0: /* top, read another word for the indirection page */
1037 /* is it a destination page? (r8) */
1038 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1041 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1044 2: /* is it an indirection page? (r3) */
1045 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1048 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1052 2: /* are we done? */
1053 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1057 2: /* is it a source page? (r9) */
1058 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1061 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1063 li r7, PAGE_SIZE / 4
1068 lwzu r0, 4(r9) /* do the copy */
1082 /* To be certain of avoiding problems with self-modifying code
1083 * execute a serializing instruction here.
1088 mfspr r3, SPRN_PIR /* current core we are running on */
1089 mr r4, r5 /* load physical address of chunk called */
1091 /* jump to the entry point, usually the setup routine */
1097 relocate_new_kernel_end:
1099 .globl relocate_new_kernel_size
1100 relocate_new_kernel_size:
1101 .long relocate_new_kernel_end - relocate_new_kernel
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