2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
19 #include <linux/sys.h>
20 #include <asm/unistd.h>
21 #include <asm/errno.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/processor.h>
31 #include <asm/kexec.h>
35 #ifdef CONFIG_IRQSTACKS
36 _GLOBAL(call_do_softirq)
39 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
47 _GLOBAL(call_handle_irq)
51 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
58 #endif /* CONFIG_IRQSTACKS */
61 * This returns the high 64 bits of the product of two 64-bit numbers.
73 1: beqlr cr1 /* all done if high part of A is 0 */
88 * sub_reloc_offset(x) returns x - reloc_offset().
90 _GLOBAL(sub_reloc_offset)
102 * reloc_got2 runs through the .got2 section adding an offset
107 lis r7,__got2_start@ha
108 addi r7,r7,__got2_start@l
110 addi r8,r8,__got2_end@l
130 * call_setup_cpu - call the setup_cpu function for this cpu
131 * r3 = data offset, r24 = cpu number
133 * Setup function is called with:
135 * r4 = ptr to CPU spec (relocated)
137 _GLOBAL(call_setup_cpu)
138 addis r4,r3,cur_cpu_spec@ha
139 addi r4,r4,cur_cpu_spec@l
142 lwz r5,CPU_SPEC_SETUP(r4)
149 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
151 /* This gets called by via-pmu.c to switch the PLL selection
152 * on 750fx CPU. This function should really be moved to some
153 * other place (as most of the cpufreq code in via-pmu
155 _GLOBAL(low_choose_750fx_pll)
161 /* If switching to PLL1, disable HID0:BTIC */
172 /* Calc new HID1 value */
173 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
174 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
175 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
179 /* Store new HID1 image */
180 rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
183 addis r6,r6,nap_save_hid1@ha
184 stw r4,nap_save_hid1@l(r6)
186 /* If switching to PLL0, enable HID0:BTIC */
201 _GLOBAL(low_choose_7447a_dfs)
207 /* Calc new HID1 value */
209 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
219 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
222 * complement mask on the msr then "or" some values on.
223 * _nmask_and_or_msr(nmask, value_to_or)
225 _GLOBAL(_nmask_and_or_msr)
226 mfmsr r0 /* Get current msr */
227 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
228 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
229 SYNC /* Some chip revs have problems here... */
230 mtmsr r0 /* Update machine state */
237 * Do an IO access in real mode
255 * Do an IO access in real mode
272 #endif /* CONFIG_40x */
277 #ifndef CONFIG_FSL_BOOKE
282 #if defined(CONFIG_40x)
283 sync /* Flush to memory before changing mapping */
285 isync /* Flush shadow TLB */
286 #elif defined(CONFIG_44x)
290 /* Load high watermark */
291 lis r4,tlb_44x_hwater@ha
292 lwz r5,tlb_44x_hwater@l(r4)
294 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
300 #elif defined(CONFIG_FSL_BOOKE)
301 /* Invalidate all entries in TLB0 */
304 /* Invalidate all entries in TLB1 */
310 #endif /* CONFIG_SMP */
311 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
312 #if defined(CONFIG_SMP)
313 rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
318 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
319 rlwinm r0,r0,0,28,26 /* clear DR */
323 lis r9,mmu_hash_lock@h
324 ori r9,r9,mmu_hash_lock@l
336 stw r0,0(r9) /* clear mmu_hash_lock */
340 #else /* CONFIG_SMP */
344 #endif /* CONFIG_SMP */
345 #endif /* ! defined(CONFIG_40x) */
349 * Flush MMU TLB for a particular address
351 #ifndef CONFIG_FSL_BOOKE
355 #if defined(CONFIG_40x)
356 /* We run the search with interrupts disabled because we have to change
357 * the PID and I don't want to preempt when that happens.
368 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
369 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
371 tlbwe r3, r3, TLB_TAG
375 #elif defined(CONFIG_44x)
377 rlwimi r5,r4,0,24,31 /* Set TID */
379 /* We have to run the search with interrupts disabled, even critical
380 * and debug interrupts (in fact the only critical exceptions we have
381 * are debug and machine check). Otherwise an interrupt which causes
382 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
384 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
385 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
393 /* There are only 64 TLB entries, so r3 < 64,
394 * which means bit 22, is clear. Since 22 is
395 * the V bit in the TLB_PAGEID, loading this
396 * value will invalidate the TLB entry.
398 tlbwe r3, r3, PPC44x_TLB_PAGEID
401 #elif defined(CONFIG_FSL_BOOKE)
402 rlwinm r4, r3, 0, 0, 19
403 ori r5, r4, 0x08 /* TLBSEL = 1 */
407 #if defined(CONFIG_SMP)
409 #endif /* CONFIG_SMP */
410 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
411 #if defined(CONFIG_SMP)
412 rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
417 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
418 rlwinm r0,r0,0,28,26 /* clear DR */
422 lis r9,mmu_hash_lock@h
423 ori r9,r9,mmu_hash_lock@l
435 stw r0,0(r9) /* clear mmu_hash_lock */
439 #else /* CONFIG_SMP */
442 #endif /* CONFIG_SMP */
443 #endif /* ! CONFIG_40x */
446 #if defined(CONFIG_FSL_BOOKE)
448 * Flush MMU TLB, but only on the local processor (no broadcast)
451 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
452 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
453 li r3,(MMUCSR0_TLBFI)@l
454 mtspr SPRN_MMUCSR0, r3
456 mfspr r3,SPRN_MMUCSR0
457 andi. r3,r3,MMUCSR0_TLBFI@l
462 * Flush MMU TLB for a particular process id, but only on the local processor
466 /* we currently do an invalidate all since we don't have per pid invalidate */
467 li r3,(MMUCSR0_TLBFI)@l
468 mtspr SPRN_MMUCSR0, r3
470 mfspr r3,SPRN_MMUCSR0
471 andi. r3,r3,MMUCSR0_TLBFI@l
476 * Flush MMU TLB for a particular address, but only on the local processor
481 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
483 mfspr r4,SPRN_MAS1 /* check valid */
484 andis. r3,r4,MAS1_VALID@h
490 #endif /* CONFIG_FSL_BOOKE */
494 * Flush instruction cache.
495 * This is a no-op on the 601.
497 _GLOBAL(flush_instruction_cache)
498 #if defined(CONFIG_8xx)
501 mtspr SPRN_IC_CST, r5
502 #elif defined(CONFIG_4xx)
514 #elif CONFIG_FSL_BOOKE
517 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
518 /* msync; isync recommended here */
522 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
524 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
528 rlwinm r3,r3,16,16,31
530 beqlr /* for 601, do nothing */
531 /* 603/604 processor - use invalidate-all bit in HID0 */
535 #endif /* CONFIG_8xx/4xx */
540 * Write any modified data cache blocks out to memory
541 * and invalidate the corresponding instruction cache blocks.
542 * This is a no-op on the 601.
544 * flush_icache_range(unsigned long start, unsigned long stop)
546 _KPROBE(__flush_icache_range)
548 blr /* for 601, do nothing */
549 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
550 li r5,L1_CACHE_BYTES-1
554 srwi. r4,r4,L1_CACHE_SHIFT
559 addi r3,r3,L1_CACHE_BYTES
561 sync /* wait for dcbst's to get to ram */
564 addi r6,r6,L1_CACHE_BYTES
566 sync /* additional sync needed on g4 */
570 * Write any modified data cache blocks out to memory.
571 * Does not invalidate the corresponding cache lines (especially for
572 * any corresponding instruction cache).
574 * clean_dcache_range(unsigned long start, unsigned long stop)
576 _GLOBAL(clean_dcache_range)
577 li r5,L1_CACHE_BYTES-1
581 srwi. r4,r4,L1_CACHE_SHIFT
586 addi r3,r3,L1_CACHE_BYTES
588 sync /* wait for dcbst's to get to ram */
592 * Write any modified data cache blocks out to memory and invalidate them.
593 * Does not invalidate the corresponding instruction cache blocks.
595 * flush_dcache_range(unsigned long start, unsigned long stop)
597 _GLOBAL(flush_dcache_range)
598 li r5,L1_CACHE_BYTES-1
602 srwi. r4,r4,L1_CACHE_SHIFT
607 addi r3,r3,L1_CACHE_BYTES
609 sync /* wait for dcbst's to get to ram */
613 * Like above, but invalidate the D-cache. This is used by the 8xx
614 * to invalidate the cache so the PPC core doesn't get stale data
615 * from the CPM (no cache snooping here :-).
617 * invalidate_dcache_range(unsigned long start, unsigned long stop)
619 _GLOBAL(invalidate_dcache_range)
620 li r5,L1_CACHE_BYTES-1
624 srwi. r4,r4,L1_CACHE_SHIFT
629 addi r3,r3,L1_CACHE_BYTES
631 sync /* wait for dcbi's to get to ram */
635 * Flush a particular page from the data cache to RAM.
636 * Note: this is necessary because the instruction cache does *not*
637 * snoop from the data cache.
638 * This is a no-op on the 601 which has a unified cache.
640 * void __flush_dcache_icache(void *page)
642 _GLOBAL(__flush_dcache_icache)
645 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
646 rlwinm r3,r3,0,0,19 /* Get page base address */
647 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
650 0: dcbst 0,r3 /* Write line to ram */
651 addi r3,r3,L1_CACHE_BYTES
655 /* We don't flush the icache on 44x. Those have a virtual icache
656 * and we don't have access to the virtual address here (it's
657 * not the page vaddr but where it's mapped in user space). The
658 * flushing of the icache on these is handled elsewhere, when
659 * a change in the address space occurs, before returning to
664 addi r6,r6,L1_CACHE_BYTES
668 #endif /* CONFIG_44x */
672 * Flush a particular page from the data cache to RAM, identified
673 * by its physical address. We turn off the MMU so we can just use
674 * the physical address (this may be a highmem page without a kernel
677 * void __flush_dcache_icache_phys(unsigned long physaddr)
679 _GLOBAL(__flush_dcache_icache_phys)
681 blr /* for 601, do nothing */
682 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
684 rlwinm r0,r10,0,28,26 /* clear DR */
687 rlwinm r3,r3,0,0,19 /* Get page base address */
688 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
691 0: dcbst 0,r3 /* Write line to ram */
692 addi r3,r3,L1_CACHE_BYTES
697 addi r6,r6,L1_CACHE_BYTES
700 mtmsr r10 /* restore DR */
705 * Clear pages using the dcbz instruction, which doesn't cause any
706 * memory traffic (except to write out any cache lines which get
707 * displaced). This only works on cacheable memory.
709 * void clear_pages(void *page, int order) ;
712 li r0,4096/L1_CACHE_BYTES
724 addi r3,r3,L1_CACHE_BYTES
729 * Copy a whole page. We use the dcbz instruction on the destination
730 * to reduce memory traffic (it eliminates the unnecessary reads of
731 * the destination into cache). This requires that the destination
734 #define COPY_16_BYTES \
749 /* don't use prefetch on 8xx */
750 li r0,4096/L1_CACHE_BYTES
756 #else /* not 8xx, we can prefetch */
759 #if MAX_COPY_PREFETCH > 1
760 li r0,MAX_COPY_PREFETCH
764 addi r11,r11,L1_CACHE_BYTES
766 #else /* MAX_COPY_PREFETCH == 1 */
768 li r11,L1_CACHE_BYTES+4
769 #endif /* MAX_COPY_PREFETCH */
770 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
778 #if L1_CACHE_BYTES >= 32
780 #if L1_CACHE_BYTES >= 64
783 #if L1_CACHE_BYTES >= 128
793 crnot 4*cr0+eq,4*cr0+eq
794 li r0,MAX_COPY_PREFETCH
797 #endif /* CONFIG_8xx */
800 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
801 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
803 _GLOBAL(atomic_clear_mask)
810 _GLOBAL(atomic_set_mask)
819 * Extended precision shifts.
821 * Updated to be valid for shift counts from 0 to 63 inclusive.
824 * R3/R4 has 64 bit value
828 * ashrdi3: arithmetic right shift (sign propagation)
829 * lshrdi3: logical right shift
830 * ashldi3: left shift
834 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
835 addi r7,r5,32 # could be xori, or addi with -32
836 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
837 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
838 sraw r7,r3,r7 # t2 = MSW >> (count-32)
839 or r4,r4,r6 # LSW |= t1
840 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
841 sraw r3,r3,r5 # MSW = MSW >> count
842 or r4,r4,r7 # LSW |= t2
847 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
848 addi r7,r5,32 # could be xori, or addi with -32
849 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
850 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
851 or r3,r3,r6 # MSW |= t1
852 slw r4,r4,r5 # LSW = LSW << count
853 or r3,r3,r7 # MSW |= t2
858 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
859 addi r7,r5,32 # could be xori, or addi with -32
860 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
861 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
862 or r4,r4,r6 # LSW |= t1
863 srw r3,r3,r5 # MSW = MSW >> count
864 or r4,r4,r7 # LSW |= t2
868 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
869 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
889 * Create a kernel thread
890 * kernel_thread(fn, arg, flags)
892 _GLOBAL(kernel_thread)
896 mr r30,r3 /* function */
897 mr r31,r4 /* argument */
898 ori r3,r5,CLONE_VM /* flags */
899 oris r3,r3,CLONE_UNTRACED>>16
900 li r4,0 /* new sp (unused) */
903 bns+ 1f /* did system call indicate error? */
904 neg r3,r3 /* if so, make return code negative */
905 1: cmpwi 0,r3,0 /* parent or child? */
906 bne 2f /* return if parent */
907 li r0,0 /* make top-level stack frame */
909 mtlr r30 /* fn addr in lr */
910 mr r3,r31 /* load arg and call fn */
913 li r0,__NR_exit /* exit if function returns */
922 * This routine is just here to keep GCC happy - sigh...
929 * Must be relocatable PIC code callable as a C function.
931 .globl relocate_new_kernel
934 /* r4 = reboot_code_buffer */
935 /* r5 = start_address */
940 * Set Machine Status Register to a known status,
941 * switch the MMU off and jump to 1: in a single step.
945 ori r8, r8, MSR_RI|MSR_ME
947 addi r8, r4, 1f - relocate_new_kernel
953 /* from this point address translation is turned off */
954 /* and interrupts are disabled */
956 /* set a new stack at the bottom of our page... */
957 /* (not really needed now) */
958 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
962 li r6, 0 /* checksum */
966 0: /* top, read another word for the indirection page */
970 /* is it a destination page? (r8) */
971 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
974 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
977 2: /* is it an indirection page? (r3) */
978 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
981 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
985 2: /* are we done? */
986 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
990 2: /* is it a source page? (r9) */
991 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
994 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1001 lwzu r0, 4(r9) /* do the copy */
1015 /* To be certain of avoiding problems with self-modifying code
1016 * execute a serializing instruction here.
1021 /* jump to the entry point, usually the setup routine */
1027 relocate_new_kernel_end:
1029 .globl relocate_new_kernel_size
1030 relocate_new_kernel_size:
1031 .long relocate_new_kernel_end - relocate_new_kernel
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