2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
35 #include <asm/ptrace.h>
40 * We store the saved ksp_limit in the unused part
41 * of the STACK_FRAME_OVERHEAD
43 _GLOBAL(call_do_softirq)
46 lwz r10,THREAD+KSP_LIMIT(r2)
47 addi r11,r3,THREAD_INFO_GAP
48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
51 stw r11,THREAD+KSP_LIMIT(r2)
56 stw r10,THREAD+KSP_LIMIT(r2)
61 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
66 lwz r10,THREAD+KSP_LIMIT(r2)
67 addi r11,r4,THREAD_INFO_GAP
68 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
71 stw r11,THREAD+KSP_LIMIT(r2)
76 stw r10,THREAD+KSP_LIMIT(r2)
81 * This returns the high 64 bits of the product of two 64-bit numbers.
93 1: beqlr cr1 /* all done if high part of A is 0 */
107 * reloc_got2 runs through the .got2 section adding an offset
112 lis r7,__got2_start@ha
113 addi r7,r7,__got2_start@l
115 addi r8,r8,__got2_end@l
135 * call_setup_cpu - call the setup_cpu function for this cpu
136 * r3 = data offset, r24 = cpu number
138 * Setup function is called with:
140 * r4 = ptr to CPU spec (relocated)
142 _GLOBAL(call_setup_cpu)
143 addis r4,r3,cur_cpu_spec@ha
144 addi r4,r4,cur_cpu_spec@l
147 lwz r5,CPU_SPEC_SETUP(r4)
154 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
156 /* This gets called by via-pmu.c to switch the PLL selection
157 * on 750fx CPU. This function should really be moved to some
158 * other place (as most of the cpufreq code in via-pmu
160 _GLOBAL(low_choose_750fx_pll)
166 /* If switching to PLL1, disable HID0:BTIC */
177 /* Calc new HID1 value */
178 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
179 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
180 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
184 /* Store new HID1 image */
185 CURRENT_THREAD_INFO(r6, r1)
188 addis r6,r6,nap_save_hid1@ha
189 stw r4,nap_save_hid1@l(r6)
191 /* If switching to PLL0, enable HID0:BTIC */
206 _GLOBAL(low_choose_7447a_dfs)
212 /* Calc new HID1 value */
214 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
224 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
227 * complement mask on the msr then "or" some values on.
228 * _nmask_and_or_msr(nmask, value_to_or)
230 _GLOBAL(_nmask_and_or_msr)
231 mfmsr r0 /* Get current msr */
232 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
233 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
234 SYNC /* Some chip revs have problems here... */
235 mtmsr r0 /* Update machine state */
242 * Do an IO access in real mode
260 * Do an IO access in real mode
277 #endif /* CONFIG_40x */
281 * Flush instruction cache.
282 * This is a no-op on the 601.
284 #ifndef CONFIG_PPC_8xx
285 _GLOBAL(flush_instruction_cache)
286 #if defined(CONFIG_4xx)
298 #elif CONFIG_FSL_BOOKE
301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
302 /* msync; isync recommended here */
306 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
312 rlwinm r3,r3,16,16,31
314 beqlr /* for 601, do nothing */
315 /* 603/604 processor - use invalidate-all bit in HID0 */
319 #endif /* CONFIG_4xx */
322 #endif /* CONFIG_PPC_8xx */
325 * Write any modified data cache blocks out to memory
326 * and invalidate the corresponding instruction cache blocks.
327 * This is a no-op on the 601.
329 * flush_icache_range(unsigned long start, unsigned long stop)
331 _KPROBE(flush_icache_range)
334 blr /* for 601, do nothing */
335 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
336 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
338 addi r4,r4,L1_CACHE_BYTES - 1
339 srwi. r4,r4,L1_CACHE_SHIFT
344 addi r3,r3,L1_CACHE_BYTES
346 sync /* wait for dcbst's to get to ram */
350 addi r6,r6,L1_CACHE_BYTES
353 /* Flash invalidate on 44x because we are passed kmapped addresses and
354 this doesn't work for userspace pages due to the virtually tagged
358 sync /* additional sync needed on g4 */
362 * Flush a particular page from the data cache to RAM.
363 * Note: this is necessary because the instruction cache does *not*
364 * snoop from the data cache.
365 * This is a no-op on the 601 which has a unified cache.
367 * void __flush_dcache_icache(void *page)
369 _GLOBAL(__flush_dcache_icache)
373 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
374 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
375 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
378 0: dcbst 0,r3 /* Write line to ram */
379 addi r3,r3,L1_CACHE_BYTES
383 /* We don't flush the icache on 44x. Those have a virtual icache
384 * and we don't have access to the virtual address here (it's
385 * not the page vaddr but where it's mapped in user space). The
386 * flushing of the icache on these is handled elsewhere, when
387 * a change in the address space occurs, before returning to
390 BEGIN_MMU_FTR_SECTION
392 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
393 #endif /* CONFIG_44x */
396 addi r6,r6,L1_CACHE_BYTES
404 * Flush a particular page from the data cache to RAM, identified
405 * by its physical address. We turn off the MMU so we can just use
406 * the physical address (this may be a highmem page without a kernel
409 * void __flush_dcache_icache_phys(unsigned long physaddr)
411 _GLOBAL(__flush_dcache_icache_phys)
414 blr /* for 601, do nothing */
415 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
417 rlwinm r0,r10,0,28,26 /* clear DR */
420 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
421 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
424 0: dcbst 0,r3 /* Write line to ram */
425 addi r3,r3,L1_CACHE_BYTES
430 addi r6,r6,L1_CACHE_BYTES
433 mtmsr r10 /* restore DR */
436 #endif /* CONFIG_BOOKE */
439 * Copy a whole page. We use the dcbz instruction on the destination
440 * to reduce memory traffic (it eliminates the unnecessary reads of
441 * the destination into cache). This requires that the destination
444 #define COPY_16_BYTES \
460 #if MAX_COPY_PREFETCH > 1
461 li r0,MAX_COPY_PREFETCH
465 addi r11,r11,L1_CACHE_BYTES
467 #else /* MAX_COPY_PREFETCH == 1 */
469 li r11,L1_CACHE_BYTES+4
470 #endif /* MAX_COPY_PREFETCH */
471 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
479 #if L1_CACHE_BYTES >= 32
481 #if L1_CACHE_BYTES >= 64
484 #if L1_CACHE_BYTES >= 128
494 crnot 4*cr0+eq,4*cr0+eq
495 li r0,MAX_COPY_PREFETCH
500 * Extended precision shifts.
502 * Updated to be valid for shift counts from 0 to 63 inclusive.
505 * R3/R4 has 64 bit value
509 * ashrdi3: arithmetic right shift (sign propagation)
510 * lshrdi3: logical right shift
511 * ashldi3: left shift
515 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
516 addi r7,r5,32 # could be xori, or addi with -32
517 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
518 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
519 sraw r7,r3,r7 # t2 = MSW >> (count-32)
520 or r4,r4,r6 # LSW |= t1
521 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
522 sraw r3,r3,r5 # MSW = MSW >> count
523 or r4,r4,r7 # LSW |= t2
528 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
529 addi r7,r5,32 # could be xori, or addi with -32
530 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
531 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
532 or r3,r3,r6 # MSW |= t1
533 slw r4,r4,r5 # LSW = LSW << count
534 or r3,r3,r7 # MSW |= t2
539 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
540 addi r7,r5,32 # could be xori, or addi with -32
541 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
542 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
543 or r4,r4,r6 # LSW |= t1
544 srw r3,r3,r5 # MSW = MSW >> count
545 or r4,r4,r7 # LSW |= t2
549 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
550 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
563 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
564 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
582 rlwimi r9,r4,24,16,23
583 rlwimi r10,r3,24,16,23
589 _GLOBAL(start_secondary_resume)
591 CURRENT_THREAD_INFO(r1, r1)
592 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
594 stw r3,0(r1) /* Zero the stack frame pointer */
597 #endif /* CONFIG_SMP */
600 * This routine is just here to keep GCC happy - sigh...
607 * Must be relocatable PIC code callable as a C function.
609 .globl relocate_new_kernel
612 /* r4 = reboot_code_buffer */
613 /* r5 = start_address */
615 #ifdef CONFIG_FSL_BOOKE
621 #define ENTRY_MAPPING_KEXEC_SETUP
622 #include "fsl_booke_entry_mapping.S"
623 #undef ENTRY_MAPPING_KEXEC_SETUP
630 #elif defined(CONFIG_44x)
632 /* Save our parameters */
637 #ifdef CONFIG_PPC_47x
638 /* Check for 47x cores */
641 cmplwi cr0,r3,PVR_476FPE@h
643 cmplwi cr0,r3,PVR_476@h
645 cmplwi cr0,r3,PVR_476_ISS@h
647 #endif /* CONFIG_PPC_47x */
650 * Code for setting up 1:1 mapping for PPC440x for KEXEC
652 * We cannot switch off the MMU on PPC44x.
654 * 1) Invalidate all the mappings except the one we are running from.
655 * 2) Create a tmp mapping for our code in the other address space(TS) and
656 * jump to it. Invalidate the entry we started in.
657 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
658 * 4) Jump to the 1:1 mapping in original TS.
659 * 5) Invalidate the tmp mapping.
661 * - Based on the kexec support code for FSL BookE
666 * Load the PID with kernel PID (0).
667 * Also load our MSR_IS and TID to MMUCR for TLB search.
674 oris r3,r3,PPC44x_MMUCR_STS@h
680 * Invalidate all the TLB entries except the current entry
681 * where we are running from
683 bl 0f /* Find our address */
684 0: mflr r5 /* Make it accessible */
685 tlbsx r23,0,r5 /* Find entry we are in */
686 li r4,0 /* Start at TLB entry 0 */
687 li r3,0 /* Set PAGEID inval value */
688 1: cmpw r23,r4 /* Is this our entry? */
689 beq skip /* If so, skip the inval */
690 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
692 addi r4,r4,1 /* Increment */
693 cmpwi r4,64 /* Are we done? */
694 bne 1b /* If not, repeat */
697 /* Create a temp mapping and jump to it */
698 andi. r6, r23, 1 /* Find the index to use */
699 addi r24, r6, 1 /* r24 will contain 1 or 2 */
701 mfmsr r9 /* get the MSR */
702 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
703 xori r7, r5, 1 /* Use the other address space */
705 /* Read the current mapping entries */
706 tlbre r3, r23, PPC44x_TLB_PAGEID
707 tlbre r4, r23, PPC44x_TLB_XLAT
708 tlbre r5, r23, PPC44x_TLB_ATTRIB
710 /* Save our current XLAT entry */
713 /* Extract the TLB PageSize */
714 li r10, 1 /* r10 will hold PageSize */
715 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
717 /* XXX: As of now we use 256M, 4K pages */
718 cmpwi r11, PPC44x_TLB_256M
720 rotlwi r10, r10, 28 /* r10 = 256M */
723 cmpwi r11, PPC44x_TLB_4K
725 rotlwi r10, r10, 12 /* r10 = 4K */
728 rotlwi r10, r10, 10 /* r10 = 1K */
732 * Write out the tmp 1:1 mapping for this code in other address space
733 * Fixup EPN = RPN , TS=other address space
735 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
737 /* Write out the tmp mapping entries */
738 tlbwe r3, r24, PPC44x_TLB_PAGEID
739 tlbwe r4, r24, PPC44x_TLB_XLAT
740 tlbwe r5, r24, PPC44x_TLB_ATTRIB
742 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
743 not r10, r11 /* Mask for PageNum */
745 /* Switch to other address space in MSR */
746 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
750 addi r8, r8, (2f-1b) /* Find the target offset */
752 /* Jump to the tmp mapping */
758 /* Invalidate the entry we were executing from */
760 tlbwe r3, r23, PPC44x_TLB_PAGEID
762 /* attribute fields. rwx for SUPERVISOR mode */
764 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
766 /* Create 1:1 mapping in 256M pages */
767 xori r7, r7, 1 /* Revert back to Original TS */
769 li r8, 0 /* PageNumber */
770 li r6, 3 /* TLB Index, start at 3 */
773 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
774 mr r4, r3 /* RPN = EPN */
775 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
776 insrwi r3, r7, 1, 23 /* Set TS from r7 */
778 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
779 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
780 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
782 addi r8, r8, 1 /* Increment PN */
783 addi r6, r6, 1 /* Increment TLB Index */
784 cmpwi r8, 8 /* Are we done ? */
788 /* Jump to the new mapping 1:1 */
790 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
794 and r8, r8, r11 /* Get our offset within page */
797 and r5, r25, r10 /* Get our target PageNum */
798 or r8, r8, r5 /* Target jump address */
804 /* Invalidate the tmp entry we used */
806 tlbwe r3, r24, PPC44x_TLB_PAGEID
810 #ifdef CONFIG_PPC_47x
812 /* 1:1 mapping for 47x */
817 * Load the kernel pid (0) to PID and also to MMUCR[TID].
818 * Also set the MSR IS->MMUCR STS
821 mtspr SPRN_PID, r3 /* Set PID */
822 mfmsr r4 /* Get MSR */
823 andi. r4, r4, MSR_IS@l /* TS=1? */
824 beq 1f /* If not, leave STS=0 */
825 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
826 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
829 /* Find the entry we are running from */
833 tlbre r24, r23, 0 /* TLB Word 0 */
834 tlbre r25, r23, 1 /* TLB Word 1 */
835 tlbre r26, r23, 2 /* TLB Word 2 */
839 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
840 * of 4k page size in all 4 ways (0-3 in r3).
841 * This would invalidate the entire UTLB including the one we are
842 * running from. However the shadow TLB entries would help us
843 * to continue the execution, until we flush them (rfi/isync).
845 addis r3, 0, 0x8000 /* specify the way */
846 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
850 /* Align the loop to speed things up. from head_44x.S */
858 addis r3, r3, 0x2000 /* Increment the way */
862 addis r4, r4, 0x100 /* Increment the EPN */
866 /* Create the entries in the other address space */
868 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
869 xori r7, r7, 1 /* r7 = !TS */
871 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
874 * write out the TLB entries for the tmp mapping
875 * Use way '0' so that we could easily invalidate it later.
877 lis r3, 0x8000 /* Way '0' */
883 /* Update the msr to the new TS */
895 * Now we are in the tmp address space.
896 * Create a 1:1 mapping for 0-2GiB in the original TS.
900 li r4, 0 /* TLB Word 0 */
901 li r5, 0 /* TLB Word 1 */
903 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
905 li r8, 0 /* PageIndex */
907 xori r7, r7, 1 /* revert back to original TS */
910 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
911 /* ERPN = 0 as we don't use memory above 2G */
913 mr r4, r5 /* EPN = RPN */
914 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
915 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
917 tlbwe r4, r3, 0 /* Write out the entries */
921 cmpwi r8, 8 /* Have we completed ? */
924 /* make sure we complete the TLB write up */
928 * Prepare to jump to the 1:1 mapping.
929 * 1) Extract page size of the tmp mapping
930 * DSIZ = TLB_Word0[22:27]
931 * 2) Calculate the physical address of the address
934 rlwinm r10, r24, 0, 22, 27
936 cmpwi r10, PPC47x_TLB0_4K
938 li r10, 0x1000 /* r10 = 4k */
942 /* Defaults to 256M */
947 addi r4, r4, (2f-1b) /* virtual address of 2f */
949 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
950 not r10, r11 /* Pagemask = ~(offsetmask) */
952 and r5, r25, r10 /* Physical page */
953 and r6, r4, r11 /* offset within the current page */
955 or r5, r5, r6 /* Physical address for 2f */
957 /* Switch the TS in MSR to the original one */
966 /* Invalidate the tmp mapping */
967 lis r3, 0x8000 /* Way '0' */
969 clrrwi r24, r24, 12 /* Clear the valid bit */
974 /* Make sure we complete the TLB write and flush the shadow TLB */
982 /* Restore the parameters */
992 * Set Machine Status Register to a known status,
993 * switch the MMU off and jump to 1: in a single step.
997 ori r8, r8, MSR_RI|MSR_ME
999 addi r8, r4, 1f - relocate_new_kernel
1006 /* from this point address translation is turned off */
1007 /* and interrupts are disabled */
1009 /* set a new stack at the bottom of our page... */
1010 /* (not really needed now) */
1011 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1015 li r6, 0 /* checksum */
1019 0: /* top, read another word for the indirection page */
1023 /* is it a destination page? (r8) */
1024 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1027 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1030 2: /* is it an indirection page? (r3) */
1031 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1034 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1038 2: /* are we done? */
1039 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1043 2: /* is it a source page? (r9) */
1044 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1047 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1049 li r7, PAGE_SIZE / 4
1054 lwzu r0, 4(r9) /* do the copy */
1068 /* To be certain of avoiding problems with self-modifying code
1069 * execute a serializing instruction here.
1074 mfspr r3, SPRN_PIR /* current core we are running on */
1075 mr r4, r5 /* load physical address of chunk called */
1077 /* jump to the entry point, usually the setup routine */
1083 relocate_new_kernel_end:
1085 .globl relocate_new_kernel_size
1086 relocate_new_kernel_size:
1087 .long relocate_new_kernel_end - relocate_new_kernel
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