arch/powerpc/kernel/pci-common.c

   1 /*
   2  * Contains common pci routines for ALL ppc platform
   3  * (based on pci_32.c and pci_64.c)
   4  *
   5  * Port for PPC64 David Engebretsen, IBM Corp.
   6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   7  *
   8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *   Rework, based on alpha PCI code.
  10  *
  11  * Common pmac/prep/chrp pci routines. -- Cort
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version
  16  * 2 of the License, or (at your option) any later version.
  17  */
  18
  19 #undef DEBUG
  20
  21 #include <linux/kernel.h>
  22 #include <linux/pci.h>
  23 #include <linux/string.h>
  24 #include <linux/init.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/mm.h>
  27 #include <linux/list.h>
  28 #include <linux/syscalls.h>
  29 #include <linux/irq.h>
  30 #include <linux/vmalloc.h>
  31
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34 #include <asm/prom.h>
  35 #include <asm/pci-bridge.h>
  36 #include <asm/byteorder.h>
  37 #include <asm/machdep.h>
  38 #include <asm/ppc-pci.h>
  39 #include <asm/firmware.h>
  40
  41 #ifdef DEBUG
  42 #include <asm/udbg.h>
  43 #define DBG(fmt...) printk(fmt)
  44 #else
  45 #define DBG(fmt...)
  46 #endif
  47
  48 static DEFINE_SPINLOCK(hose_spinlock);
  49
  50 /* XXX kill that some day ... */
  51 int global_phb_number;          /* Global phb counter */
  52
  53 extern struct list_head hose_list;
  54
  55 /*
  56  * pci_controller(phb) initialized common variables.
  57  */
  58 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
  59 {
  60         memset(hose, 0, sizeof(struct pci_controller));
  61
  62         spin_lock(&hose_spinlock);
  63         hose->global_number = global_phb_number++;
  64         list_add_tail(&hose->list_node, &hose_list);
  65         spin_unlock(&hose_spinlock);
  66 }
  67
  68 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
  69 {
  70         struct pci_controller *phb;
  71
  72         if (mem_init_done)
  73                 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
  74         else
  75                 phb = alloc_bootmem(sizeof (struct pci_controller));
  76         if (phb == NULL)
  77                 return NULL;
  78         pci_setup_pci_controller(phb);
  79         phb->arch_data = dev;
  80         phb->is_dynamic = mem_init_done;
  81 #ifdef CONFIG_PPC64
  82         if (dev) {
  83                 int nid = of_node_to_nid(dev);
  84
  85                 if (nid < 0 || !node_online(nid))
  86                         nid = -1;
  87
  88                 PHB_SET_NODE(phb, nid);
  89         }
  90 #endif
  91         return phb;
  92 }
  93
  94 void pcibios_free_controller(struct pci_controller *phb)
  95 {
  96         spin_lock(&hose_spinlock);
  97         list_del(&phb->list_node);
  98         spin_unlock(&hose_spinlock);
  99
 100         if (phb->is_dynamic)
 101                 kfree(phb);
 102 }
 103
 104 /*
 105  * Return the domain number for this bus.
 106  */
 107 int pci_domain_nr(struct pci_bus *bus)
 108 {
 109         if (firmware_has_feature(FW_FEATURE_ISERIES))
 110                 return 0;
 111         else {
 112                 struct pci_controller *hose = pci_bus_to_host(bus);
 113
 114                 return hose->global_number;
 115         }
 116 }
 117
 118 EXPORT_SYMBOL(pci_domain_nr);
 119
 120 #ifdef CONFIG_PPC_OF
 121
 122 /* This routine is meant to be used early during boot, when the
 123  * PCI bus numbers have not yet been assigned, and you need to
 124  * issue PCI config cycles to an OF device.
 125  * It could also be used to "fix" RTAS config cycles if you want
 126  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
 127  * config cycles.
 128  */
 129 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
 130 {
 131         if (!have_of)
 132                 return NULL;
 133         while(node) {
 134                 struct pci_controller *hose, *tmp;
 135                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
 136                         if (hose->arch_data == node)
 137                                 return hose;
 138                 node = node->parent;
 139         }
 140         return NULL;
 141 }
 142
 143 static ssize_t pci_show_devspec(struct device *dev,
 144                 struct device_attribute *attr, char *buf)
 145 {
 146         struct pci_dev *pdev;
 147         struct device_node *np;
 148
 149         pdev = to_pci_dev (dev);
 150         np = pci_device_to_OF_node(pdev);
 151         if (np == NULL || np->full_name == NULL)
 152                 return 0;
 153         return sprintf(buf, "%s", np->full_name);
 154 }
 155 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
 156 #endif /* CONFIG_PPC_OF */
 157
 158 /* Add sysfs properties */
 159 void pcibios_add_platform_entries(struct pci_dev *pdev)
 160 {
 161 #ifdef CONFIG_PPC_OF
 162         device_create_file(&pdev->dev, &dev_attr_devspec);
 163 #endif /* CONFIG_PPC_OF */
 164 }
 165
 166 char __init *pcibios_setup(char *str)
 167 {
 168         return str;
 169 }
 170
 171 /*
 172  * Reads the interrupt pin to determine if interrupt is use by card.
 173  * If the interrupt is used, then gets the interrupt line from the
 174  * openfirmware and sets it in the pci_dev and pci_config line.
 175  */
 176 int pci_read_irq_line(struct pci_dev *pci_dev)
 177 {
 178         struct of_irq oirq;
 179         unsigned int virq;
 180
 181         DBG("Try to map irq for %s...\n", pci_name(pci_dev));
 182
 183 #ifdef DEBUG
 184         memset(&oirq, 0xff, sizeof(oirq));
 185 #endif
 186         /* Try to get a mapping from the device-tree */
 187         if (of_irq_map_pci(pci_dev, &oirq)) {
 188                 u8 line, pin;
 189
 190                 /* If that fails, lets fallback to what is in the config
 191                  * space and map that through the default controller. We
 192                  * also set the type to level low since that's what PCI
 193                  * interrupts are. If your platform does differently, then
 194                  * either provide a proper interrupt tree or don't use this
 195                  * function.
 196                  */
 197                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
 198                         return -1;
 199                 if (pin == 0)
 200                         return -1;
 201                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
 202                     line == 0xff) {
 203                         return -1;
 204                 }
 205                 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
 206
 207                 virq = irq_create_mapping(NULL, line);
 208                 if (virq != NO_IRQ)
 209                         set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
 210         } else {
 211                 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
 212                     oirq.size, oirq.specifier[0], oirq.specifier[1],
 213                     oirq.controller->full_name);
 214
 215                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
 216                                              oirq.size);
 217         }
 218         if(virq == NO_IRQ) {
 219                 DBG(" -> failed to map !\n");
 220                 return -1;
 221         }
 222
 223         DBG(" -> mapped to linux irq %d\n", virq);
 224
 225         pci_dev->irq = virq;
 226
 227         return 0;
 228 }
 229 EXPORT_SYMBOL(pci_read_irq_line);
 230
 231 /*
 232  * Platform support for /proc/bus/pci/X/Y mmap()s,
 233  * modelled on the sparc64 implementation by Dave Miller.
 234  *  -- paulus.
 235  */
 236
 237 /*
 238  * Adjust vm_pgoff of VMA such that it is the physical page offset
 239  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 240  *
 241  * Basically, the user finds the base address for his device which he wishes
 242  * to mmap.  They read the 32-bit value from the config space base register,
 243  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 244  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 245  *
 246  * Returns negative error code on failure, zero on success.
 247  */
 248 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
 249                                                resource_size_t *offset,
 250                                                enum pci_mmap_state mmap_state)
 251 {
 252         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 253         unsigned long io_offset = 0;
 254         int i, res_bit;
 255
 256         if (hose == 0)
 257                 return NULL;            /* should never happen */
 258
 259         /* If memory, add on the PCI bridge address offset */
 260         if (mmap_state == pci_mmap_mem) {
 261 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
 262                 *offset += hose->pci_mem_offset;
 263 #endif
 264                 res_bit = IORESOURCE_MEM;
 265         } else {
 266                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 267                 *offset += io_offset;
 268                 res_bit = IORESOURCE_IO;
 269         }
 270
 271         /*
 272          * Check that the offset requested corresponds to one of the
 273          * resources of the device.
 274          */
 275         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 276                 struct resource *rp = &dev->resource[i];
 277                 int flags = rp->flags;
 278
 279                 /* treat ROM as memory (should be already) */
 280                 if (i == PCI_ROM_RESOURCE)
 281                         flags |= IORESOURCE_MEM;
 282
 283                 /* Active and same type? */
 284                 if ((flags & res_bit) == 0)
 285                         continue;
 286
 287                 /* In the range of this resource? */
 288                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
 289                         continue;
 290
 291                 /* found it! construct the final physical address */
 292                 if (mmap_state == pci_mmap_io)
 293                         *offset += hose->io_base_phys - io_offset;
 294                 return rp;
 295         }
 296
 297         return NULL;
 298 }
 299
 300 /*
 301  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 302  * device mapping.
 303  */
 304 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
 305                                       pgprot_t protection,
 306                                       enum pci_mmap_state mmap_state,
 307                                       int write_combine)
 308 {
 309         unsigned long prot = pgprot_val(protection);
 310
 311         /* Write combine is always 0 on non-memory space mappings. On
 312          * memory space, if the user didn't pass 1, we check for a
 313          * "prefetchable" resource. This is a bit hackish, but we use
 314          * this to workaround the inability of /sysfs to provide a write
 315          * combine bit
 316          */
 317         if (mmap_state != pci_mmap_mem)
 318                 write_combine = 0;
 319         else if (write_combine == 0) {
 320                 if (rp->flags & IORESOURCE_PREFETCH)
 321                         write_combine = 1;
 322         }
 323
 324         /* XXX would be nice to have a way to ask for write-through */
 325         prot |= _PAGE_NO_CACHE;
 326         if (write_combine)
 327                 prot &= ~_PAGE_GUARDED;
 328         else
 329                 prot |= _PAGE_GUARDED;
 330
 331         return __pgprot(prot);
 332 }
 333
 334 /*
 335  * This one is used by /dev/mem and fbdev who have no clue about the
 336  * PCI device, it tries to find the PCI device first and calls the
 337  * above routine
 338  */
 339 pgprot_t pci_phys_mem_access_prot(struct file *file,
 340                                   unsigned long pfn,
 341                                   unsigned long size,
 342                                   pgprot_t protection)
 343 {
 344         struct pci_dev *pdev = NULL;
 345         struct resource *found = NULL;
 346         unsigned long prot = pgprot_val(protection);
 347         unsigned long offset = pfn << PAGE_SHIFT;
 348         int i;
 349
 350         if (page_is_ram(pfn))
 351                 return __pgprot(prot);
 352
 353         prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
 354
 355         for_each_pci_dev(pdev) {
 356                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 357                         struct resource *rp = &pdev->resource[i];
 358                         int flags = rp->flags;
 359
 360                         /* Active and same type? */
 361                         if ((flags & IORESOURCE_MEM) == 0)
 362                                 continue;
 363                         /* In the range of this resource? */
 364                         if (offset < (rp->start & PAGE_MASK) ||
 365                             offset > rp->end)
 366                                 continue;
 367                         found = rp;
 368                         break;
 369                 }
 370                 if (found)
 371                         break;
 372         }
 373         if (found) {
 374                 if (found->flags & IORESOURCE_PREFETCH)
 375                         prot &= ~_PAGE_GUARDED;
 376                 pci_dev_put(pdev);
 377         }
 378
 379         DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
 380
 381         return __pgprot(prot);
 382 }
 383
 384
 385 /*
 386  * Perform the actual remap of the pages for a PCI device mapping, as
 387  * appropriate for this architecture.  The region in the process to map
 388  * is described by vm_start and vm_end members of VMA, the base physical
 389  * address is found in vm_pgoff.
 390  * The pci device structure is provided so that architectures may make mapping
 391  * decisions on a per-device or per-bus basis.
 392  *
 393  * Returns a negative error code on failure, zero on success.
 394  */
 395 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 396                         enum pci_mmap_state mmap_state, int write_combine)
 397 {
 398         resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
 399         struct resource *rp;
 400         int ret;
 401
 402         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
 403         if (rp == NULL)
 404                 return -EINVAL;
 405
 406         vma->vm_pgoff = offset >> PAGE_SHIFT;
 407         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
 408                                                   vma->vm_page_prot,
 409                                                   mmap_state, write_combine);
 410
 411         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 412                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
 413
 414         return ret;
 415 }
 416
 417 void pci_resource_to_user(const struct pci_dev *dev, int bar,
 418                           const struct resource *rsrc,
 419                           resource_size_t *start, resource_size_t *end)
 420 {
 421         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 422         resource_size_t offset = 0;
 423
 424         if (hose == NULL)
 425                 return;
 426
 427         if (rsrc->flags & IORESOURCE_IO)
 428                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 429
 430         /* We pass a fully fixed up address to userland for MMIO instead of
 431          * a BAR value because X is lame and expects to be able to use that
 432          * to pass to /dev/mem !
 433          *
 434          * That means that we'll have potentially 64 bits values where some
 435          * userland apps only expect 32 (like X itself since it thinks only
 436          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
 437          * 32 bits CHRPs :-(
 438          *
 439          * Hopefully, the sysfs insterface is immune to that gunk. Once X
 440          * has been fixed (and the fix spread enough), we can re-enable the
 441          * 2 lines below and pass down a BAR value to userland. In that case
 442          * we'll also have to re-enable the matching code in
 443          * __pci_mmap_make_offset().
 444          *
 445          * BenH.
 446          */
 447 #if 0
 448         else if (rsrc->flags & IORESOURCE_MEM)
 449                 offset = hose->pci_mem_offset;
 450 #endif
 451
 452         *start = rsrc->start - offset;
 453         *end = rsrc->end - offset;
 454 }